osc32kctrl: implement CONF_SLCDCTRL_SRC setting

diff --git a/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c b/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c
index b6c624ccd73848a5f69665a0ad7ddf08467e7742..e69e916d2e8a28ceb1fdab2860dad50c7a22bdef 100644 (file)
--- a/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c
+++ b/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c
@@ -82,5 +82,7 @@ void _osc32kctrl_init_sources(void)
 #endif
 
        hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+       hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(hw, CONF_SLCDCTRL_SRC);
+
        (void)calib;
 }

diff --git a/watch-library/shared/config/hpl_osc32kctrl_config.h b/watch-library/shared/config/hpl_osc32kctrl_config.h
index 540f1c60e9af1e51f0b809b7effc3bc89daeb2fd..a77800e90526d650c3a983ce4e92bdbf58d028a2 100644 (file)
--- a/watch-library/shared/config/hpl_osc32kctrl_config.h
+++ b/watch-library/shared/config/hpl_osc32kctrl_config.h
@@ -50,12 +50,12 @@
 
 // <h> SLCD source control
 // <y> SLCD Clock Source Selection
-// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
-// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <0> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <1> 32kHz External Crystal Oscillator (XOSC32K)
 // <i> This defines the clock source for SLCD
 // <id> slcd_source_oscillator
 #ifndef CONF_SLCDCTRL_SRC
-#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_SLCDCTRL_SRC 0
 #endif
 
 // </h>