Merge PR #450 - sync after enabling RTC

According to the data sheet, writing to a Control A register's ENABLE
bit will trigger write synchronization and set SYNCBUSY's ENABLE bit
which will be automatically cleared by the hardware once the write
operation is complete.

It is necessary to wait until SYNCBUSY's ENABLE bit is clear.
Reading synchronized registers before that returns previous values.
Writing synchronized registers before that drops the write and generates
an error value in another register.

The data sheet recommends polling the ENABLE bit in this situation.

Reviewed-by: Matheus Afonso Martins Moreira <matheus@matheusmoreira.com>
GitHub-Pull-Request: https://github.com/joeycastillo/Sensor-Watch/pull/450
References: SAM L22 Family Data Sheet §§ 14.3.2, 14.3.3, 14.3.4, 14.3.5