From: Joey Castillo <jose.castillo@gmail.com>
Date: Mon, 26 Apr 2021 02:43:47 +0000 (-0400)
Subject: WIP simple C-based library for hacking on the watch
X-Git-Url: https://git.earman.xyz/?a=commitdiff_plain;h=efd1e8a1238af8eea53afa0d5acac071d73d1ea5;p=sensor-watch.git

WIP simple C-based library for hacking on the watch
---

diff --git a/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf b/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf
new file mode 100644
index 0000000..4b12c8d
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf	
@@ -0,0 +1,6 @@
+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAML22J18A" name="SAML22_DFP" vendor="Atmel" version="1.2.77"/>
+  </device-packs>
+</environment>
diff --git a/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc b/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc
new file mode 100644
index 0000000..563240f
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc	
@@ -0,0 +1,242 @@
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Atmel</vendor>
+  <name>My Project</name>
+  <description>Project generated by Atmel Start</description>
+  <url>http://start.atmel.com/</url>
+  <releases>
+    <release version="1.0.1">Initial version</release>
+  </releases>
+  <taxonomy>
+    <description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
+  </taxonomy>
+  <generators>
+    <generator id="AtmelStart">
+      <description>Atmel Start</description>
+      <select Dname="ATSAML22J18A" Dvendor="Atmel:3"/>
+      <command>http://start.atmel.com/</command>
+      <files>
+        <file category="generator" name="atmel_start_config.atstart"/>
+        <file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
+      </files>
+    </generator>
+  </generators>
+  <conditions>
+    <condition id="CMSIS Device Startup">
+      <description>Dependency on CMSIS core and Device Startup components</description>
+      <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
+      <require Cclass="Device" Cgroup="Startup" Cversion="1.2.0"/>
+    </condition>
+    <condition id="ARMCC, GCC, IAR">
+      <require Dname="ATSAML22J18A"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+    <condition id="GCC">
+      <require Dname="ATSAML22J18A"/>
+      <accept Tcompiler="GCC"/>
+    </condition>
+  </conditions>
+  <components generator="AtmelStart">
+    <component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
+      <description>Atmel Start Framework</description>
+      <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
+      <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/calendar.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/slcd_sync.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_calendar.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_slcd_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_slcd.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_slcd_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_slcd_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_decrement_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_recursion_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mtb_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvic_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_slcd_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systemcontrol_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systick_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_l22.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_l22.h"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/sleep_manager.rst"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="sleep_manager/sleep_manager.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="sleep_manager/sleep_manager.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_calendar.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_calendar.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm_14_seg_mapping.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm_7_seg_mapping.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/hpl_tc_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="sleep_manager_main.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="sleep_manager_main.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_rtc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_slcd_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/sleep_manager_config.h"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/rtc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/slcd"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/tcc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="sleep_manager"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+      </files>
+    </component>
+  </components>
+</package>
diff --git a/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart b/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart
new file mode 100644
index 0000000..0e0d365
--- /dev/null
+++ b/Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart	
@@ -0,0 +1,1698 @@
+format_version: '2'
+name: My Project
+versions:
+  api: '1.0'
+  backend: 1.8.543
+  commit: 931b2422bde1a793dea853de68547f48bf245b0f
+  content: unknown
+  content_pack_name: unknown
+  format: '2'
+  frontend: 1.8.543
+  packs_version_avr8: 1.0.1457
+  packs_version_qtouch: unknown
+  packs_version_sam: 1.0.1726
+  version_backend: 1.8.543
+  version_frontend: ''
+board:
+  identifier: CustomBoard
+  device: SAML22J18A-AN
+details: null
+application: null
+middlewares:
+  SLEEP_MANAGER_0:
+    user_label: SLEEP_MANAGER_0
+    configuration: {}
+    definition: Atmel:Sleep_Manager:0.0.1::Sleep_manager
+    functionality: Sleep_Manager
+    api: Sleep-Manager:Sleep-Manager:API
+    dependencies: {}
+drivers:
+  ADC_0:
+    user_label: ADC_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+    functionality: ADC
+    api: HAL:Driver:ADC_Sync
+    configuration:
+      adc_advanced_settings: false
+      adc_arch_adjres: 0
+      adc_arch_corren: false
+      adc_arch_dbgrun: false
+      adc_arch_event_settings: false
+      adc_arch_flushei: false
+      adc_arch_flushinv: false
+      adc_arch_gaincorr: 0
+      adc_arch_leftadj: false
+      adc_arch_offcomp: false
+      adc_arch_offsetcorr: 0
+      adc_arch_ondemand: false
+      adc_arch_refcomp: false
+      adc_arch_resrdyeo: false
+      adc_arch_runstdby: false
+      adc_arch_samplen: 0
+      adc_arch_samplenum: 1 sample
+      adc_arch_seqen: 0
+      adc_arch_startei: false
+      adc_arch_startinv: false
+      adc_arch_winlt: 0
+      adc_arch_winmode: No window mode
+      adc_arch_winmoneo: false
+      adc_arch_winut: 0
+      adc_differential_mode: false
+      adc_freerunning_mode: false
+      adc_pinmux_negative: ADC AIN0 pin
+      adc_pinmux_positive: ADC AIN0 pin
+      adc_prescaler: Peripheral clock divided by 2
+      adc_reference: Internal bandgap reference
+      adc_resolution: 12-bit
+    optional_signals:
+    - identifier: ADC_0:AIN/9
+      pad: PB01
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.9
+      name: ADC/AIN/9
+      label: AIN/9
+    - identifier: ADC_0:AIN/10
+      pad: PB02
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.10
+      name: ADC/AIN/10
+      label: AIN/10
+    - identifier: ADC_0:AIN/12
+      pad: PB04
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.12
+      name: ADC/AIN/12
+      label: AIN/12
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: ADC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          adc_gclk_selection: Generic clock generator 0
+  DMAC:
+    user_label: DMAC
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
+    functionality: System
+    api: HAL:HPL:DMAC
+    configuration:
+      dmac_beatsize_0: 8-bit bus transfer
+      dmac_beatsize_1: 8-bit bus transfer
+      dmac_beatsize_10: 8-bit bus transfer
+      dmac_beatsize_11: 8-bit bus transfer
+      dmac_beatsize_12: 8-bit bus transfer
+      dmac_beatsize_13: 8-bit bus transfer
+      dmac_beatsize_14: 8-bit bus transfer
+      dmac_beatsize_15: 8-bit bus transfer
+      dmac_beatsize_2: 8-bit bus transfer
+      dmac_beatsize_3: 8-bit bus transfer
+      dmac_beatsize_4: 8-bit bus transfer
+      dmac_beatsize_5: 8-bit bus transfer
+      dmac_beatsize_6: 8-bit bus transfer
+      dmac_beatsize_7: 8-bit bus transfer
+      dmac_beatsize_8: 8-bit bus transfer
+      dmac_beatsize_9: 8-bit bus transfer
+      dmac_blockact_0: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_1: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_10: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_11: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_12: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_13: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_14: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_15: Channel will be disabled if it is the last block transfer
+        in the transaction
+      dmac_blockact_2: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_3: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_4: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_5: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_6: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_7: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_8: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_blockact_9: Channel will be disabled if it is the last block transfer in
+        the transaction
+      dmac_channel_0_settings: false
+      dmac_channel_10_settings: false
+      dmac_channel_11_settings: false
+      dmac_channel_12_settings: false
+      dmac_channel_13_settings: false
+      dmac_channel_14_settings: false
+      dmac_channel_15_settings: false
+      dmac_channel_1_settings: false
+      dmac_channel_2_settings: false
+      dmac_channel_3_settings: false
+      dmac_channel_4_settings: false
+      dmac_channel_5_settings: false
+      dmac_channel_6_settings: false
+      dmac_channel_7_settings: false
+      dmac_channel_8_settings: false
+      dmac_channel_9_settings: false
+      dmac_dbgrun: false
+      dmac_dqos: Background (no sensitive operation)
+      dmac_dstinc_0: false
+      dmac_dstinc_1: false
+      dmac_dstinc_10: false
+      dmac_dstinc_11: false
+      dmac_dstinc_12: false
+      dmac_dstinc_13: false
+      dmac_dstinc_14: false
+      dmac_dstinc_15: false
+      dmac_dstinc_2: false
+      dmac_dstinc_3: false
+      dmac_dstinc_4: false
+      dmac_dstinc_5: false
+      dmac_dstinc_6: false
+      dmac_dstinc_7: false
+      dmac_dstinc_8: false
+      dmac_dstinc_9: false
+      dmac_enable: false
+      dmac_enable_0: false
+      dmac_enable_1: false
+      dmac_enable_10: false
+      dmac_enable_11: false
+      dmac_enable_12: false
+      dmac_enable_13: false
+      dmac_enable_14: false
+      dmac_enable_15: false
+      dmac_enable_2: false
+      dmac_enable_3: false
+      dmac_enable_4: false
+      dmac_enable_5: false
+      dmac_enable_6: false
+      dmac_enable_7: false
+      dmac_enable_8: false
+      dmac_enable_9: false
+      dmac_evact_0: No action
+      dmac_evact_1: No action
+      dmac_evact_10: No action
+      dmac_evact_11: No action
+      dmac_evact_12: No action
+      dmac_evact_13: No action
+      dmac_evact_14: No action
+      dmac_evact_15: No action
+      dmac_evact_2: No action
+      dmac_evact_3: No action
+      dmac_evact_4: No action
+      dmac_evact_5: No action
+      dmac_evact_6: No action
+      dmac_evact_7: No action
+      dmac_evact_8: No action
+      dmac_evact_9: No action
+      dmac_evie_0: false
+      dmac_evie_1: false
+      dmac_evie_10: false
+      dmac_evie_11: false
+      dmac_evie_12: false
+      dmac_evie_13: false
+      dmac_evie_14: false
+      dmac_evie_15: false
+      dmac_evie_2: false
+      dmac_evie_3: false
+      dmac_evie_4: false
+      dmac_evie_5: false
+      dmac_evie_6: false
+      dmac_evie_7: false
+      dmac_evie_8: false
+      dmac_evie_9: false
+      dmac_evoe_0: false
+      dmac_evoe_1: false
+      dmac_evoe_10: false
+      dmac_evoe_11: false
+      dmac_evoe_12: false
+      dmac_evoe_13: false
+      dmac_evoe_14: false
+      dmac_evoe_15: false
+      dmac_evoe_2: false
+      dmac_evoe_3: false
+      dmac_evoe_4: false
+      dmac_evoe_5: false
+      dmac_evoe_6: false
+      dmac_evoe_7: false
+      dmac_evoe_8: false
+      dmac_evoe_9: false
+      dmac_evosel_0: Event generation disabled
+      dmac_evosel_1: Event generation disabled
+      dmac_evosel_10: Event generation disabled
+      dmac_evosel_11: Event generation disabled
+      dmac_evosel_12: Event generation disabled
+      dmac_evosel_13: Event generation disabled
+      dmac_evosel_14: Event generation disabled
+      dmac_evosel_15: Event generation disabled
+      dmac_evosel_2: Event generation disabled
+      dmac_evosel_3: Event generation disabled
+      dmac_evosel_4: Event generation disabled
+      dmac_evosel_5: Event generation disabled
+      dmac_evosel_6: Event generation disabled
+      dmac_evosel_7: Event generation disabled
+      dmac_evosel_8: Event generation disabled
+      dmac_evosel_9: Event generation disabled
+      dmac_fqos: Background (no sensitive operation)
+      dmac_lvl_0: Channel priority 0
+      dmac_lvl_1: Channel priority 0
+      dmac_lvl_10: Channel priority 0
+      dmac_lvl_11: Channel priority 0
+      dmac_lvl_12: Channel priority 0
+      dmac_lvl_13: Channel priority 0
+      dmac_lvl_14: Channel priority 0
+      dmac_lvl_15: Channel priority 0
+      dmac_lvl_2: Channel priority 0
+      dmac_lvl_3: Channel priority 0
+      dmac_lvl_4: Channel priority 0
+      dmac_lvl_5: Channel priority 0
+      dmac_lvl_6: Channel priority 0
+      dmac_lvl_7: Channel priority 0
+      dmac_lvl_8: Channel priority 0
+      dmac_lvl_9: Channel priority 0
+      dmac_lvlen0: false
+      dmac_lvlen1: false
+      dmac_lvlen2: false
+      dmac_lvlen3: false
+      dmac_lvlpri0: 0
+      dmac_lvlpri1: 0
+      dmac_lvlpri2: 0
+      dmac_lvlpri3: 0
+      dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
+      dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
+      dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
+      dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
+      dmac_runstdby_0: false
+      dmac_runstdby_1: false
+      dmac_runstdby_10: false
+      dmac_runstdby_11: false
+      dmac_runstdby_12: false
+      dmac_runstdby_13: false
+      dmac_runstdby_14: false
+      dmac_runstdby_15: false
+      dmac_runstdby_2: false
+      dmac_runstdby_3: false
+      dmac_runstdby_4: false
+      dmac_runstdby_5: false
+      dmac_runstdby_6: false
+      dmac_runstdby_7: false
+      dmac_runstdby_8: false
+      dmac_runstdby_9: false
+      dmac_srcinc_0: false
+      dmac_srcinc_1: false
+      dmac_srcinc_10: false
+      dmac_srcinc_11: false
+      dmac_srcinc_12: false
+      dmac_srcinc_13: false
+      dmac_srcinc_14: false
+      dmac_srcinc_15: false
+      dmac_srcinc_2: false
+      dmac_srcinc_3: false
+      dmac_srcinc_4: false
+      dmac_srcinc_5: false
+      dmac_srcinc_6: false
+      dmac_srcinc_7: false
+      dmac_srcinc_8: false
+      dmac_srcinc_9: false
+      dmac_stepsel_0: Step size settings apply to the destination address
+      dmac_stepsel_1: Step size settings apply to the destination address
+      dmac_stepsel_10: Step size settings apply to the destination address
+      dmac_stepsel_11: Step size settings apply to the destination address
+      dmac_stepsel_12: Step size settings apply to the destination address
+      dmac_stepsel_13: Step size settings apply to the destination address
+      dmac_stepsel_14: Step size settings apply to the destination address
+      dmac_stepsel_15: Step size settings apply to the destination address
+      dmac_stepsel_2: Step size settings apply to the destination address
+      dmac_stepsel_3: Step size settings apply to the destination address
+      dmac_stepsel_4: Step size settings apply to the destination address
+      dmac_stepsel_5: Step size settings apply to the destination address
+      dmac_stepsel_6: Step size settings apply to the destination address
+      dmac_stepsel_7: Step size settings apply to the destination address
+      dmac_stepsel_8: Step size settings apply to the destination address
+      dmac_stepsel_9: Step size settings apply to the destination address
+      dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1
+      dmac_trifsrc_0: Only software/event triggers
+      dmac_trifsrc_1: Only software/event triggers
+      dmac_trifsrc_10: Only software/event triggers
+      dmac_trifsrc_11: Only software/event triggers
+      dmac_trifsrc_12: Only software/event triggers
+      dmac_trifsrc_13: Only software/event triggers
+      dmac_trifsrc_14: Only software/event triggers
+      dmac_trifsrc_15: Only software/event triggers
+      dmac_trifsrc_2: Only software/event triggers
+      dmac_trifsrc_3: Only software/event triggers
+      dmac_trifsrc_4: Only software/event triggers
+      dmac_trifsrc_5: Only software/event triggers
+      dmac_trifsrc_6: Only software/event triggers
+      dmac_trifsrc_7: Only software/event triggers
+      dmac_trifsrc_8: Only software/event triggers
+      dmac_trifsrc_9: Only software/event triggers
+      dmac_trigact_0: One trigger required for each block transfer
+      dmac_trigact_1: One trigger required for each block transfer
+      dmac_trigact_10: One trigger required for each block transfer
+      dmac_trigact_11: One trigger required for each block transfer
+      dmac_trigact_12: One trigger required for each block transfer
+      dmac_trigact_13: One trigger required for each block transfer
+      dmac_trigact_14: One trigger required for each block transfer
+      dmac_trigact_15: One trigger required for each block transfer
+      dmac_trigact_2: One trigger required for each block transfer
+      dmac_trigact_3: One trigger required for each block transfer
+      dmac_trigact_4: One trigger required for each block transfer
+      dmac_trigact_5: One trigger required for each block transfer
+      dmac_trigact_6: One trigger required for each block transfer
+      dmac_trigact_7: One trigger required for each block transfer
+      dmac_trigact_8: One trigger required for each block transfer
+      dmac_trigact_9: One trigger required for each block transfer
+      dmac_wrbqos: Background (no sensitive operation)
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  EXTERNAL_IRQ_0:
+    user_label: EXTERNAL_IRQ_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ
+    functionality: External_IRQ
+    api: HAL:Driver:Ext_IRQ
+    configuration:
+      eic_arch_asynch0: false
+      eic_arch_asynch1: false
+      eic_arch_asynch10: false
+      eic_arch_asynch11: false
+      eic_arch_asynch12: false
+      eic_arch_asynch13: false
+      eic_arch_asynch14: false
+      eic_arch_asynch15: false
+      eic_arch_asynch2: false
+      eic_arch_asynch3: false
+      eic_arch_asynch4: false
+      eic_arch_asynch5: false
+      eic_arch_asynch6: false
+      eic_arch_asynch7: false
+      eic_arch_asynch8: false
+      eic_arch_asynch9: false
+      eic_arch_cksel: Clocked by GCLK
+      eic_arch_enable_irq_setting0: false
+      eic_arch_enable_irq_setting1: false
+      eic_arch_enable_irq_setting10: false
+      eic_arch_enable_irq_setting11: false
+      eic_arch_enable_irq_setting12: false
+      eic_arch_enable_irq_setting13: false
+      eic_arch_enable_irq_setting14: false
+      eic_arch_enable_irq_setting15: false
+      eic_arch_enable_irq_setting2: false
+      eic_arch_enable_irq_setting3: false
+      eic_arch_enable_irq_setting4: false
+      eic_arch_enable_irq_setting5: true
+      eic_arch_enable_irq_setting6: true
+      eic_arch_enable_irq_setting7: true
+      eic_arch_enable_irq_setting8: false
+      eic_arch_enable_irq_setting9: false
+      eic_arch_extinteo0: false
+      eic_arch_extinteo1: false
+      eic_arch_extinteo10: false
+      eic_arch_extinteo11: false
+      eic_arch_extinteo12: false
+      eic_arch_extinteo13: false
+      eic_arch_extinteo14: false
+      eic_arch_extinteo15: false
+      eic_arch_extinteo2: false
+      eic_arch_extinteo3: false
+      eic_arch_extinteo4: false
+      eic_arch_extinteo5: false
+      eic_arch_extinteo6: false
+      eic_arch_extinteo7: false
+      eic_arch_extinteo8: false
+      eic_arch_extinteo9: false
+      eic_arch_filten0: false
+      eic_arch_filten1: false
+      eic_arch_filten10: false
+      eic_arch_filten11: false
+      eic_arch_filten12: false
+      eic_arch_filten13: false
+      eic_arch_filten14: false
+      eic_arch_filten15: false
+      eic_arch_filten2: false
+      eic_arch_filten3: false
+      eic_arch_filten4: false
+      eic_arch_filten5: false
+      eic_arch_filten6: false
+      eic_arch_filten7: false
+      eic_arch_filten8: false
+      eic_arch_filten9: false
+      eic_arch_nmi_ctrl: false
+      eic_arch_nmiasynch: false
+      eic_arch_nmifilten: false
+      eic_arch_nmisense: No detection
+      eic_arch_sense0: No detection
+      eic_arch_sense1: No detection
+      eic_arch_sense10: No detection
+      eic_arch_sense11: No detection
+      eic_arch_sense12: No detection
+      eic_arch_sense13: No detection
+      eic_arch_sense14: No detection
+      eic_arch_sense15: No detection
+      eic_arch_sense2: No detection
+      eic_arch_sense3: No detection
+      eic_arch_sense4: No detection
+      eic_arch_sense5: Rising-edge detection
+      eic_arch_sense6: Rising-edge detection
+      eic_arch_sense7: Rising-edge detection
+      eic_arch_sense8: No detection
+      eic_arch_sense9: No detection
+    optional_signals:
+    - identifier: EXTERNAL_IRQ_0:EXTINT/5
+      pad: PB05
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.5
+      name: EIC/EXTINT/5
+      label: EXTINT/5
+    - identifier: EXTERNAL_IRQ_0:EXTINT/6
+      pad: PA22
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.6
+      name: EIC/EXTINT/6
+      label: EXTINT/6
+    - identifier: EXTERNAL_IRQ_0:EXTINT/7
+      pad: PA23
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.7
+      name: EIC/EXTINT/7
+      label: EXTINT/7
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: EIC
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          eic_gclk_selection: Generic clock generator 3
+  GCLK:
+    user_label: GCLK
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
+    functionality: System
+    api: HAL:HPL:GCLK
+    configuration:
+      $input: 400000
+      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+      RESERVED_InputFreq: 400000
+      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+      _$freq_output_Generic clock generator 0: 4000000
+      _$freq_output_Generic clock generator 1: 400000
+      _$freq_output_Generic clock generator 2: 400000
+      _$freq_output_Generic clock generator 3: 32768
+      _$freq_output_Generic clock generator 4: 400000
+      enable_gclk_gen_0: true
+      enable_gclk_gen_0__externalclock: 1000000
+      enable_gclk_gen_1: false
+      enable_gclk_gen_1__externalclock: 1000000
+      enable_gclk_gen_2: false
+      enable_gclk_gen_2__externalclock: 1000000
+      enable_gclk_gen_3: true
+      enable_gclk_gen_3__externalclock: 1000000
+      enable_gclk_gen_4: false
+      enable_gclk_gen_4__externalclock: 1000000
+      gclk_arch_gen_0_enable: true
+      gclk_arch_gen_0_idc: false
+      gclk_arch_gen_0_oe: false
+      gclk_arch_gen_0_oov: false
+      gclk_arch_gen_0_runstdby: false
+      gclk_arch_gen_1_enable: false
+      gclk_arch_gen_1_idc: false
+      gclk_arch_gen_1_oe: false
+      gclk_arch_gen_1_oov: false
+      gclk_arch_gen_1_runstdby: false
+      gclk_arch_gen_2_enable: false
+      gclk_arch_gen_2_idc: false
+      gclk_arch_gen_2_oe: false
+      gclk_arch_gen_2_oov: false
+      gclk_arch_gen_2_runstdby: false
+      gclk_arch_gen_3_enable: true
+      gclk_arch_gen_3_idc: true
+      gclk_arch_gen_3_oe: false
+      gclk_arch_gen_3_oov: false
+      gclk_arch_gen_3_runstdby: true
+      gclk_arch_gen_4_enable: false
+      gclk_arch_gen_4_idc: false
+      gclk_arch_gen_4_oe: false
+      gclk_arch_gen_4_oov: false
+      gclk_arch_gen_4_runstdby: false
+      gclk_gen_0_div: 1
+      gclk_gen_0_div_sel: false
+      gclk_gen_0_oscillator: 16MHz Internal Oscillator (OSC16M)
+      gclk_gen_1_div: 1
+      gclk_gen_1_div_sel: false
+      gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+      gclk_gen_2_div: 1
+      gclk_gen_2_div_sel: false
+      gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+      gclk_gen_3_div: 1
+      gclk_gen_3_div_sel: false
+      gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+      gclk_gen_4_div: 1
+      gclk_gen_4_div_sel: false
+      gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  MCLK:
+    user_label: MCLK
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
+    functionality: System
+    api: HAL:HPL:MCLK
+    configuration:
+      $input: 4000000
+      $input_id: Generic clock generator 0
+      RESERVED_InputFreq: 4000000
+      RESERVED_InputFreq_id: Generic clock generator 0
+      _$freq_output_CPU: 4000000
+      cpu_clock_source: Generic clock generator 0
+      cpu_div: '1'
+      enable_cpu_clock: true
+      mclk_arch_bupdiv: Divide by 8
+      nvm_wait_states: '0'
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: CPU
+          input: CPU
+          external: false
+          external_frequency: 0
+        configuration: {}
+  OSC32KCTRL:
+    user_label: OSC32KCTRL
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
+    functionality: System
+    api: HAL:HPL:OSC32KCTRL
+    configuration:
+      $input: 32768
+      $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+      RESERVED_InputFreq: 32768
+      RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+      _$freq_output_RTC source: 1024
+      enable_osculp32k: true
+      enable_rtc_source: false
+      enable_slcd_source: false
+      enable_xosc32k: true
+      osculp32k_calib: 0
+      osculp32k_calib_enable: false
+      rtc_1khz_selection: true
+      rtc_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+      slcd_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+      xosc32k_arch_cfden: false
+      xosc32k_arch_cfdeo: false
+      xosc32k_arch_en1k: true
+      xosc32k_arch_en32k: true
+      xosc32k_arch_enable: true
+      xosc32k_arch_ondemand: true
+      xosc32k_arch_runstdby: false
+      xosc32k_arch_startup: 62592us
+      xosc32k_arch_swben: false
+      xosc32k_arch_xtalen: true
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  OSCCTRL:
+    user_label: OSCCTRL
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
+    functionality: System
+    api: HAL:HPL:OSCCTRL
+    configuration:
+      $input: 32768
+      $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+      RESERVED_InputFreq: 32768
+      RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+      _$freq_output_16MHz Internal Oscillator (OSC16M): 4000000
+      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
+      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976
+      dfll48m_arch_enable: false
+      dfll48m_mode: Open Loop Mode
+      dfll48m_mul: 0
+      dfll48m_ref_clock: Generic clock generator 3
+      dfll_arch_bplckc: false
+      dfll_arch_calibration: false
+      dfll_arch_ccdis: false
+      dfll_arch_coarse: 31
+      dfll_arch_cstep: 1
+      dfll_arch_fine: 512
+      dfll_arch_fstep: 1
+      dfll_arch_llaw: false
+      dfll_arch_ondemand: true
+      dfll_arch_qldis: false
+      dfll_arch_runstdby: false
+      dfll_arch_stable: false
+      dfll_arch_usbcrm: false
+      dfll_arch_waitlock: false
+      enable_dfll48m: false
+      enable_fdpll96m: false
+      enable_osc16m: true
+      enable_xosc: false
+      fdpll96m_arch_enable: false
+      fdpll96m_arch_filter: Default filter mode
+      fdpll96m_arch_lbypass: false
+      fdpll96m_arch_lpen: false
+      fdpll96m_arch_ltime: No time-out, automatic lock
+      fdpll96m_arch_ondemand: true
+      fdpll96m_arch_refclk: XOSC32K clock reference
+      fdpll96m_arch_runstdby: false
+      fdpll96m_arch_wuf: false
+      fdpll96m_clock_div: 0
+      fdpll96m_ldr: 1463
+      fdpll96m_ldrfrac: 13
+      fdpll96m_presc: '1'
+      fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)
+      osc16m_arch_12m_fcal: 0
+      osc16m_arch_12m_tcal: 0
+      osc16m_arch_16m_tcal: 0
+      osc16m_arch_4m_fcal: 0
+      osc16m_arch_4m_tcal: 0
+      osc16m_arch_8m_fcal: 0
+      osc16m_arch_8m_tcal: 0
+      osc16m_arch_calib_enable: false
+      osc16m_arch_enable: true
+      osc16m_arch_fcal: 0
+      osc16m_arch_ondemand: true
+      osc16m_arch_runstdby: false
+      osc16m_freq: '4'
+      xosc_arch_ampgc: false
+      xosc_arch_cfden: false
+      xosc_arch_cfdeo: false
+      xosc_arch_enable: false
+      xosc_arch_gain: 2MHz
+      xosc_arch_ondemand: true
+      xosc_arch_runstdby: false
+      xosc_arch_startup: 31us
+      xosc_arch_swben: false
+      xosc_arch_xtalen: false
+      xosc_frequency: 400000
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  PORT:
+    user_label: PORT
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT
+    functionality: System
+    api: HAL:HPL:PORT
+    configuration:
+      enable_port_input_event_0: false
+      enable_port_input_event_1: false
+      enable_port_input_event_2: false
+      enable_port_input_event_3: false
+      porta_event_action_0: Output register of pin will be set to level of event
+      porta_event_action_1: Output register of pin will be set to level of event
+      porta_event_action_2: Output register of pin will be set to level of event
+      porta_event_action_3: Output register of pin will be set to level of event
+      porta_event_pin_identifier_0: 0
+      porta_event_pin_identifier_1: 0
+      porta_event_pin_identifier_2: 0
+      porta_event_pin_identifier_3: 0
+      porta_input_event_enable_0: false
+      porta_input_event_enable_1: false
+      porta_input_event_enable_2: false
+      porta_input_event_enable_3: false
+      portb_event_action_0: Output register of pin will be set to level of event
+      portb_event_action_1: Output register of pin will be set to level of event
+      portb_event_action_2: Output register of pin will be set to level of event
+      portb_event_action_3: Output register of pin will be set to level of event
+      portb_event_pin_identifier_0: 0
+      portb_event_pin_identifier_1: 0
+      portb_event_pin_identifier_2: 0
+      portb_event_pin_identifier_3: 0
+      portb_input_event_enable_0: false
+      portb_input_event_enable_1: false
+      portb_input_event_enable_2: false
+      portb_input_event_enable_3: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  CALENDAR_0:
+    user_label: CALENDAR_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::RTC::driver_config_definition::Calendar::HAL:Driver:Calendar
+    functionality: Calendar
+    api: HAL:Driver:Calendar
+    configuration:
+      rtc_arch_init_reset: true
+      rtc_arch_prescaler: Peripheral clock divided by 1024
+      rtc_cmpeo0: false
+      rtc_event_control: false
+      rtc_ovfeo: false
+      rtc_pereo0: false
+      rtc_pereo1: false
+      rtc_pereo2: false
+      rtc_pereo3: false
+      rtc_pereo4: false
+      rtc_pereo5: false
+      rtc_pereo6: false
+      rtc_pereo7: false
+      rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2
+      rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2
+      rtc_tamper_input_action_0: OFF(Disabled)
+      rtc_tamper_input_action_1: OFF(Disabled)
+      rtc_tamper_input_action_2: OFF(Disabled)
+      rtc_tamper_input_action_3: OFF(Disabled)
+      rtc_tamper_input_action_4: OFF(Disabled)
+      tamper_debounce_enable_0: false
+      tamper_debounce_enable_1: false
+      tamper_debounce_enable_2: false
+      tamper_debounce_enable_3: false
+      tamper_debounce_enable_4: false
+      tamper_input_0_settings: false
+      tamper_input_1_settings: false
+      tamper_input_2_settings: false
+      tamper_input_3_settings: false
+      tamper_input_4_settings: false
+      tamper_level_0: false
+      tamper_level_1: false
+      tamper_level_2: false
+      tamper_level_3: false
+      tamper_level_4: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: RTC
+          input: RTC source
+          external: false
+          external_frequency: 0
+        configuration:
+          rtc_clk_selection: RTC source
+  I2C_0:
+    user_label: I2C_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
+    functionality: I2C
+    api: HAL:Driver:I2C_Master_Sync
+    configuration:
+      i2c_master_advanced: false
+      i2c_master_arch_dbgstop: Keep running
+      i2c_master_arch_inactout: Disabled
+      i2c_master_arch_lowtout: false
+      i2c_master_arch_mexttoen: false
+      i2c_master_arch_runstdby: false
+      i2c_master_arch_sdahold: 300-600ns hold time
+      i2c_master_arch_sexttoen: false
+      i2c_master_arch_trise: 215
+      i2c_master_baud_rate: 100000
+    optional_signals: []
+    variant:
+      specification: SDA=0, SCL=1
+      required_signals:
+      - name: SERCOM1/PAD/0
+        pad: PB30
+        label: SDA
+      - name: SERCOM1/PAD/1
+        pad: PB31
+        label: SCL
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 3
+  DELAY_0:
+    user_label: DELAY_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay
+    functionality: Delay
+    api: HAL:Driver:Delay
+    configuration:
+      systick_arch_tickint: false
+    optional_signals: []
+    variant: null
+    clocks:
+      domain_group: null
+  PWM_0:
+    user_label: PWM_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TC3::driver_config_definition::PWM::HAL:Driver:PWM
+    functionality: PWM
+    api: HAL:Driver:PWM
+    configuration:
+      tc_arch_alock: The Lock Update bit is not affected on overflow/underflow and
+        re-trigger event
+      tc_arch_dbgrun: false
+      tc_arch_evact: Event action disabled
+      tc_arch_mceo0: false
+      tc_arch_mceo1: false
+      tc_arch_ondemand: false
+      tc_arch_ovfeo: false
+      tc_arch_presync: Reload or reset counter on next GCLK
+      tc_arch_runstdby: false
+      tc_arch_tcei: false
+      tc_arch_tcinv: false
+      tc_arch_wave_duty_val: 500
+      tc_arch_wave_per_val: 1000
+      tc_mode: Counter in 16-bit mode
+      tc_prescaler: No division
+      timer_event_control: false
+    optional_signals:
+    - identifier: PWM_0:WO/0
+      pad: PA20
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.0
+      name: TC3/WO/0
+      label: WO/0
+    - identifier: PWM_0:WO/1
+      pad: PA21
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.1
+      name: TC3/WO/1
+      label: WO/1
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tc_gclk_selection: Generic clock generator 0
+  PWM_1:
+    user_label: PWM_1
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TCC0::driver_config_definition::PWM::HAL:Driver:PWM
+    functionality: PWM
+    api: HAL:Driver:PWM
+    configuration:
+      tcc_arch_alock: false
+      tcc_arch_cc0: 0
+      tcc_arch_cc1: 0
+      tcc_arch_cc2: 0
+      tcc_arch_cc3: 0
+      tcc_arch_cnteo: false
+      tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts
+      tcc_arch_cpten0: false
+      tcc_arch_cpten1: false
+      tcc_arch_cpten2: false
+      tcc_arch_cpten3: false
+      tcc_arch_cpten4: false
+      tcc_arch_cpten5: false
+      tcc_arch_cpten6: false
+      tcc_arch_cpten7: false
+      tcc_arch_dbgrun: false
+      tcc_arch_evact0: Event action disabled
+      tcc_arch_evact1: Event action disabled
+      tcc_arch_lupd: true
+      tcc_arch_mcei0: false
+      tcc_arch_mcei1: false
+      tcc_arch_mcei2: false
+      tcc_arch_mcei3: false
+      tcc_arch_mceo0: false
+      tcc_arch_mceo1: false
+      tcc_arch_mceo2: false
+      tcc_arch_mceo3: false
+      tcc_arch_ovfeo: false
+      tcc_arch_prescsync: Reload or reset counter on next GCLK
+      tcc_arch_runstdby: false
+      tcc_arch_sel_ch: 1
+      tcc_arch_tcei0: false
+      tcc_arch_tcei1: false
+      tcc_arch_tceinv0: false
+      tcc_arch_tceinv1: false
+      tcc_arch_trgeo: false
+      tcc_arch_wave_duty_val: 500
+      tcc_arch_wave_per_val: 1000
+      tcc_arch_wavegen: Single-slope PWM
+      tcc_per: 10000
+      tcc_prescaler: Divide by 8
+      timer_event_control: false
+    optional_signals:
+    - identifier: PWM_1:WO/5
+      pad: PA27
+      mode: PWM output
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TCC0.WO.5
+      name: TCC0/WO/5
+      label: WO/5
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: TCC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          tcc_gclk_selection: Generic clock generator 0
+  SEGMENT_LCD_0:
+    user_label: SEGMENT_LCD_0
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SLCD::driver_config_definition::SLCD::HAL:Driver:SLCD.Sync
+    functionality: Segment_LCD
+    api: HAL:Driver:SLCD_Sync
+    configuration:
+      slcd_arch_advanced_settings: false
+      slcd_arch_bbd: 2
+      slcd_arch_bben: true
+      slcd_arch_bias: THIRD
+      slcd_arch_char0_com_idx: 0
+      slcd_arch_char0_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char0_seg_idx: 1
+      slcd_arch_char0_seg_num: 1
+      slcd_arch_char0_setting: false
+      slcd_arch_char10_com_idx: 0
+      slcd_arch_char10_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char10_seg_idx: 1
+      slcd_arch_char10_seg_num: 1
+      slcd_arch_char10_setting: false
+      slcd_arch_char11_com_idx: 0
+      slcd_arch_char11_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char11_seg_idx: 1
+      slcd_arch_char11_seg_num: 1
+      slcd_arch_char11_setting: false
+      slcd_arch_char12_com_idx: 0
+      slcd_arch_char12_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char12_seg_idx: 1
+      slcd_arch_char12_seg_num: 1
+      slcd_arch_char12_setting: false
+      slcd_arch_char13_com_idx: 0
+      slcd_arch_char13_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char13_seg_idx: 1
+      slcd_arch_char13_seg_num: 1
+      slcd_arch_char13_setting: false
+      slcd_arch_char14_com_idx: 0
+      slcd_arch_char14_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char14_seg_idx: 1
+      slcd_arch_char14_seg_num: 1
+      slcd_arch_char14_setting: false
+      slcd_arch_char15_com_idx: 0
+      slcd_arch_char15_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char15_seg_idx: 1
+      slcd_arch_char15_seg_num: 1
+      slcd_arch_char15_setting: false
+      slcd_arch_char16_com_idx: 0
+      slcd_arch_char16_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char16_seg_idx: 1
+      slcd_arch_char16_seg_num: 1
+      slcd_arch_char16_setting: false
+      slcd_arch_char17_com_idx: 0
+      slcd_arch_char17_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char17_seg_idx: 1
+      slcd_arch_char17_seg_num: 1
+      slcd_arch_char17_setting: false
+      slcd_arch_char18_com_idx: 0
+      slcd_arch_char18_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char18_seg_idx: 1
+      slcd_arch_char18_seg_num: 1
+      slcd_arch_char18_setting: false
+      slcd_arch_char19_com_idx: 0
+      slcd_arch_char19_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char19_seg_idx: 1
+      slcd_arch_char19_seg_num: 1
+      slcd_arch_char19_setting: false
+      slcd_arch_char1_com_idx: 0
+      slcd_arch_char1_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char1_seg_idx: 1
+      slcd_arch_char1_seg_num: 1
+      slcd_arch_char1_setting: false
+      slcd_arch_char20_com_idx: 0
+      slcd_arch_char20_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char20_seg_idx: 1
+      slcd_arch_char20_seg_num: 1
+      slcd_arch_char20_setting: false
+      slcd_arch_char21_com_idx: 0
+      slcd_arch_char21_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char21_seg_idx: 1
+      slcd_arch_char21_seg_num: 1
+      slcd_arch_char21_setting: false
+      slcd_arch_char22_com_idx: 0
+      slcd_arch_char22_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char22_seg_idx: 1
+      slcd_arch_char22_seg_num: 1
+      slcd_arch_char22_setting: false
+      slcd_arch_char23_com_idx: 0
+      slcd_arch_char23_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char23_seg_idx: 1
+      slcd_arch_char23_seg_num: 1
+      slcd_arch_char23_setting: false
+      slcd_arch_char24_com_idx: 0
+      slcd_arch_char24_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char24_seg_idx: 1
+      slcd_arch_char24_seg_num: 1
+      slcd_arch_char24_setting: false
+      slcd_arch_char25_com_idx: 0
+      slcd_arch_char25_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char25_seg_idx: 1
+      slcd_arch_char25_seg_num: 1
+      slcd_arch_char25_setting: false
+      slcd_arch_char26_com_idx: 0
+      slcd_arch_char26_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char26_seg_idx: 1
+      slcd_arch_char26_seg_num: 1
+      slcd_arch_char26_setting: false
+      slcd_arch_char27_com_idx: 0
+      slcd_arch_char27_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char27_seg_idx: 1
+      slcd_arch_char27_seg_num: 1
+      slcd_arch_char27_setting: false
+      slcd_arch_char28_com_idx: 0
+      slcd_arch_char28_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char28_seg_idx: 1
+      slcd_arch_char28_seg_num: 1
+      slcd_arch_char28_setting: false
+      slcd_arch_char29_com_idx: 0
+      slcd_arch_char29_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char29_seg_idx: 1
+      slcd_arch_char29_seg_num: 1
+      slcd_arch_char29_setting: false
+      slcd_arch_char2_com_idx: 0
+      slcd_arch_char2_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char2_seg_idx: 1
+      slcd_arch_char2_seg_num: 1
+      slcd_arch_char2_setting: false
+      slcd_arch_char30_com_idx: 0
+      slcd_arch_char30_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char30_seg_idx: 1
+      slcd_arch_char30_seg_num: 1
+      slcd_arch_char30_setting: false
+      slcd_arch_char31_com_idx: 0
+      slcd_arch_char31_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char31_seg_idx: 1
+      slcd_arch_char31_seg_num: 1
+      slcd_arch_char31_setting: false
+      slcd_arch_char32_com_idx: 0
+      slcd_arch_char32_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char32_seg_idx: 1
+      slcd_arch_char32_seg_num: 1
+      slcd_arch_char32_setting: false
+      slcd_arch_char33_com_idx: 0
+      slcd_arch_char33_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char33_seg_idx: 1
+      slcd_arch_char33_seg_num: 1
+      slcd_arch_char33_setting: false
+      slcd_arch_char34_com_idx: 0
+      slcd_arch_char34_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char34_seg_idx: 1
+      slcd_arch_char34_seg_num: 1
+      slcd_arch_char34_setting: false
+      slcd_arch_char35_com_idx: 0
+      slcd_arch_char35_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char35_seg_idx: 1
+      slcd_arch_char35_seg_num: 1
+      slcd_arch_char35_setting: false
+      slcd_arch_char36_com_idx: 0
+      slcd_arch_char36_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char36_seg_idx: 1
+      slcd_arch_char36_seg_num: 1
+      slcd_arch_char36_setting: false
+      slcd_arch_char37_com_idx: 0
+      slcd_arch_char37_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char37_seg_idx: 1
+      slcd_arch_char37_seg_num: 1
+      slcd_arch_char37_setting: false
+      slcd_arch_char38_com_idx: 0
+      slcd_arch_char38_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char38_seg_idx: 1
+      slcd_arch_char38_seg_num: 1
+      slcd_arch_char38_setting: false
+      slcd_arch_char39_com_idx: 0
+      slcd_arch_char39_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char39_seg_idx: 1
+      slcd_arch_char39_seg_num: 1
+      slcd_arch_char39_setting: false
+      slcd_arch_char3_com_idx: 0
+      slcd_arch_char3_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char3_seg_idx: 1
+      slcd_arch_char3_seg_num: 1
+      slcd_arch_char3_setting: false
+      slcd_arch_char40_com_idx: 0
+      slcd_arch_char40_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char40_seg_idx: 1
+      slcd_arch_char40_seg_num: 1
+      slcd_arch_char40_setting: false
+      slcd_arch_char41_com_idx: 0
+      slcd_arch_char41_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char41_seg_idx: 1
+      slcd_arch_char41_seg_num: 1
+      slcd_arch_char41_setting: false
+      slcd_arch_char42_com_idx: 0
+      slcd_arch_char42_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char42_seg_idx: 1
+      slcd_arch_char42_seg_num: 1
+      slcd_arch_char42_setting: false
+      slcd_arch_char43_com_idx: 0
+      slcd_arch_char43_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char43_seg_idx: 1
+      slcd_arch_char43_seg_num: 1
+      slcd_arch_char43_setting: false
+      slcd_arch_char4_com_idx: 0
+      slcd_arch_char4_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char4_seg_idx: 1
+      slcd_arch_char4_seg_num: 1
+      slcd_arch_char4_setting: false
+      slcd_arch_char5_com_idx: 0
+      slcd_arch_char5_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char5_seg_idx: 1
+      slcd_arch_char5_seg_num: 1
+      slcd_arch_char5_setting: false
+      slcd_arch_char6_com_idx: 0
+      slcd_arch_char6_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char6_seg_idx: 1
+      slcd_arch_char6_seg_num: 1
+      slcd_arch_char6_setting: false
+      slcd_arch_char7_com_idx: 0
+      slcd_arch_char7_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char7_seg_idx: 1
+      slcd_arch_char7_seg_num: 1
+      slcd_arch_char7_setting: false
+      slcd_arch_char8_com_idx: 0
+      slcd_arch_char8_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char8_seg_idx: 1
+      slcd_arch_char8_seg_num: 1
+      slcd_arch_char8_setting: false
+      slcd_arch_char9_com_idx: 0
+      slcd_arch_char9_mapping_table: 7 Segments Mapping Table
+      slcd_arch_char9_seg_idx: 1
+      slcd_arch_char9_seg_num: 1
+      slcd_arch_char9_setting: false
+      slcd_arch_ckdiv: '4'
+      slcd_arch_cm_14segs_0_mapping_setting: '0'
+      slcd_arch_cm_14segs_10_mapping_setting: '10'
+      slcd_arch_cm_14segs_11_mapping_setting: '11'
+      slcd_arch_cm_14segs_12_mapping_setting: '12'
+      slcd_arch_cm_14segs_13_mapping_setting: '13'
+      slcd_arch_cm_14segs_1_mapping_setting: '1'
+      slcd_arch_cm_14segs_2_mapping_setting: '2'
+      slcd_arch_cm_14segs_3_mapping_setting: '3'
+      slcd_arch_cm_14segs_4_mapping_setting: '4'
+      slcd_arch_cm_14segs_5_mapping_setting: '5'
+      slcd_arch_cm_14segs_6_mapping_setting: '6'
+      slcd_arch_cm_14segs_7_mapping_setting: '7'
+      slcd_arch_cm_14segs_8_mapping_setting: '8'
+      slcd_arch_cm_14segs_9_mapping_setting: '9'
+      slcd_arch_cm_14segs_enable: false
+      slcd_arch_cm_7segs_0_mapping_setting: '0'
+      slcd_arch_cm_7segs_1_mapping_setting: '1'
+      slcd_arch_cm_7segs_2_mapping_setting: '2'
+      slcd_arch_cm_7segs_3_mapping_setting: '3'
+      slcd_arch_cm_7segs_4_mapping_setting: '4'
+      slcd_arch_cm_7segs_5_mapping_setting: '5'
+      slcd_arch_cm_7segs_6_mapping_setting: '6'
+      slcd_arch_cm_7segs_setting: false
+      slcd_arch_cm_setting: false
+      slcd_arch_com_num: '3'
+      slcd_arch_contrast_adjust: 3.4398V
+      slcd_arch_presc: '64'
+      slcd_arch_prf: 250Hz
+      slcd_arch_rrf: 2kHz
+      slcd_arch_runstdby: false
+      slcd_arch_seg_num: 24
+      slcd_arch_wmod: Low Power Waveform(frame-inversion)
+      slcd_arch_xvlcd: false
+    optional_signals:
+    - identifier: SEGMENT_LCD_0:LP/0
+      pad: PB06
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.0
+      name: SLCD/LP/0
+      label: LP/0
+    - identifier: SEGMENT_LCD_0:LP/1
+      pad: PB07
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.1
+      name: SLCD/LP/1
+      label: LP/1
+    - identifier: SEGMENT_LCD_0:LP/2
+      pad: PB08
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.2
+      name: SLCD/LP/2
+      label: LP/2
+    - identifier: SEGMENT_LCD_0:LP/3
+      pad: PB09
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.3
+      name: SLCD/LP/3
+      label: LP/3
+    - identifier: SEGMENT_LCD_0:LP/4
+      pad: PA04
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.4
+      name: SLCD/LP/4
+      label: LP/4
+    - identifier: SEGMENT_LCD_0:LP/5
+      pad: PA05
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.5
+      name: SLCD/LP/5
+      label: LP/5
+    - identifier: SEGMENT_LCD_0:LP/6
+      pad: PA06
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.6
+      name: SLCD/LP/6
+      label: LP/6
+    - identifier: SEGMENT_LCD_0:LP/7
+      pad: PA07
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.7
+      name: SLCD/LP/7
+      label: LP/7
+    - identifier: SEGMENT_LCD_0:LP/11
+      pad: PA08
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.11
+      name: SLCD/LP/11
+      label: LP/11
+    - identifier: SEGMENT_LCD_0:LP/12
+      pad: PA09
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.12
+      name: SLCD/LP/12
+      label: LP/12
+    - identifier: SEGMENT_LCD_0:LP/13
+      pad: PA10
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.13
+      name: SLCD/LP/13
+      label: LP/13
+    - identifier: SEGMENT_LCD_0:LP/14
+      pad: PA11
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.14
+      name: SLCD/LP/14
+      label: LP/14
+    - identifier: SEGMENT_LCD_0:LP/21
+      pad: PB11
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.21
+      name: SLCD/LP/21
+      label: LP/21
+    - identifier: SEGMENT_LCD_0:LP/22
+      pad: PB12
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.22
+      name: SLCD/LP/22
+      label: LP/22
+    - identifier: SEGMENT_LCD_0:LP/23
+      pad: PB13
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.23
+      name: SLCD/LP/23
+      label: LP/23
+    - identifier: SEGMENT_LCD_0:LP/24
+      pad: PB14
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.24
+      name: SLCD/LP/24
+      label: LP/24
+    - identifier: SEGMENT_LCD_0:LP/25
+      pad: PB15
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.25
+      name: SLCD/LP/25
+      label: LP/25
+    - identifier: SEGMENT_LCD_0:LP/28
+      pad: PA12
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.28
+      name: SLCD/LP/28
+      label: LP/28
+    - identifier: SEGMENT_LCD_0:LP/29
+      pad: PA13
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.29
+      name: SLCD/LP/29
+      label: LP/29
+    - identifier: SEGMENT_LCD_0:LP/30
+      pad: PA14
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.30
+      name: SLCD/LP/30
+      label: LP/30
+    - identifier: SEGMENT_LCD_0:LP/31
+      pad: PA15
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.31
+      name: SLCD/LP/31
+      label: LP/31
+    - identifier: SEGMENT_LCD_0:LP/32
+      pad: PA16
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.32
+      name: SLCD/LP/32
+      label: LP/32
+    - identifier: SEGMENT_LCD_0:LP/33
+      pad: PA17
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.33
+      name: SLCD/LP/33
+      label: LP/33
+    - identifier: SEGMENT_LCD_0:LP/34
+      pad: PA18
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.34
+      name: SLCD/LP/34
+      label: LP/34
+    - identifier: SEGMENT_LCD_0:LP/35
+      pad: PA19
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.35
+      name: SLCD/LP/35
+      label: LP/35
+    - identifier: SEGMENT_LCD_0:LP/42
+      pad: PB16
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.42
+      name: SLCD/LP/42
+      label: LP/42
+    - identifier: SEGMENT_LCD_0:LP/43
+      pad: PB17
+      mode: LCD pin
+      configuration: null
+      definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.43
+      name: SLCD/LP/43
+      label: LP/43
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: SLCD
+          input: SLCD source
+          external: false
+          external_frequency: 0
+        configuration:
+          slcd_clk_selection: SLCD source
+pads:
+  VBUS_DET:
+    name: PA02
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA02
+    mode: Digital input
+    user_label: VBUS_DET
+    configuration:
+      pad_pull_config: Pull-down
+  A0:
+    name: PB04
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB04
+    mode: Analog
+    user_label: A0
+    configuration: null
+  BTN_ALARM:
+    name: PB05
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB05
+    mode: Digital input
+    user_label: BTN_ALARM
+    configuration:
+      pad_pull_config: Pull-down
+  COM0:
+    name: PB06
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB06
+    mode: Peripheral IO
+    user_label: COM0
+    configuration: null
+  COM1:
+    name: PB07
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB07
+    mode: Peripheral IO
+    user_label: COM1
+    configuration: null
+  COM2:
+    name: PB08
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB08
+    mode: Peripheral IO
+    user_label: COM2
+    configuration: null
+  SEG0:
+    name: PB09
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB09
+    mode: Peripheral IO
+    user_label: SEG0
+    configuration: null
+  SEG1:
+    name: PA04
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA04
+    mode: Peripheral IO
+    user_label: SEG1
+    configuration: null
+  SEG2:
+    name: PA05
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA05
+    mode: Peripheral IO
+    user_label: SEG2
+    configuration: null
+  SEG3:
+    name: PA06
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA06
+    mode: Peripheral IO
+    user_label: SEG3
+    configuration: null
+  SEG4:
+    name: PA07
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA07
+    mode: Peripheral IO
+    user_label: SEG4
+    configuration: null
+  SEG5:
+    name: PA08
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA08
+    mode: Peripheral IO
+    user_label: SEG5
+    configuration: null
+  SEG6:
+    name: PA09
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA09
+    mode: Peripheral IO
+    user_label: SEG6
+    configuration: null
+  SEG7:
+    name: PA10
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA10
+    mode: Peripheral IO
+    user_label: SEG7
+    configuration: null
+  SEG8:
+    name: PA11
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA11
+    mode: Peripheral IO
+    user_label: SEG8
+    configuration: null
+  SEG9:
+    name: PB11
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB11
+    mode: Peripheral IO
+    user_label: SEG9
+    configuration: null
+  SEG10:
+    name: PB12
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB12
+    mode: Peripheral IO
+    user_label: SEG10
+    configuration: null
+  SEG11:
+    name: PB13
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB13
+    mode: Peripheral IO
+    user_label: SEG11
+    configuration: null
+  SEG12:
+    name: PB14
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB14
+    mode: Peripheral IO
+    user_label: SEG12
+    configuration: null
+  SEG13:
+    name: PB15
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB15
+    mode: Peripheral IO
+    user_label: SEG13
+    configuration: null
+  SEG14:
+    name: PA12
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA12
+    mode: Peripheral IO
+    user_label: SEG14
+    configuration: null
+  SEG15:
+    name: PA13
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA13
+    mode: Peripheral IO
+    user_label: SEG15
+    configuration: null
+  SEG16:
+    name: PA14
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA14
+    mode: Peripheral IO
+    user_label: SEG16
+    configuration: null
+  SEG17:
+    name: PA15
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA15
+    mode: Peripheral IO
+    user_label: SEG17
+    configuration: null
+  SEG18:
+    name: PA16
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA16
+    mode: Peripheral IO
+    user_label: SEG18
+    configuration: null
+  SEG19:
+    name: PA17
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA17
+    mode: Peripheral IO
+    user_label: SEG19
+    configuration: null
+  SEG20:
+    name: PA18
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA18
+    mode: Peripheral IO
+    user_label: SEG20
+    configuration: null
+  SEG21:
+    name: PA19
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA19
+    mode: Peripheral IO
+    user_label: SEG21
+    configuration: null
+  SEG22:
+    name: PB16
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB16
+    mode: Peripheral IO
+    user_label: SEG22
+    configuration: null
+  SEG23:
+    name: PB17
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB17
+    mode: Peripheral IO
+    user_label: SEG23
+    configuration: null
+  RED:
+    name: PA20
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA20
+    mode: Peripheral IO
+    user_label: RED
+    configuration: null
+  GREEN:
+    name: PA21
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA21
+    mode: Peripheral IO
+    user_label: GREEN
+    configuration: null
+  BTN_LIGHT:
+    name: PA22
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA22
+    mode: Digital input
+    user_label: BTN_LIGHT
+    configuration:
+      pad_pull_config: Pull-down
+  BTN_MODE:
+    name: PA23
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA23
+    mode: Digital input
+    user_label: BTN_MODE
+    configuration:
+      pad_pull_config: Pull-down
+  BUZZER:
+    name: PA27
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA27
+    mode: Peripheral IO
+    user_label: BUZZER
+    configuration: null
+  SDA:
+    name: PB30
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB30
+    mode: I2C
+    user_label: SDA
+    configuration: null
+  SCL:
+    name: PB31
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB31
+    mode: I2C
+    user_label: SCL
+    configuration: null
+  D1:
+    name: PB00
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB00
+    mode: Digital output
+    user_label: D1
+    configuration: null
+  A1:
+    name: PB01
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB01
+    mode: Analog
+    user_label: A1
+    configuration: null
+  A2:
+    name: PB02
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB02
+    mode: Analog
+    user_label: A2
+    configuration: null
+  D0:
+    name: PB03
+    definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB03
+    mode: Digital output
+    user_label: D0
+    configuration: null
+toolchain_options: []
diff --git a/Smol Watch Project/My Project/Config/RTE_Components.h b/Smol Watch Project/My Project/Config/RTE_Components.h
new file mode 100644
index 0000000..3ba6b1b
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/RTE_Components.h	
@@ -0,0 +1,54 @@
+ /**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \acme_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \acme_license_stop
+ *
+ * Project: My Project
+ * Target:  ATSAML22J18A 
+ *
+ **/
+
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#define ATMEL_START
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Smol Watch Project/My Project/Config/hpl_adc_config.h b/Smol Watch Project/My Project/Config/hpl_adc_config.h
new file mode 100644
index 0000000..e15dc52
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_adc_config.h	
@@ -0,0 +1,305 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x0
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x1=>1/1.6 VDDANA
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>External reference A
+// <0x4=>External reference B
+// <0x5=>VDDANA
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x10=>ADC AIN16 pin
+// <0x11=>ADC AIN17 pin
+// <0x12=>ADC AIN18 pin
+// <0x13=>ADC AIN19 pin
+// <0x18=>Temperature reference
+// <0x19=>Bandgap voltage
+// <0x1A=>1/4 scaled core supply
+// <0x1B=>1/4 scaled I/O supply
+// <0x1D=>1/4 Scaled VBAT Supply
+// <0x1E=>CTAT Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_dmac_config.h b/Smol Watch Project/My Project/Config/hpl_dmac_config.h
new file mode 100644
index 0000000..36adb88
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_dmac_config.h	
@@ -0,0 +1,3122 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> DMAC enable
+// <i> Indicates whether dmac is enabled or not
+// <id> dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 0
+#endif
+
+// <q> Priority Level 0
+// <i> Indicates whether Priority Level 0 is enabled or not
+// <id> dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 0
+#endif
+
+// <o> Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// <i> Defines Level 0 Arbitration for DMA channels
+// <id> dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// <o> Level 0 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+
+// <q> Priority Level 1
+// <i> Indicates whether Priority Level 1 is enabled or not
+// <id> dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 0
+#endif
+
+// <o> Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// <i> Defines Level 1 Arbitration for DMA channels
+// <id> dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// <o> Level 1 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+
+// <q> Priority Level 2
+// <i> Indicates whether Priority Level 2 is enabled or not
+// <id> dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 0
+#endif
+
+// <o> Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// <i> Defines Level 2 Arbitration for DMA channels
+// <id> dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// <o> Level 2 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+
+// <q> Priority Level 3
+// <i> Indicates whether Priority Level 3 is enabled or not
+// <id> dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 0
+#endif
+
+// <o> Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// <i> Defines Level 3 Arbitration for DMA channels
+// <id> dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// <o> Level 3 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+
+// <o> Data Transfer Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// <i> Defines the memory priority access during the data transfer operation
+// <id> dmac_dqos
+#ifndef CONF_DMAC_DQOS
+#define CONF_DMAC_DQOS 0
+#endif
+
+// <o> Fetch Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// <i> Defines the memory priority access during the fetch operation
+// <id> dmac_fqos
+#ifndef CONF_DMAC_FQOS
+#define CONF_DMAC_FQOS 0
+#endif
+
+// <o> Write-Back Quality of Service
+// <0=> Background (no sensitive operation)
+// <1=> Sensitive bandwidth
+// <2=> Sensitive latency
+// <3=> Critical latency
+// <i> Defines the memory priority access during the write-back operation
+// <id> dmac_wrbqos
+#ifndef CONF_DMAC_WRBQOS
+#define CONF_DMAC_WRBQOS 0
+#endif
+
+// <q> Debug Run
+// <i> Indicates whether Debug Run is enabled or not
+// <id> dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 0 is enabled or not
+// <id> dmac_enable_0
+#ifndef CONF_DMAC_ENABLE_0
+#define CONF_DMAC_ENABLE_0 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 0 is running in standby mode or not
+// <id> dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 0
+#endif
+// </e>
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 1 is enabled or not
+// <id> dmac_enable_1
+#ifndef CONF_DMAC_ENABLE_1
+#define CONF_DMAC_ENABLE_1 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 1 is running in standby mode or not
+// <id> dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 0
+#endif
+// </e>
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 2 is enabled or not
+// <id> dmac_enable_2
+#ifndef CONF_DMAC_ENABLE_2
+#define CONF_DMAC_ENABLE_2 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 2 is running in standby mode or not
+// <id> dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 0
+#endif
+// </e>
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 3 is enabled or not
+// <id> dmac_enable_3
+#ifndef CONF_DMAC_ENABLE_3
+#define CONF_DMAC_ENABLE_3 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 3 is running in standby mode or not
+// <id> dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+// </e>
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 4 is enabled or not
+// <id> dmac_enable_4
+#ifndef CONF_DMAC_ENABLE_4
+#define CONF_DMAC_ENABLE_4 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 4 is running in standby mode or not
+// <id> dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+// </e>
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 5 is enabled or not
+// <id> dmac_enable_5
+#ifndef CONF_DMAC_ENABLE_5
+#define CONF_DMAC_ENABLE_5 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 5 is running in standby mode or not
+// <id> dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+// </e>
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 6 is enabled or not
+// <id> dmac_enable_6
+#ifndef CONF_DMAC_ENABLE_6
+#define CONF_DMAC_ENABLE_6 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 6 is running in standby mode or not
+// <id> dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+// </e>
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 7 is enabled or not
+// <id> dmac_enable_7
+#ifndef CONF_DMAC_ENABLE_7
+#define CONF_DMAC_ENABLE_7 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 7 is running in standby mode or not
+// <id> dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+// </e>
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 8 is enabled or not
+// <id> dmac_enable_8
+#ifndef CONF_DMAC_ENABLE_8
+#define CONF_DMAC_ENABLE_8 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 8 is running in standby mode or not
+// <id> dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+// </e>
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 9 is enabled or not
+// <id> dmac_enable_9
+#ifndef CONF_DMAC_ENABLE_9
+#define CONF_DMAC_ENABLE_9 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 9 is running in standby mode or not
+// <id> dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+// </e>
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 10 is enabled or not
+// <id> dmac_enable_10
+#ifndef CONF_DMAC_ENABLE_10
+#define CONF_DMAC_ENABLE_10 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 10 is running in standby mode or not
+// <id> dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+// </e>
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 11 is enabled or not
+// <id> dmac_enable_11
+#ifndef CONF_DMAC_ENABLE_11
+#define CONF_DMAC_ENABLE_11 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 11 is running in standby mode or not
+// <id> dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+// </e>
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 12 is enabled or not
+// <id> dmac_enable_12
+#ifndef CONF_DMAC_ENABLE_12
+#define CONF_DMAC_ENABLE_12 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 12 is running in standby mode or not
+// <id> dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+// </e>
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 13 is enabled or not
+// <id> dmac_enable_13
+#ifndef CONF_DMAC_ENABLE_13
+#define CONF_DMAC_ENABLE_13 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 13 is running in standby mode or not
+// <id> dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+// </e>
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 14 is enabled or not
+// <id> dmac_enable_14
+#ifndef CONF_DMAC_ENABLE_14
+#define CONF_DMAC_ENABLE_14 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 14 is running in standby mode or not
+// <id> dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+// </e>
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <q> Channel Enable
+// <i> Indicates whether channel 15 is enabled or not
+// <id> dmac_enable_15
+#ifndef CONF_DMAC_ENABLE_15
+#define CONF_DMAC_ENABLE_15 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 15 is running in standby mode or not
+// <id> dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Timestamp
+// <0x02=> SERCOM0 RX Trigger
+// <0x03=> SERCOM0 TX Trigger
+// <0x04=> SERCOM1 RX Trigger
+// <0x05=> SERCOM1 TX Trigger
+// <0x06=> SERCOM2 RX Trigger
+// <0x07=> SERCOM2 TX Trigger
+// <0x08=> SERCOM3 RX Trigger
+// <0x09=> SERCOM3 TX Trigger
+// <0x0A=> SERCOM4 RX Trigger
+// <0x0B=> SERCOM4 TX Trigger
+// <0x0C=> SERCOM5 RX Trigger
+// <0x0D=> SERCOM5 TX Trigger
+// <0x0E=> TCC0 Overflow Trigger
+// <0x0F=> TCC0 Match/Compare 0 Trigger
+// <0x10=> TCC0 Match/Compare 1 Trigger
+// <0x11=> TCC0 Match/Compare 2 Trigger
+// <0x12=> TCC0 Match/Compare 3 Trigger
+// <0x13=> TC0 Overflow Trigger
+// <0x14=> TC0 Match/Compare 0 Trigger
+// <0x15=> TC0 Match/Compare 1 Trigger
+// <0x16=> TC1 Overflow Trigger
+// <0x17=> TC1 Match/Compare 0 Trigger
+// <0x18=> TC1 Match/Compare 1 Trigger
+// <0x19=> TC2 Overflow Trigger
+// <0x1A=> TC2 Match/Compare 0 Trigger
+// <0x1B=> TC2 Match/Compare 1 Trigger
+// <0x1C=> TC3 Overflow Trigger
+// <0x1D=> TC3 Match/Compare 0 Trigger
+// <0x1E=> TC3 Match/Compare 1 Trigger
+// <0x1F=> ADC Result Ready Trigger
+// <0x20=> SLCD Display Memory Update Trigger
+// <0x21=> SLCD Automated Character Mapping Data Ready Trigger
+// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger
+// <0x23=> AES Write Trigger
+// <0x24=> AES Read Trigger
+// <0x25=> PTC End of Conversion Trigger
+// <0x26=> PTC Sequence Trigger
+// <0x27=> PTC Window Comparator Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+// </e>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_eic_config.h b/Smol Watch Project/My Project/Config/hpl_eic_config.h
new file mode 100644
index 0000000..3b268a1
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_eic_config.h	
@@ -0,0 +1,730 @@
+/* Auto-generated config file hpl_eic_config.h */
+#ifndef HPL_EIC_CONFIG_H
+#define HPL_EIC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+// <o> Clock Selection
+// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
+// <i> either by CLK_ULP32K when power consumption is the priority.
+// <0x0=> Clocked by GCLK
+// <0x1=> Clocked by ULPOSC32K
+// <id> eic_arch_cksel
+#ifndef CONF_EIC_CKSEL
+#define CONF_EIC_CKSEL 0
+#endif
+
+// </h>
+
+// <e> Non-Maskable Interrupt Control
+// <id> eic_arch_nmi_ctrl
+#ifndef CONF_EIC_ENABLE_NMI_CTRL
+#define CONF_EIC_ENABLE_NMI_CTRL 0
+#endif
+
+// <q> Non-Maskable Interrupt Filter Enable
+// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
+// <id> eic_arch_nmifilten
+#ifndef CONF_EIC_NMIFILTEN
+#define CONF_EIC_NMIFILTEN 0
+#endif
+
+// <y> Non-Maskable Interrupt Sense
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines non-maskable interrupt sense
+// <id> eic_arch_nmisense
+#ifndef CONF_EIC_NMISENSE
+#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> Asynchronous Edge Detection Mode
+// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
+// <id> eic_arch_nmiasynch
+#ifndef CONF_EIC_NMIASYNCH
+#define CONF_EIC_NMIASYNCH 0
+#endif
+// </e>
+
+// <e> Interrupt 0 Settings
+// <id> eic_arch_enable_irq_setting0
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
+#define CONF_EIC_ENABLE_IRQ_SETTING0 0
+#endif
+
+// <q> External Interrupt 0 Filter Enable
+// <i> Indicates whether the external interrupt 0 filter is enabled or not
+// <id> eic_arch_filten0
+#ifndef CONF_EIC_FILTEN0
+#define CONF_EIC_FILTEN0 0
+#endif
+
+// <q> External Interrupt 0 Event Output Enable
+// <i> Indicates whether the external interrupt 0 event output is enabled or not
+// <id> eic_arch_extinteo0
+#ifndef CONF_EIC_EXTINTEO0
+#define CONF_EIC_EXTINTEO0 0
+#endif
+
+// <y> Input 0 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense0
+#ifndef CONF_EIC_SENSE0
+#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 0 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch0
+#ifndef CONF_EIC_ASYNCH0
+#define CONF_EIC_ASYNCH0 0
+#endif
+
+// </e>
+
+// <e> Interrupt 1 Settings
+// <id> eic_arch_enable_irq_setting1
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
+#define CONF_EIC_ENABLE_IRQ_SETTING1 0
+#endif
+
+// <q> External Interrupt 1 Filter Enable
+// <i> Indicates whether the external interrupt 1 filter is enabled or not
+// <id> eic_arch_filten1
+#ifndef CONF_EIC_FILTEN1
+#define CONF_EIC_FILTEN1 0
+#endif
+
+// <q> External Interrupt 1 Event Output Enable
+// <i> Indicates whether the external interrupt 1 event output is enabled or not
+// <id> eic_arch_extinteo1
+#ifndef CONF_EIC_EXTINTEO1
+#define CONF_EIC_EXTINTEO1 0
+#endif
+
+// <y> Input 1 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense1
+#ifndef CONF_EIC_SENSE1
+#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 1 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch1
+#ifndef CONF_EIC_ASYNCH1
+#define CONF_EIC_ASYNCH1 0
+#endif
+
+// </e>
+
+// <e> Interrupt 2 Settings
+// <id> eic_arch_enable_irq_setting2
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
+#define CONF_EIC_ENABLE_IRQ_SETTING2 0
+#endif
+
+// <q> External Interrupt 2 Filter Enable
+// <i> Indicates whether the external interrupt 2 filter is enabled or not
+// <id> eic_arch_filten2
+#ifndef CONF_EIC_FILTEN2
+#define CONF_EIC_FILTEN2 0
+#endif
+
+// <q> External Interrupt 2 Event Output Enable
+// <i> Indicates whether the external interrupt 2 event output is enabled or not
+// <id> eic_arch_extinteo2
+#ifndef CONF_EIC_EXTINTEO2
+#define CONF_EIC_EXTINTEO2 0
+#endif
+
+// <y> Input 2 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense2
+#ifndef CONF_EIC_SENSE2
+#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 2 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch2
+#ifndef CONF_EIC_ASYNCH2
+#define CONF_EIC_ASYNCH2 0
+#endif
+
+// </e>
+
+// <e> Interrupt 3 Settings
+// <id> eic_arch_enable_irq_setting3
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
+#define CONF_EIC_ENABLE_IRQ_SETTING3 0
+#endif
+
+// <q> External Interrupt 3 Filter Enable
+// <i> Indicates whether the external interrupt 3 filter is enabled or not
+// <id> eic_arch_filten3
+#ifndef CONF_EIC_FILTEN3
+#define CONF_EIC_FILTEN3 0
+#endif
+
+// <q> External Interrupt 3 Event Output Enable
+// <i> Indicates whether the external interrupt 3 event output is enabled or not
+// <id> eic_arch_extinteo3
+#ifndef CONF_EIC_EXTINTEO3
+#define CONF_EIC_EXTINTEO3 0
+#endif
+
+// <y> Input 3 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense3
+#ifndef CONF_EIC_SENSE3
+#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 3 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch3
+#ifndef CONF_EIC_ASYNCH3
+#define CONF_EIC_ASYNCH3 0
+#endif
+
+// </e>
+
+// <e> Interrupt 4 Settings
+// <id> eic_arch_enable_irq_setting4
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
+#define CONF_EIC_ENABLE_IRQ_SETTING4 0
+#endif
+
+// <q> External Interrupt 4 Filter Enable
+// <i> Indicates whether the external interrupt 4 filter is enabled or not
+// <id> eic_arch_filten4
+#ifndef CONF_EIC_FILTEN4
+#define CONF_EIC_FILTEN4 0
+#endif
+
+// <q> External Interrupt 4 Event Output Enable
+// <i> Indicates whether the external interrupt 4 event output is enabled or not
+// <id> eic_arch_extinteo4
+#ifndef CONF_EIC_EXTINTEO4
+#define CONF_EIC_EXTINTEO4 0
+#endif
+
+// <y> Input 4 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense4
+#ifndef CONF_EIC_SENSE4
+#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 4 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch4
+#ifndef CONF_EIC_ASYNCH4
+#define CONF_EIC_ASYNCH4 0
+#endif
+
+// </e>
+
+// <e> Interrupt 5 Settings
+// <id> eic_arch_enable_irq_setting5
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
+#define CONF_EIC_ENABLE_IRQ_SETTING5 1
+#endif
+
+// <q> External Interrupt 5 Filter Enable
+// <i> Indicates whether the external interrupt 5 filter is enabled or not
+// <id> eic_arch_filten5
+#ifndef CONF_EIC_FILTEN5
+#define CONF_EIC_FILTEN5 0
+#endif
+
+// <q> External Interrupt 5 Event Output Enable
+// <i> Indicates whether the external interrupt 5 event output is enabled or not
+// <id> eic_arch_extinteo5
+#ifndef CONF_EIC_EXTINTEO5
+#define CONF_EIC_EXTINTEO5 0
+#endif
+
+// <y> Input 5 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense5
+#ifndef CONF_EIC_SENSE5
+#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// <q> External Interrupt 5 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch5
+#ifndef CONF_EIC_ASYNCH5
+#define CONF_EIC_ASYNCH5 0
+#endif
+
+// </e>
+
+// <e> Interrupt 6 Settings
+// <id> eic_arch_enable_irq_setting6
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
+#define CONF_EIC_ENABLE_IRQ_SETTING6 1
+#endif
+
+// <q> External Interrupt 6 Filter Enable
+// <i> Indicates whether the external interrupt 6 filter is enabled or not
+// <id> eic_arch_filten6
+#ifndef CONF_EIC_FILTEN6
+#define CONF_EIC_FILTEN6 0
+#endif
+
+// <q> External Interrupt 6 Event Output Enable
+// <i> Indicates whether the external interrupt 6 event output is enabled or not
+// <id> eic_arch_extinteo6
+#ifndef CONF_EIC_EXTINTEO6
+#define CONF_EIC_EXTINTEO6 0
+#endif
+
+// <y> Input 6 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense6
+#ifndef CONF_EIC_SENSE6
+#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// <q> External Interrupt 6 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch6
+#ifndef CONF_EIC_ASYNCH6
+#define CONF_EIC_ASYNCH6 0
+#endif
+
+// </e>
+
+// <e> Interrupt 7 Settings
+// <id> eic_arch_enable_irq_setting7
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
+#define CONF_EIC_ENABLE_IRQ_SETTING7 1
+#endif
+
+// <q> External Interrupt 7 Filter Enable
+// <i> Indicates whether the external interrupt 7 filter is enabled or not
+// <id> eic_arch_filten7
+#ifndef CONF_EIC_FILTEN7
+#define CONF_EIC_FILTEN7 0
+#endif
+
+// <q> External Interrupt 7 Event Output Enable
+// <i> Indicates whether the external interrupt 7 event output is enabled or not
+// <id> eic_arch_extinteo7
+#ifndef CONF_EIC_EXTINTEO7
+#define CONF_EIC_EXTINTEO7 0
+#endif
+
+// <y> Input 7 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense7
+#ifndef CONF_EIC_SENSE7
+#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_RISE_Val
+#endif
+
+// <q> External Interrupt 7 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch7
+#ifndef CONF_EIC_ASYNCH7
+#define CONF_EIC_ASYNCH7 0
+#endif
+
+// </e>
+
+// <e> Interrupt 8 Settings
+// <id> eic_arch_enable_irq_setting8
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
+#define CONF_EIC_ENABLE_IRQ_SETTING8 0
+#endif
+
+// <q> External Interrupt 8 Filter Enable
+// <i> Indicates whether the external interrupt 8 filter is enabled or not
+// <id> eic_arch_filten8
+#ifndef CONF_EIC_FILTEN8
+#define CONF_EIC_FILTEN8 0
+#endif
+
+// <q> External Interrupt 8 Event Output Enable
+// <i> Indicates whether the external interrupt 8 event output is enabled or not
+// <id> eic_arch_extinteo8
+#ifndef CONF_EIC_EXTINTEO8
+#define CONF_EIC_EXTINTEO8 0
+#endif
+
+// <y> Input 8 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense8
+#ifndef CONF_EIC_SENSE8
+#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 8 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch8
+#ifndef CONF_EIC_ASYNCH8
+#define CONF_EIC_ASYNCH8 0
+#endif
+
+// </e>
+
+// <e> Interrupt 9 Settings
+// <id> eic_arch_enable_irq_setting9
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
+#define CONF_EIC_ENABLE_IRQ_SETTING9 0
+#endif
+
+// <q> External Interrupt 9 Filter Enable
+// <i> Indicates whether the external interrupt 9 filter is enabled or not
+// <id> eic_arch_filten9
+#ifndef CONF_EIC_FILTEN9
+#define CONF_EIC_FILTEN9 0
+#endif
+
+// <q> External Interrupt 9 Event Output Enable
+// <i> Indicates whether the external interrupt 9 event output is enabled or not
+// <id> eic_arch_extinteo9
+#ifndef CONF_EIC_EXTINTEO9
+#define CONF_EIC_EXTINTEO9 0
+#endif
+
+// <y> Input 9 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense9
+#ifndef CONF_EIC_SENSE9
+#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 9 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch9
+#ifndef CONF_EIC_ASYNCH9
+#define CONF_EIC_ASYNCH9 0
+#endif
+
+// </e>
+
+// <e> Interrupt 10 Settings
+// <id> eic_arch_enable_irq_setting10
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
+#define CONF_EIC_ENABLE_IRQ_SETTING10 0
+#endif
+
+// <q> External Interrupt 10 Filter Enable
+// <i> Indicates whether the external interrupt 10 filter is enabled or not
+// <id> eic_arch_filten10
+#ifndef CONF_EIC_FILTEN10
+#define CONF_EIC_FILTEN10 0
+#endif
+
+// <q> External Interrupt 10 Event Output Enable
+// <i> Indicates whether the external interrupt 10 event output is enabled or not
+// <id> eic_arch_extinteo10
+#ifndef CONF_EIC_EXTINTEO10
+#define CONF_EIC_EXTINTEO10 0
+#endif
+
+// <y> Input 10 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense10
+#ifndef CONF_EIC_SENSE10
+#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 10 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch10
+#ifndef CONF_EIC_ASYNCH10
+#define CONF_EIC_ASYNCH10 0
+#endif
+
+// </e>
+
+// <e> Interrupt 11 Settings
+// <id> eic_arch_enable_irq_setting11
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
+#define CONF_EIC_ENABLE_IRQ_SETTING11 0
+#endif
+
+// <q> External Interrupt 11 Filter Enable
+// <i> Indicates whether the external interrupt 11 filter is enabled or not
+// <id> eic_arch_filten11
+#ifndef CONF_EIC_FILTEN11
+#define CONF_EIC_FILTEN11 0
+#endif
+
+// <q> External Interrupt 11 Event Output Enable
+// <i> Indicates whether the external interrupt 11 event output is enabled or not
+// <id> eic_arch_extinteo11
+#ifndef CONF_EIC_EXTINTEO11
+#define CONF_EIC_EXTINTEO11 0
+#endif
+
+// <y> Input 11 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense11
+#ifndef CONF_EIC_SENSE11
+#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 11 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch11
+#ifndef CONF_EIC_ASYNCH11
+#define CONF_EIC_ASYNCH11 0
+#endif
+
+// </e>
+
+// <e> Interrupt 12 Settings
+// <id> eic_arch_enable_irq_setting12
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
+#define CONF_EIC_ENABLE_IRQ_SETTING12 0
+#endif
+
+// <q> External Interrupt 12 Filter Enable
+// <i> Indicates whether the external interrupt 12 filter is enabled or not
+// <id> eic_arch_filten12
+#ifndef CONF_EIC_FILTEN12
+#define CONF_EIC_FILTEN12 0
+#endif
+
+// <q> External Interrupt 12 Event Output Enable
+// <i> Indicates whether the external interrupt 12 event output is enabled or not
+// <id> eic_arch_extinteo12
+#ifndef CONF_EIC_EXTINTEO12
+#define CONF_EIC_EXTINTEO12 0
+#endif
+
+// <y> Input 12 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense12
+#ifndef CONF_EIC_SENSE12
+#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 12 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch12
+#ifndef CONF_EIC_ASYNCH12
+#define CONF_EIC_ASYNCH12 0
+#endif
+
+// </e>
+
+// <e> Interrupt 13 Settings
+// <id> eic_arch_enable_irq_setting13
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
+#define CONF_EIC_ENABLE_IRQ_SETTING13 0
+#endif
+
+// <q> External Interrupt 13 Filter Enable
+// <i> Indicates whether the external interrupt 13 filter is enabled or not
+// <id> eic_arch_filten13
+#ifndef CONF_EIC_FILTEN13
+#define CONF_EIC_FILTEN13 0
+#endif
+
+// <q> External Interrupt 13 Event Output Enable
+// <i> Indicates whether the external interrupt 13 event output is enabled or not
+// <id> eic_arch_extinteo13
+#ifndef CONF_EIC_EXTINTEO13
+#define CONF_EIC_EXTINTEO13 0
+#endif
+
+// <y> Input 13 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense13
+#ifndef CONF_EIC_SENSE13
+#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 13 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch13
+#ifndef CONF_EIC_ASYNCH13
+#define CONF_EIC_ASYNCH13 0
+#endif
+
+// </e>
+
+// <e> Interrupt 14 Settings
+// <id> eic_arch_enable_irq_setting14
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
+#define CONF_EIC_ENABLE_IRQ_SETTING14 0
+#endif
+
+// <q> External Interrupt 14 Filter Enable
+// <i> Indicates whether the external interrupt 14 filter is enabled or not
+// <id> eic_arch_filten14
+#ifndef CONF_EIC_FILTEN14
+#define CONF_EIC_FILTEN14 0
+#endif
+
+// <q> External Interrupt 14 Event Output Enable
+// <i> Indicates whether the external interrupt 14 event output is enabled or not
+// <id> eic_arch_extinteo14
+#ifndef CONF_EIC_EXTINTEO14
+#define CONF_EIC_EXTINTEO14 0
+#endif
+
+// <y> Input 14 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense14
+#ifndef CONF_EIC_SENSE14
+#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 14 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch14
+#ifndef CONF_EIC_ASYNCH14
+#define CONF_EIC_ASYNCH14 0
+#endif
+
+// </e>
+
+// <e> Interrupt 15 Settings
+// <id> eic_arch_enable_irq_setting15
+#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
+#define CONF_EIC_ENABLE_IRQ_SETTING15 0
+#endif
+
+// <q> External Interrupt 15 Filter Enable
+// <i> Indicates whether the external interrupt 15 filter is enabled or not
+// <id> eic_arch_filten15
+#ifndef CONF_EIC_FILTEN15
+#define CONF_EIC_FILTEN15 0
+#endif
+
+// <q> External Interrupt 15 Event Output Enable
+// <i> Indicates whether the external interrupt 15 event output is enabled or not
+// <id> eic_arch_extinteo15
+#ifndef CONF_EIC_EXTINTEO15
+#define CONF_EIC_EXTINTEO15 0
+#endif
+
+// <y> Input 15 Sense Configuration
+// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
+// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
+// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
+// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
+// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
+// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
+// <i> This defines input sense trigger
+// <id> eic_arch_sense15
+#ifndef CONF_EIC_SENSE15
+#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
+#endif
+
+// <q> External Interrupt 15 Asynchronous Edge Detection Mode
+// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
+// <id> eic_arch_asynch15
+#ifndef CONF_EIC_ASYNCH15
+#define CONF_EIC_ASYNCH15 0
+#endif
+
+// </e>
+
+#define CONFIG_EIC_EXTINT_MAP {5, PIN_PB05}, {6, PIN_PA22}, {7, PIN_PA23},
+
+// <<< end of configuration section >>>
+
+#endif // HPL_EIC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_gclk_config.h b/Smol Watch Project/My Project/Config/hpl_gclk_config.h
new file mode 100644
index 0000000..c56e281
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_gclk_config.h	
@@ -0,0 +1,383 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Generic clock generator 0 configuration
+// <i> Indicates whether generic clock 0 configuration is enabled or not
+// <id> enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 0 source
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
+// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
+// <i> This defines the clock source for generic clock generator 0
+// <id> gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 0 division <0x0000-0xFFFF>
+// <id> gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 1 configuration
+// <i> Indicates whether generic clock 1 configuration is enabled or not
+// <id> enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 1 source
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
+// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
+// <i> This defines the clock source for generic clock generator 1
+// <id> gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 1 division <0x0000-0xFFFF>
+// <id> gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 2 configuration
+// <i> Indicates whether generic clock 2 configuration is enabled or not
+// <id> enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 2 source
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
+// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
+// <i> This defines the clock source for generic clock generator 2
+// <id> gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 2 division <0x0000-0xFFFF>
+// <id> gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 3 configuration
+// <i> Indicates whether generic clock 3 configuration is enabled or not
+// <id> enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 3 source
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
+// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
+// <i> This defines the clock source for generic clock generator 3
+// <id> gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 1
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 1
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 3 division <0x0000-0xFFFF>
+// <id> gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 4 configuration
+// <i> Indicates whether generic clock 4 configuration is enabled or not
+// <id> enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 4 source
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
+// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
+// <i> This defines the clock source for generic clock generator 4
+// <id> gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 4 division <0x0000-0xFFFF>
+// <id> gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_mclk_config.h b/Smol Watch Project/My Project/Config/hpl_mclk_config.h
new file mode 100644
index 0000000..be1cd54
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_mclk_config.h	
@@ -0,0 +1,85 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
+#endif
+
+// <y> Backup Clock Division
+// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
+// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
+// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
+// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
+// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
+// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
+// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
+// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h b/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
new file mode 100644
index 0000000..55e297a
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h	
@@ -0,0 +1,173 @@
+/* Auto-generated config file hpl_osc32kctrl_config.h */
+#ifndef HPL_OSC32KCTRL_CONFIG_H
+#define HPL_OSC32KCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> RTC Source configuration
+// <id> enable_rtc_source
+#ifndef CONF_RTCCTRL_CONFIG
+#define CONF_RTCCTRL_CONFIG 0
+#endif
+
+// <h> RTC source control
+// <y> RTC Clock Source Selection
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <i> This defines the clock source for RTC
+// <id> rtc_source_oscillator
+#ifndef CONF_RTCCTRL_SRC
+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// <q> Use 1 kHz output
+// <id> rtc_1khz_selection
+#ifndef CONF_RTCCTRL_1KHZ
+
+#define CONF_RTCCTRL_1KHZ 1
+
+#endif
+
+#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
+#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
+#else
+#error unexpected CONF_RTCCTRL_SRC
+#endif
+
+// </h>
+// </e>
+// <e> SLCD Source configuration
+// <id> enable_slcd_source
+#ifndef CONF_SLCDCTRL_CONFIG
+#define CONF_SLCDCTRL_CONFIG 0
+#endif
+
+// <h> SLCD source control
+// <y> SLCD Clock Source Selection
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <i> This defines the clock source for SLCD
+// <id> slcd_source_oscillator
+#ifndef CONF_SLCDCTRL_SRC
+#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
+#endif
+
+// </h>
+// </e>
+// <e> 32kHz External Crystal Oscillator Configuration
+// <i> Indicates whether configuration for External 32K Osc is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 1
+#endif
+
+// <h> 32kHz External Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 1
+#endif
+
+// <o> Start-Up Time
+// <0x0=>62592us
+// <0x1=>125092us
+// <0x2=>500092us
+// <0x3=>1000092us
+// <0x4=>2000092us
+// <0x5=>4000092us
+// <0x6=>8000092us
+// <id> xosc32k_arch_startup
+#ifndef CONF_XOSC32K_STARTUP
+#define CONF_XOSC32K_STARTUP 0x0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc32k_arch_ondemand
+#ifndef CONF_XOSC32K_ONDEMAND
+#define CONF_XOSC32K_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc32k_arch_runstdby
+#ifndef CONF_XOSC32K_RUNSTDBY
+#define CONF_XOSC32K_RUNSTDBY 0
+#endif
+
+// <q> 1kHz Output Enable
+// <i> Indicates whether 1kHz Output is enabled or not
+// <id> xosc32k_arch_en1k
+#ifndef CONF_XOSC32K_EN1K
+#define CONF_XOSC32K_EN1K 1
+#endif
+
+// <q> 32kHz Output Enable
+// <i> Indicates whether 32kHz Output is enabled or not
+// <id> xosc32k_arch_en32k
+#ifndef CONF_XOSC32K_EN32K
+#define CONF_XOSC32K_EN32K 1
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc32k_arch_swben
+#ifndef CONF_XOSC32K_SWBEN
+#define CONF_XOSC32K_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc32k_arch_cfden
+#ifndef CONF_XOSC32K_CFDEN
+#define CONF_XOSC32K_CFDEN 0
+#endif
+
+// <q> Clock Failure Detector Event Out
+// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
+// <id> xosc32k_arch_cfdeo
+#ifndef CONF_XOSC32K_CFDEO
+#define CONF_XOSC32K_CFDEO 0
+#endif
+
+// <q> Crystal connected to XIN32/XOUT32 Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc32k_arch_xtalen
+#ifndef CONF_XOSC32K_XTALEN
+#define CONF_XOSC32K_XTALEN 1
+#endif
+
+// </h>
+// </e>
+
+// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
+// <i> Indicates whether configuration for OSCULP32K is enabled or not
+// <id> enable_osculp32k
+#ifndef CONF_OSCULP32K_CONFIG
+#define CONF_OSCULP32K_CONFIG 1
+#endif
+
+// <h> 32kHz Ultra Low Power Internal Oscillator Control
+
+// <q> Oscillator Calibration Control
+// <i> Indicates whether Oscillator Calibration is enabled or not
+// <id> osculp32k_calib_enable
+#ifndef CONF_OSCULP32K_CALIB_ENABLE
+#define CONF_OSCULP32K_CALIB_ENABLE 0
+#endif
+
+// <o> Oscillator Calibration <0x0-0x1F>
+// <id> osculp32k_calib
+#ifndef CONF_OSCULP32K_CALIB
+#define CONF_OSCULP32K_CALIB 0x0
+#endif
+
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSC32KCTRL_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h b/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
new file mode 100644
index 0000000..ba2d42e
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_oscctrl_config.h	
@@ -0,0 +1,483 @@
+/* Auto-generated config file hpl_oscctrl_config.h */
+#ifndef HPL_OSCCTRL_CONFIG_H
+#define HPL_OSCCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> External Multipurpose Crystal Oscillator Configuration
+// <i> Indicates whether configuration for XOSC is enabled or not
+// <id> enable_xosc
+#ifndef CONF_XOSC_CONFIG
+#define CONF_XOSC_CONFIG 0
+#endif
+
+// <o> Frequency <400000-32000000>
+// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
+// <id> xosc_frequency
+#ifndef CONF_XOSC_FREQUENCY
+#define CONF_XOSC_FREQUENCY 400000
+#endif
+
+// <h> External Multipurpose Crystal Oscillator Control
+// <q> Oscillator enable
+// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
+// <id> xosc_arch_enable
+#ifndef CONF_XOSC_ENABLE
+#define CONF_XOSC_ENABLE 0
+#endif
+
+// <o> Start-Up Time
+// <0x0=>31us
+// <0x1=>61us
+// <0x2=>122us
+// <0x3=>244us
+// <0x4=>488us
+// <0x5=>977us
+// <0x6=>1953us
+// <0x7=>3906us
+// <0x8=>7813us
+// <0x9=>15625us
+// <0xA=>31250us
+// <0xB=>62500us
+// <0xC=>125000us
+// <0xD=>250000us
+// <0xE=>500000us
+// <0xF=>1000000us
+// <id> xosc_arch_startup
+#ifndef CONF_XOSC_STARTUP
+#define CONF_XOSC_STARTUP 0x0
+#endif
+
+// <q> Automatic Amplitude Gain Control
+// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not
+// <id> xosc_arch_ampgc
+#ifndef CONF_XOSC_AMPGC
+#define CONF_XOSC_AMPGC 0
+#endif
+
+// <o> External Multipurpose Crystal Oscillator Gain
+// <0x0=>2MHz
+// <0x1=>4MHz
+// <0x2=>8MHz
+// <0x3=>16MHz
+// <0x4=>30MHz
+// <id> xosc_arch_gain
+#ifndef CONF_XOSC_GAIN
+#define CONF_XOSC_GAIN 0x0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> xosc_arch_ondemand
+#ifndef CONF_XOSC_ONDEMAND
+#define CONF_XOSC_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> xosc_arch_runstdby
+#ifndef CONF_XOSC_RUNSTDBY
+#define CONF_XOSC_RUNSTDBY 0
+#endif
+
+// <q> Clock Switch Back
+// <i> Indicates whether Clock Switch Back is enabled or not
+// <id> xosc_arch_swben
+#ifndef CONF_XOSC_SWBEN
+#define CONF_XOSC_SWBEN 0
+#endif
+
+// <q> Clock Failure Detector
+// <i> Indicates whether Clock Failure Detector is enabled or not
+// <id> xosc_arch_cfden
+#ifndef CONF_XOSC_CFDEN
+#define CONF_XOSC_CFDEN 0
+#endif
+
+// <q> Clock Failure Detector Event Out
+// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
+// <id> xosc_arch_cfdeo
+#ifndef CONF_XOSC_CFDEO
+#define CONF_XOSC_CFDEO 0
+#endif
+
+// <q> Crystal connected to XIN/XOUT Enable
+// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
+// <id> xosc_arch_xtalen
+#ifndef CONF_XOSC_XTALEN
+#define CONF_XOSC_XTALEN 0
+#endif
+//</h>
+//</e>
+
+// <e> 16MHz Internal Oscillator Configuration
+// <i> Indicates whether configuration for OSC8M is enabled or not
+// <id> enable_osc16m
+#ifndef CONF_OSC16M_CONFIG
+#define CONF_OSC16M_CONFIG 1
+#endif
+
+// <h> 16MHz Internal Oscillator Control
+// <q> Enable
+// <i> Indicates whether 16MHz Internal Oscillator is enabled or not
+// <id> osc16m_arch_enable
+#ifndef CONF_OSC16M_ENABLE
+#define CONF_OSC16M_ENABLE 1
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> osc16m_arch_ondemand
+#ifndef CONF_OSC16M_ONDEMAND
+#define CONF_OSC16M_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> osc16m_arch_runstdby
+#ifndef CONF_OSC16M_RUNSTDBY
+#define CONF_OSC16M_RUNSTDBY 0
+#endif
+
+// <y> Oscillator Frequency Selection(Mhz)
+// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4
+// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8
+// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12
+// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16
+// <i> This defines the oscillator frequency (Mhz)
+// <id> osc16m_freq
+#ifndef CONF_OSC16M_FSEL
+#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
+#endif
+
+// <q> Oscillator Calibration Control
+// <i> Indicates whether Oscillator Calibration is enabled or not
+// <id> osc16m_arch_calib_enable
+#ifndef CONF_OSC16M_CALIB_ENABLE
+#define CONF_OSC16M_CALIB_ENABLE 0
+#endif
+
+// <o> 4MHz Frequency Calibration <0x0-0x3F>
+// <id> osc16m_arch_4m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_4M_FCAL 0
+#endif
+
+// <o> 4MHz Temperature Calibration <0x0-0x3F>
+// <id> osc16m_arch_4m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_4M_TCAL 0
+#endif
+
+// <o> 8MHz Frequency Calibration <0x0-0x3F>
+// <id> osc16m_arch_8m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_8M_FCAL 0
+#endif
+
+// <o> 8MHz Temperature Calibration <0x0-0x3F>
+// <id> osc16m_arch_8m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_8M_TCAL 0
+#endif
+
+// <o> 12MHz Frequency Calibration <0x0-0x3F>
+// <id> osc16m_arch_12m_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_12M_FCAL 0
+#endif
+
+// <o> 12MHz Temperature Calibration <0x0-0x3F>
+// <id> osc16m_arch_12m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_12M_TCAL 0
+#endif
+
+// <o> 16MHz Frequency Calibration <0x0-0x3F>
+// <id> osc16m_arch_fcal
+#ifndef CONF_OSC16M_FCAL
+#define CONF_OSC16M_16M_FCAL 0
+#endif
+
+// <o> 16MHz Temperature Calibration <0x0-0x3F>
+// <id> osc16m_arch_16m_tcal
+#ifndef CONF_OSC16M_TCAL
+#define CONF_OSC16M_16M_TCAL 0
+#endif
+//</h>
+//</e>
+
+// <e> DFLL Configuration
+// <i> Indicates whether configuration for DFLL is enabled or not
+// <id> enable_dfll48m
+#ifndef CONF_DFLL_CONFIG
+#define CONF_DFLL_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <i> Select the clock source.
+// <id> dfll48m_ref_clock
+#ifndef CONF_DFLL_GCLK
+#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+// <h> Digital Frequency Locked Loop Control
+// <q> DFLL Enable
+// <i> Indicates whether DFLL is enabled or not
+// <id> dfll48m_arch_enable
+#ifndef CONF_DFLL_ENABLE
+#define CONF_DFLL_ENABLE 0
+#endif
+
+// <q> Wait Lock
+// <i> Indicates whether Wait Lock is enabled or not
+// <id> dfll_arch_waitlock
+#ifndef CONF_DFLL_WAITLOCK
+#define CONF_DFLL_WAITLOCK 0
+#endif
+
+// <q> Bypass Coarse Lock
+// <i> Indicates whether Bypass Coarse Lock is enabled or not
+// <id> dfll_arch_bplckc
+#ifndef CONF_DFLL_BPLCKC
+#define CONF_DFLL_BPLCKC 0
+#endif
+
+// <q> Quick Lock Disable
+// <i> Indicates whether Quick Lock Disable is enabled or not
+// <id> dfll_arch_qldis
+#ifndef CONF_DFLL_QLDIS
+#define CONF_DFLL_QLDIS 0
+#endif
+
+// <q> Chill Cycle Disable
+// <i> Indicates whether Chill Cycle Disable is enabled or not
+// <id> dfll_arch_ccdis
+#ifndef CONF_DFLL_CCDIS
+#define CONF_DFLL_CCDIS 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> dfll_arch_ondemand
+#ifndef CONF_DFLL_ONDEMAND
+#define CONF_DFLL_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> dfll_arch_runstdby
+#ifndef CONF_DFLL_RUNSTDBY
+#define CONF_DFLL_RUNSTDBY 0
+#endif
+
+// <q> USB Clock Recovery Mode
+// <i> Indicates whether USB Clock Recovery Mode is enabled or not
+// <id> dfll_arch_usbcrm
+#ifndef CONF_DFLL_USBCRM
+#define CONF_DFLL_USBCRM 0
+#endif
+
+// <q> Lose Lock After Wake
+// <i> Indicates whether Lose Lock After Wake is enabled or not
+// <id> dfll_arch_llaw
+#ifndef CONF_DFLL_LLAW
+#define CONF_DFLL_LLAW 0
+#endif
+
+// <q> Stable DFLL Frequency
+// <i> Indicates whether Stable DFLL Frequency is enabled or not
+// <id> dfll_arch_stable
+#ifndef CONF_DFLL_STABLE
+#define CONF_DFLL_STABLE 0
+#endif
+
+// <o> Operating Mode Selection
+// <0=>Open Loop Mode
+// <1=>Closed Loop Mode
+// <id> dfll48m_mode
+#ifndef CONF_DFLL_MODE
+#define CONF_DFLL_MODE 0
+#endif
+
+// <o> Coarse Maximum Step <0x0-0x1F>
+// <id> dfll_arch_cstep
+#ifndef CONF_DFLL_CSTEP
+#define CONF_DFLL_CSTEP 1
+#endif
+
+// <o> Fine Maximum Step <0x0-0x3FF>
+// <id> dfll_arch_fstep
+#ifndef CONF_DFLL_FSTEP
+#define CONF_DFLL_FSTEP 1
+#endif
+
+// <o> DFLL Multiply Factor <0x0-0xFFFF>
+//  <id> dfll48m_mul
+#ifndef CONF_DFLL_MUL
+#define CONF_DFLL_MUL 0
+#endif
+
+// <e> DFLL Calibration Overwrite
+// <i> Indicates whether Overwrite Calibration value of DFLL
+// <id> dfll_arch_calibration
+#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
+#define CONF_DFLL_OVERWRITE_CALIBRATION 0
+#endif
+
+// <o> Coarse Value <0x0-0x3F>
+// <id> dfll_arch_coarse
+#ifndef CONF_DFLL_COARSE
+#define CONF_DFLL_COARSE (0x1f / 4)
+#endif
+
+// <o> Fine Value <0x0-0x3FF>
+// <id> dfll_arch_fine
+#ifndef CONF_DFLL_FINE
+#define CONF_DFLL_FINE (0x200)
+#endif
+
+//</e>
+
+//</h>
+
+//</e>
+
+// <e> DPLL Configuration
+// <i> Indicates whether configuration for DPLL is enabled or not
+// <id> enable_fdpll96m
+#ifndef CONF_DPLL_CONFIG
+#define CONF_DPLL_CONFIG 0
+#endif
+
+// <y> Reference Clock Source
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+// <i> Select the clock source.
+// <id> fdpll96m_ref_clock
+#ifndef CONF_DPLL_GCLK
+#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
+
+#endif
+
+// <h> Digital Phase Locked Loop Control
+// <q> Enable
+// <i> Indicates whether Digital Phase Locked Loop is enabled or not
+// <id> fdpll96m_arch_enable
+#ifndef CONF_DPLL_ENABLE
+#define CONF_DPLL_ENABLE 0
+#endif
+
+// <q> On Demand Control
+// <i> Indicates whether On Demand Control is enabled or not
+// <id> fdpll96m_arch_ondemand
+#ifndef CONF_DPLL_ONDEMAND
+#define CONF_DPLL_ONDEMAND 1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> fdpll96m_arch_runstdby
+#ifndef CONF_DPLL_RUNSTDBY
+#define CONF_DPLL_RUNSTDBY 0
+#endif
+
+// <o> Loop Divider Ratio Fractional Part <0x0-0xF>
+// <id> fdpll96m_ldrfrac
+#ifndef CONF_DPLL_LDRFRAC
+#define CONF_DPLL_LDRFRAC 0xd
+#endif
+
+// <o> Loop Divider Ratio Integer Part <0x0-0xFFF>
+// <id> fdpll96m_ldr
+#ifndef CONF_DPLL_LDR
+#define CONF_DPLL_LDR 0x5b7
+#endif
+
+// <o> Clock Divider <0x0-0x3FF>
+// <id> fdpll96m_clock_div
+#ifndef CONF_DPLL_DIV
+#define CONF_DPLL_DIV 0
+#endif
+
+// <q> Lock Bypass
+// <i> Indicates whether Lock Bypass is enabled or not
+// <id> fdpll96m_arch_lbypass
+#ifndef CONF_DPLL_LBYPASS
+#define CONF_DPLL_LBYPASS 0
+#endif
+
+// <o> Lock Time
+// <0=>No time-out, automatic lock
+// <4=>The Time-out if no lock within 8 ms
+// <5=>The Time-out if no lock within 9 ms
+// <6=>The Time-out if no lock within 10 ms
+// <7=>The Time-out if no lock within 11 ms
+// <id> fdpll96m_arch_ltime
+#ifndef CONF_DPLL_LTIME
+#define CONF_DPLL_LTIME 0
+#endif
+
+// <o> Reference Clock Selection
+// <0=>XOSC32K clock reference
+// <1=>XOSC clock reference
+// <2=>GCLK clock reference
+// <id> fdpll96m_arch_refclk
+#ifndef CONF_DPLL_REFCLK
+#define CONF_DPLL_REFCLK 0
+#endif
+
+// <q> Wake Up Fast
+// <i> Indicates whether Wake Up Fast is enabled or not
+// <id> fdpll96m_arch_wuf
+#ifndef CONF_DPLL_WUF
+#define CONF_DPLL_WUF 0
+#endif
+
+// <q> Low-Power Enable
+// <i> Indicates whether Low-Power Enable is enabled or not
+// <id> fdpll96m_arch_lpen
+#ifndef CONF_DPLL_LPEN
+#define CONF_DPLL_LPEN 0
+#endif
+
+// <o> Reference Clock Selection
+// <0=>Default filter mode
+// <1=>Low bandwidth filter
+// <2=>High bandwidth filter
+// <3=>High damping filter
+// <id> fdpll96m_arch_filter
+#ifndef CONF_DPLL_FILTER
+#define CONF_DPLL_FILTER 0
+#endif
+
+// <y> Output Clock Prescaler
+// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1
+// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2
+// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4
+// <id> fdpll96m_presc
+#ifndef CONF_DPLL_PRESC
+#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
+#endif
+//</h>
+//</e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_OSCCTRL_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_port_config.h b/Smol Watch Project/My Project/Config/hpl_port_config.h
new file mode 100644
index 0000000..1efce33
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_port_config.h	
@@ -0,0 +1,284 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> PORT Input Event 0 configuration
+// <id> enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 0
+#endif
+
+// <h> PORT Input Event 0 configuration on PORT A
+
+// <q> PORTA Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// <id> porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 0
+// <id> porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+// <h> PORT Input Event 0 configuration on PORT B
+
+// <q> PORTB Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// <id> portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 0
+// <id> portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 1 configuration
+// <id> enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 0
+#endif
+
+// <h> PORT Input Event 1 configuration on PORT A
+
+// <q> PORTA Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// <id> porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 1
+// <id> porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+// <h> PORT Input Event 1 configuration on PORT B
+
+// <q> PORTB Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// <id> portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 1
+// <id> portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 2 configuration
+// <id> enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 0
+#endif
+
+// <h> PORT Input Event 2 configuration on PORT A
+
+// <q> PORTA Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// <id> porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 2
+// <id> porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+// <h> PORT Input Event 2 configuration on PORT B
+
+// <q> PORTB Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// <id> portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 2
+// <id> portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 3 configuration
+// <id> enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 0
+#endif
+
+// <h> PORT Input Event 3 configuration on PORT A
+
+// <q> PORTA Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// <id> porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 3
+// <id> porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+// <h> PORT Input Event 3 configuration on PORT B
+
+// <q> PORTB Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// <id> portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 3
+// <id> portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+
+// </e>
+
+#define CONF_PORTA_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_rtc_config.h b/Smol Watch Project/My Project/Config/hpl_rtc_config.h
new file mode 100644
index 0000000..174f77a
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_rtc_config.h	
@@ -0,0 +1,318 @@
+/* Auto-generated config file hpl_rtc_config.h */
+#ifndef HPL_RTC_CONFIG_H
+#define HPL_RTC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic settings
+
+#ifndef CONF_RTC_ENABLE
+#define CONF_RTC_ENABLE 1
+#endif
+
+// <q> Force reset RTC on initialization
+// <i> Force RTC to reset on initialization.
+// <i> Note that the previous power down data in RTC is lost if it's enabled.
+// <id> rtc_arch_init_reset
+#ifndef CONF_RTC_INIT_RESET
+#define CONF_RTC_INIT_RESET 1
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>OFF(Peripheral clock divided by 1)
+// <0x1=>Peripheral clock divided by 1
+// <0x2=>Peripheral clock divided by 2
+// <0x3=>Peripheral clock divided by 4
+// <0x4=>Peripheral clock divided by 8
+// <0x5=>Peripheral clock divided by 16
+// <0x6=>Peripheral clock divided by 32
+// <0x7=>Peripheral clock divided by 64
+// <0x8=>Peripheral clock divided by 128
+// <0x9=>Peripheral clock divided by 256
+// <0xA=>Peripheral clock divided by 512
+// <0xB=>Peripheral clock divided by 1024
+// <i> These bits define the RTC clock relative to the peripheral clock
+// <id> rtc_arch_prescaler
+#ifndef CONF_RTC_PRESCALER
+
+#define CONF_RTC_PRESCALER 0xb
+
+#endif
+
+#ifndef CONF_RTC_COMP_VAL
+
+#define CONF_RTC_COMP_VAL 0
+
+#endif
+
+// <e> RTC Tamper Input 0 settings
+// <id> tamper_input_0_settings
+#ifndef CONF_TAMPER_INPUT_0_SETTINGS
+#define CONF_TAMPER_INPUT_0_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 0 level
+// <id> tamper_level_0
+#ifndef CONF_RTC_TAMP_LVL_0
+#define CONF_RTC_TAMP_LVL_0 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_0
+#ifndef CONF_RTC_TAMPER_INACT_0
+#define CONF_RTC_TAMPER_INACT_0 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 0
+// <id> tamper_debounce_enable_0
+#ifndef CONF_RTC_TAMP_DEBNC_0
+#define CONF_RTC_TAMP_DEBNC_0 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 1 settings
+// <id> tamper_input_1_settings
+#ifndef CONF_TAMPER_INPUT_1_SETTINGS
+#define CONF_TAMPER_INPUT_1_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 1 level
+// <id> tamper_level_1
+#ifndef CONF_RTC_TAMP_LVL_1
+#define CONF_RTC_TAMP_LVL_1 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_1
+#ifndef CONF_RTC_TAMPER_INACT_1
+#define CONF_RTC_TAMPER_INACT_1 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 1
+// <id> tamper_debounce_enable_1
+#ifndef CONF_RTC_TAMP_DEBNC_1
+#define CONF_RTC_TAMP_DEBNC_1 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 2 settings
+// <id> tamper_input_2_settings
+#ifndef CONF_TAMPER_INPUT_2_SETTINGS
+#define CONF_TAMPER_INPUT_2_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 2 level
+// <id> tamper_level_2
+#ifndef CONF_RTC_TAMP_LVL_2
+#define CONF_RTC_TAMP_LVL_2 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_2
+#ifndef CONF_RTC_TAMPER_INACT_2
+#define CONF_RTC_TAMPER_INACT_2 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 2
+// <id> tamper_debounce_enable_2
+#ifndef CONF_RTC_TAMP_DEBNC_2
+#define CONF_RTC_TAMP_DEBNC_2 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 3 settings
+// <id> tamper_input_3_settings
+#ifndef CONF_TAMPER_INPUT_3_SETTINGS
+#define CONF_TAMPER_INPUT_3_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 3 level
+// <id> tamper_level_3
+#ifndef CONF_RTC_TAMP_LVL_3
+#define CONF_RTC_TAMP_LVL_3 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_3
+#ifndef CONF_RTC_TAMPER_INACT_3
+#define CONF_RTC_TAMPER_INACT_3 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 3
+// <id> tamper_debounce_enable_3
+#ifndef CONF_RTC_TAMP_DEBNC_3
+#define CONF_RTC_TAMP_DEBNC_3 0
+#endif
+
+// </e>
+
+// <e> RTC Tamper Input 4 settings
+// <id> tamper_input_4_settings
+#ifndef CONF_TAMPER_INPUT_4_SETTINGS
+#define CONF_TAMPER_INPUT_4_SETTINGS 0
+#endif
+
+// <q> Tamper Level Settings
+// <i> Indicates Tamper input 4 level
+// <id> tamper_level_4
+#ifndef CONF_RTC_TAMP_LVL_4
+#define CONF_RTC_TAMP_LVL_4 0
+#endif
+
+// <o> RTC Tamper Input Action
+// <0x0=>OFF(Disabled)
+// <0x1=>Wake and Set Tamper Flag
+// <0x2=>Capture Timestamp and Set Tamper Flag
+// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
+// <i> These bits define the RTC Tamper Input Action to be performed
+// <id> rtc_tamper_input_action_4
+#ifndef CONF_RTC_TAMPER_INACT_4
+#define CONF_RTC_TAMPER_INACT_4 0
+#endif
+
+// <q> Debounce Enable for Tamper Input
+// <i> Indicates Debounce should be enabled for Tamper input 4
+// <id> tamper_debounce_enable_4
+#ifndef CONF_RTC_TAMP_DEBNC_4
+#define CONF_RTC_TAMP_DEBNC_4 0
+#endif
+
+// </e>
+
+// <o> RTC Tamper Active Layer Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
+// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
+// <id> rtc_tamper_active_layer_frequency_prescalar
+#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
+#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
+#endif
+
+// <o> RTC Tamper Debounce Frequency Prescalar
+// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
+// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
+// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
+// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
+// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
+// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
+// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
+// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
+// <i> These bits define the RTC Debounce Frequency Prescalar
+// <id> rtc_tamper_debounce_frequency_prescalar
+#ifndef CONF_RTC_TAMP_DEBF_PRES
+#define CONF_RTC_TAMP_DEBF_PRES 0
+#endif
+
+// <e> Event control
+// <id> rtc_event_control
+#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
+#define CONF_RTC_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Periodic Interval 0 Event Output
+// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
+// <id> rtc_pereo0
+#ifndef CONF_RTC_PEREO0
+#define CONF_RTC_PEREO0 0
+#endif
+// <q> Periodic Interval 1 Event Output
+// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
+// <id> rtc_pereo1
+#ifndef CONF_RTC_PEREO1
+#define CONF_RTC_PEREO1 0
+#endif
+// <q> Periodic Interval 2 Event Output
+// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
+// <id> rtc_pereo2
+#ifndef CONF_RTC_PEREO2
+#define CONF_RTC_PEREO2 0
+#endif
+// <q> Periodic Interval 3 Event Output
+// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
+// <id> rtc_pereo3
+#ifndef CONF_RTC_PEREO3
+#define CONF_RTC_PEREO3 0
+#endif
+// <q> Periodic Interval 4 Event Output
+// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
+// <id> rtc_pereo4
+#ifndef CONF_RTC_PEREO4
+#define CONF_RTC_PEREO4 0
+#endif
+// <q> Periodic Interval 5 Event Output
+// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
+// <id> rtc_pereo5
+#ifndef CONF_RTC_PEREO5
+#define CONF_RTC_PEREO5 0
+#endif
+// <q> Periodic Interval 6 Event Output
+// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
+// <id> rtc_pereo6
+#ifndef CONF_RTC_PEREO6
+#define CONF_RTC_PEREO6 0
+#endif
+// <q> Periodic Interval 7 Event Output
+// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
+// <id> rtc_pereo7
+#ifndef CONF_RTC_PEREO7
+#define CONF_RTC_PEREO7 0
+#endif
+
+// <q> Compare 0 Event Output
+// <i> This bit indicates whether Compare O event is enabled and will be generated
+// <id> rtc_cmpeo0
+#ifndef CONF_RTC_COMPE0
+#define CONF_RTC_COMPE0 0
+#endif
+
+// <q> Overflow Event Output
+// <i> This bit indicates whether Overflow event is enabled and will be generated
+// <id> rtc_ovfeo
+#ifndef CONF_RTC_OVFEO
+#define CONF_RTC_OVFEO 0
+#endif
+
+// </e>
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_RTC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_sercom_config.h b/Smol Watch Project/My Project/Config/hpl_sercom_config.h
new file mode 100644
index 0000000..ad16e64
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_sercom_config.h	
@@ -0,0 +1,144 @@
+/* Auto-generated config file hpl_sercom_config.h */
+#ifndef HPL_SERCOM_CONFIG_H
+#define HPL_SERCOM_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_1_I2CM_ENABLE
+#define CONF_SERCOM_1_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_1_I2CM_BAUD
+#define CONF_SERCOM_1_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
+#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
+#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
+#define CONF_SERCOM_1_I2CM_LOWTOUT 0
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_1_I2CM_INACTOUT
+#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
+#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
+#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_1_I2CM_SPEED
+#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_1_I2CM_TRISE
+#define CONF_SERCOM_1_I2CM_TRISE 215U
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U)                                              \
+	   - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U)    \
+	      / 1000U))                                                                                                    \
+	      * 10U                                                                                                        \
+	  + 5U)                                                                                                            \
+	 / (CONF_SERCOM_1_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
+#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_1_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SERCOM_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_slcd_config.h b/Smol Watch Project/My Project/Config/hpl_slcd_config.h
new file mode 100644
index 0000000..e3bb1bd
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_slcd_config.h	
@@ -0,0 +1,2744 @@
+/* Auto-generated config file hpl_slcd_config.h */
+#ifndef HPL_SLCD_CONFIG_H
+#define HPL_SLCD_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <hpl_slcd_cm.h>
+#include <peripheral_clk_config.h>
+
+// <h> Standard configuration
+
+// <o> Number of COM Lines
+// <i> Number of COM Lines
+// <0=>1
+// <1=>2
+// <2=>3
+// <3=>4
+// <4=>6
+// <5=>8
+// <id> slcd_arch_com_num
+#ifndef CONF_SLCD_COM_NUM
+#define CONF_SLCD_COM_NUM 2
+#endif
+
+// <o> Number of Segment Lines <1-44>
+// <i> Number of Segment Lines
+// <id> slcd_arch_seg_num
+#ifndef CONF_SLCD_SEG_NUM
+#define CONF_SLCD_SEG_NUM 24
+#endif
+
+#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42
+#warning Segment number should less than or equals to 42
+#endif
+#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40
+#warning Segment number should less than or equals to 40
+#endif
+
+// <o> Bias
+// <i> Bias Settting
+// <0=>STATIC
+// <1=>HALF
+// <2=>THIRD
+// <3=>FOURTH
+// <id> slcd_arch_bias
+#ifndef CONF_SLCD_BIAS
+#define CONF_SLCD_BIAS 2
+#endif
+
+#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0
+#warning Recommended Bias for 1 common terminal is STATIC
+#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1
+#warning Recommended Bias for 2 Common Terminals is HALF
+#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2
+#warning Recommended Bias for 3/4/6 Common Terminals is THIRD
+#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3
+#warning Recommended Bias for 8 Common Terminals is FOURTH
+#endif
+
+// <q> Bias Buffer Enable
+// <i> Enable Bias Buffer
+// <id> slcd_arch_bben
+#ifndef CONF_SLCD_BBEN
+#define CONF_SLCD_BBEN 1
+#endif
+
+// <o> Bias Buffer Enable Duration <1-16>
+// <i> Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source
+// <id> slcd_arch_bbd
+#ifndef CONF_SLCD_BBD
+#define CONF_SLCD_BBD 2
+#endif
+
+// <o> Clock Prescaler
+// <i> Setting for LCD frame frequency
+// <0=>16
+// <1=>32
+// <2=>64
+// <3=>128
+// <id> slcd_arch_presc
+#ifndef CONF_SLCD_PRESC
+#define CONF_SLCD_PRESC 2
+#endif
+
+// <o> Clock Divider
+// <i> Setting for LCD frame frequency
+// <0=>1
+// <1=>2
+// <2=>3
+// <3=>4
+// <4=>5
+// <5=>6
+// <6=>7
+// <7=>8
+// <id> slcd_arch_ckdiv
+#ifndef CONF_SLCD_CKDIV
+#define CONF_SLCD_CKDIV 3
+#endif
+
+/* TODO add frame frequency check */
+
+// <o> Reference Refresh Frequency
+// <i> Setting for Reference Refresh Frequency
+// <0=>2kHz
+// <1=>1kHz
+// <2=>500Hz
+// <3=>250Hz
+// <4=>125Hz
+// <5=>62.5Hz
+// <id> slcd_arch_rrf
+#ifndef CONF_SLCD_RRF
+#define CONF_SLCD_RRF 0
+#endif
+
+// <o> Power Refresh Frequency
+// <i> Setting for Charge pump Refresh Frequency
+// <0=>2kHz
+// <1=>1kHz
+// <2=>500Hz
+// <3=>250Hz
+// <id> slcd_arch_prf
+#ifndef CONF_SLCD_PRF
+#define CONF_SLCD_PRF 3
+#endif
+
+// <q> External VLCD
+// <i> Setting for how VLCD is generated
+// <id> slcd_arch_xvlcd
+#ifndef CONF_SLCD_XVLCD
+#define CONF_SLCD_XVLCD 0
+#endif
+
+// <o> Waveform Mode
+// <i> Setting for Waveform Mode
+// <0=>Low Power Waveform(frame-inversion)
+// <1=>Standard Waveform Mode(bit-inversion)
+// <id> slcd_arch_wmod
+#ifndef CONF_SLCD_WMOD
+#define CONF_SLCD_WMOD 0
+#endif
+
+// <o> Contrast Adjustment
+// <i> The contrast of the LCD is determined by the value of VLCD voltage.
+// <i> The higher the VLCD voltage, the higher is the contrast.
+// <i> The software contrast adjustment is only possible in internal supply mode.
+// <0=>2.5056V
+// <1=>2.5731V
+// <2=>2.6379V
+// <3=>2.7054V
+// <4=>2.7729V
+// <5=>2.8404V
+// <6=>2.9052V
+// <7=>2.9727V
+// <8=>3.0402V
+// <9=>3.1077V
+// <10=>3.1725V
+// <11=>3.24V
+// <12=>3.3075V
+// <13=>3.375V
+// <14=>3.4398V
+// <15=>3.5073V
+// <id> slcd_arch_contrast_adjust
+#ifndef CONF_SLCD_CONTRAST_ADJUST
+#define CONF_SLCD_CONTRAST_ADJUST 14
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> slcd_arch_advanced_settings
+#ifndef CONF_SLCD_ADVANCED_SETTINGS
+#define CONF_SLCD_ADVANCED_SETTINGS 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the SLCD will continue running in standby sleep mode or not
+// <id> slcd_arch_runstdby
+#ifndef CONF_SLCD_RUNSTDBY
+#define CONF_SLCD_RUNSTDBY 0
+#endif
+
+// </e>
+
+#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100
+#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect.
+#endif
+
+#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY))
+#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY)
+#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY))
+
+// <e> Character Mapping Setting
+// <id> slcd_arch_cm_setting
+#ifndef CONF_SLCD_CM_ENABLE
+#define CONF_SLCD_CM_ENABLE 0
+#endif
+
+// <e> 7 Segment Character Mapping Setting
+// <id> slcd_arch_cm_7segs_setting
+#ifndef CONF_SLCD_CM_7SEGS_SETTING
+#define CONF_SLCD_CM_7SEGS_SETTING 0
+#endif
+
+// <o> Segment 0 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_0_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_0_SETTING
+#define CONF_SLCD_CM_7SEGS_0_SETTING 0
+#endif
+// <o> Segment 1 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_1_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_1_SETTING
+#define CONF_SLCD_CM_7SEGS_1_SETTING 1
+#endif
+// <o> Segment 2 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_2_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_2_SETTING
+#define CONF_SLCD_CM_7SEGS_2_SETTING 2
+#endif
+// <o> Segment 3 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_3_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_3_SETTING
+#define CONF_SLCD_CM_7SEGS_3_SETTING 3
+#endif
+// <o> Segment 4 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_4_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_4_SETTING
+#define CONF_SLCD_CM_7SEGS_4_SETTING 4
+#endif
+// <o> Segment 5 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_5_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_5_SETTING
+#define CONF_SLCD_CM_7SEGS_5_SETTING 5
+#endif
+// <o> Segment 6 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_7segs_6_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_7SEGS_6_SETTING
+#define CONF_SLCD_CM_7SEGS_6_SETTING 6
+#endif
+
+// </e>
+
+// <e> 14 Segment Character Mapping Setting
+// <id> slcd_arch_cm_14segs_enable
+#ifndef CONF_SLCD_CM_14SEGS_ENABLE
+#define CONF_SLCD_CM_14SEGS_ENABLE 0
+#endif
+
+// <o> Segments 0 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_0_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_0_SETTING
+#define CONF_SLCD_CM_14SEGS_0_SETTING 0
+#endif
+
+// <o> Segments 1 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_1_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_1_SETTING
+#define CONF_SLCD_CM_14SEGS_1_SETTING 1
+#endif
+
+// <o> Segments 2 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_2_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_2_SETTING
+#define CONF_SLCD_CM_14SEGS_2_SETTING 2
+#endif
+
+// <o> Segments 3 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_3_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_3_SETTING
+#define CONF_SLCD_CM_14SEGS_3_SETTING 3
+#endif
+
+// <o> Segments 4 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_4_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_4_SETTING
+#define CONF_SLCD_CM_14SEGS_4_SETTING 4
+#endif
+
+// <o> Segments 5 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_5_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_5_SETTING
+#define CONF_SLCD_CM_14SEGS_5_SETTING 5
+#endif
+
+// <o> Segments 6 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_6_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_6_SETTING
+#define CONF_SLCD_CM_14SEGS_6_SETTING 6
+#endif
+
+// <o> Segments 7 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_7_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_7_SETTING
+#define CONF_SLCD_CM_14SEGS_7_SETTING 7
+#endif
+
+// <o> Segments 8 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_8_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_8_SETTING
+#define CONF_SLCD_CM_14SEGS_8_SETTING 8
+#endif
+
+// <o> Segments 9 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_9_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_9_SETTING
+#define CONF_SLCD_CM_14SEGS_9_SETTING 9
+#endif
+
+// <o> Segments 10 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_10_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_10_SETTING
+#define CONF_SLCD_CM_14SEGS_10_SETTING 10
+#endif
+
+// <o> Segments 11 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_11_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_11_SETTING
+#define CONF_SLCD_CM_14SEGS_11_SETTING 11
+#endif
+
+// <o> Segments 12 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_12_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_12_SETTING
+#define CONF_SLCD_CM_14SEGS_12_SETTING 12
+#endif
+
+// <o> Segments 13 Setting
+//   <i> Segment index for the character mapping area
+//   <i> Index 0 is the Character mapping beinging COMn/SEGn, Index 1 is COMn/SEGn + 1
+// <id> slcd_arch_cm_14segs_13_mapping_setting
+// <0=>0
+// <1=>1
+// <2=>2
+// <3=>3
+// <4=>4
+// <5=>5
+// <6=>6
+// <7=>7
+// <8=>8
+// <9=>9
+// <10=>10
+// <11=>11
+// <12=>12
+// <13=>13
+// <14=>14
+// <15=>15
+// <16=>16
+// <17=>17
+// <18=>18
+// <19=>19
+// <20=>20
+// <21=>21
+// <22=>22
+// <23=>23
+#ifndef CONF_SLCD_CM_14SEGS_13_SETTING
+#define CONF_SLCD_CM_14SEGS_13_SETTING 13
+#endif
+
+// </e>
+
+// <e> Character 0 Mapping Setting
+// <id> slcd_arch_char0_setting
+#ifndef CONF_SLCD_CHAR0_ENABLE_SETTING
+#define CONF_SLCD_CHAR0_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character0 COM begin index
+// <id> slcd_arch_char0_com_idx
+#ifndef CONF_SLCD_CHAR0_COM_IDX
+#define CONF_SLCD_CHAR0_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character0 Segment begin index
+// <id> slcd_arch_char0_seg_idx
+#ifndef CONF_SLCD_CHAR0_SEG_IDX
+#define CONF_SLCD_CHAR0_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character0 mapping
+// <id> slcd_arch_char0_seg_num
+#ifndef CONF_SLCD_CHAR0_SEG_NUM
+#define CONF_SLCD_CHAR0_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character0
+//   <id> slcd_arch_char0_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR0_MAPPING_TABLE
+#define CONF_SLCD_CHAR0_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 1 Mapping Setting
+// <id> slcd_arch_char1_setting
+#ifndef CONF_SLCD_CHAR1_ENABLE_SETTING
+#define CONF_SLCD_CHAR1_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character1 COM begin index
+// <id> slcd_arch_char1_com_idx
+#ifndef CONF_SLCD_CHAR1_COM_IDX
+#define CONF_SLCD_CHAR1_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character1 Segment begin index
+// <id> slcd_arch_char1_seg_idx
+#ifndef CONF_SLCD_CHAR1_SEG_IDX
+#define CONF_SLCD_CHAR1_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character1 mapping
+// <id> slcd_arch_char1_seg_num
+#ifndef CONF_SLCD_CHAR1_SEG_NUM
+#define CONF_SLCD_CHAR1_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character1
+//   <id> slcd_arch_char1_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR1_MAPPING_TABLE
+#define CONF_SLCD_CHAR1_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 2 Mapping Setting
+// <id> slcd_arch_char2_setting
+#ifndef CONF_SLCD_CHAR2_ENABLE_SETTING
+#define CONF_SLCD_CHAR2_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character2 COM begin index
+// <id> slcd_arch_char2_com_idx
+#ifndef CONF_SLCD_CHAR2_COM_IDX
+#define CONF_SLCD_CHAR2_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character2 Segment begin index
+// <id> slcd_arch_char2_seg_idx
+#ifndef CONF_SLCD_CHAR2_SEG_IDX
+#define CONF_SLCD_CHAR2_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character2 mapping
+// <id> slcd_arch_char2_seg_num
+#ifndef CONF_SLCD_CHAR2_SEG_NUM
+#define CONF_SLCD_CHAR2_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character2
+//   <id> slcd_arch_char2_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR2_MAPPING_TABLE
+#define CONF_SLCD_CHAR2_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 3 Mapping Setting
+// <id> slcd_arch_char3_setting
+#ifndef CONF_SLCD_CHAR3_ENABLE_SETTING
+#define CONF_SLCD_CHAR3_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character3 COM begin index
+// <id> slcd_arch_char3_com_idx
+#ifndef CONF_SLCD_CHAR3_COM_IDX
+#define CONF_SLCD_CHAR3_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character3 Segment begin index
+// <id> slcd_arch_char3_seg_idx
+#ifndef CONF_SLCD_CHAR3_SEG_IDX
+#define CONF_SLCD_CHAR3_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character3 mapping
+// <id> slcd_arch_char3_seg_num
+#ifndef CONF_SLCD_CHAR3_SEG_NUM
+#define CONF_SLCD_CHAR3_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character3
+//   <id> slcd_arch_char3_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR3_MAPPING_TABLE
+#define CONF_SLCD_CHAR3_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 4 Mapping Setting
+// <id> slcd_arch_char4_setting
+#ifndef CONF_SLCD_CHAR4_ENABLE_SETTING
+#define CONF_SLCD_CHAR4_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character4 COM begin index
+// <id> slcd_arch_char4_com_idx
+#ifndef CONF_SLCD_CHAR4_COM_IDX
+#define CONF_SLCD_CHAR4_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character4 Segment begin index
+// <id> slcd_arch_char4_seg_idx
+#ifndef CONF_SLCD_CHAR4_SEG_IDX
+#define CONF_SLCD_CHAR4_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character4 mapping
+// <id> slcd_arch_char4_seg_num
+#ifndef CONF_SLCD_CHAR4_SEG_NUM
+#define CONF_SLCD_CHAR4_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character4
+//   <id> slcd_arch_char4_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR4_MAPPING_TABLE
+#define CONF_SLCD_CHAR4_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 5 Mapping Setting
+// <id> slcd_arch_char5_setting
+#ifndef CONF_SLCD_CHAR5_ENABLE_SETTING
+#define CONF_SLCD_CHAR5_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character5 COM begin index
+// <id> slcd_arch_char5_com_idx
+#ifndef CONF_SLCD_CHAR5_COM_IDX
+#define CONF_SLCD_CHAR5_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character5 Segment begin index
+// <id> slcd_arch_char5_seg_idx
+#ifndef CONF_SLCD_CHAR5_SEG_IDX
+#define CONF_SLCD_CHAR5_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character5 mapping
+// <id> slcd_arch_char5_seg_num
+#ifndef CONF_SLCD_CHAR5_SEG_NUM
+#define CONF_SLCD_CHAR5_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character5
+//   <id> slcd_arch_char5_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR5_MAPPING_TABLE
+#define CONF_SLCD_CHAR5_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 6 Mapping Setting
+// <id> slcd_arch_char6_setting
+#ifndef CONF_SLCD_CHAR6_ENABLE_SETTING
+#define CONF_SLCD_CHAR6_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character6 COM begin index
+// <id> slcd_arch_char6_com_idx
+#ifndef CONF_SLCD_CHAR6_COM_IDX
+#define CONF_SLCD_CHAR6_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character6 Segment begin index
+// <id> slcd_arch_char6_seg_idx
+#ifndef CONF_SLCD_CHAR6_SEG_IDX
+#define CONF_SLCD_CHAR6_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character6 mapping
+// <id> slcd_arch_char6_seg_num
+#ifndef CONF_SLCD_CHAR6_SEG_NUM
+#define CONF_SLCD_CHAR6_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character6
+//   <id> slcd_arch_char6_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR6_MAPPING_TABLE
+#define CONF_SLCD_CHAR6_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 7 Mapping Setting
+// <id> slcd_arch_char7_setting
+#ifndef CONF_SLCD_CHAR7_ENABLE_SETTING
+#define CONF_SLCD_CHAR7_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character7 COM begin index
+// <id> slcd_arch_char7_com_idx
+#ifndef CONF_SLCD_CHAR7_COM_IDX
+#define CONF_SLCD_CHAR7_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character7 Segment begin index
+// <id> slcd_arch_char7_seg_idx
+#ifndef CONF_SLCD_CHAR7_SEG_IDX
+#define CONF_SLCD_CHAR7_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character7 mapping
+// <id> slcd_arch_char7_seg_num
+#ifndef CONF_SLCD_CHAR7_SEG_NUM
+#define CONF_SLCD_CHAR7_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character7
+//   <id> slcd_arch_char7_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR7_MAPPING_TABLE
+#define CONF_SLCD_CHAR7_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 8 Mapping Setting
+// <id> slcd_arch_char8_setting
+#ifndef CONF_SLCD_CHAR8_ENABLE_SETTING
+#define CONF_SLCD_CHAR8_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character8 COM begin index
+// <id> slcd_arch_char8_com_idx
+#ifndef CONF_SLCD_CHAR8_COM_IDX
+#define CONF_SLCD_CHAR8_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character8 Segment begin index
+// <id> slcd_arch_char8_seg_idx
+#ifndef CONF_SLCD_CHAR8_SEG_IDX
+#define CONF_SLCD_CHAR8_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character8 mapping
+// <id> slcd_arch_char8_seg_num
+#ifndef CONF_SLCD_CHAR8_SEG_NUM
+#define CONF_SLCD_CHAR8_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character8
+//   <id> slcd_arch_char8_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR8_MAPPING_TABLE
+#define CONF_SLCD_CHAR8_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 9 Mapping Setting
+// <id> slcd_arch_char9_setting
+#ifndef CONF_SLCD_CHAR9_ENABLE_SETTING
+#define CONF_SLCD_CHAR9_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character9 COM begin index
+// <id> slcd_arch_char9_com_idx
+#ifndef CONF_SLCD_CHAR9_COM_IDX
+#define CONF_SLCD_CHAR9_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character9 Segment begin index
+// <id> slcd_arch_char9_seg_idx
+#ifndef CONF_SLCD_CHAR9_SEG_IDX
+#define CONF_SLCD_CHAR9_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character9 mapping
+// <id> slcd_arch_char9_seg_num
+#ifndef CONF_SLCD_CHAR9_SEG_NUM
+#define CONF_SLCD_CHAR9_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character9
+//   <id> slcd_arch_char9_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR9_MAPPING_TABLE
+#define CONF_SLCD_CHAR9_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 10 Mapping Setting
+// <id> slcd_arch_char10_setting
+#ifndef CONF_SLCD_CHAR10_ENABLE_SETTING
+#define CONF_SLCD_CHAR10_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character10 COM begin index
+// <id> slcd_arch_char10_com_idx
+#ifndef CONF_SLCD_CHAR10_COM_IDX
+#define CONF_SLCD_CHAR10_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character10 Segment begin index
+// <id> slcd_arch_char10_seg_idx
+#ifndef CONF_SLCD_CHAR10_SEG_IDX
+#define CONF_SLCD_CHAR10_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character10 mapping
+// <id> slcd_arch_char10_seg_num
+#ifndef CONF_SLCD_CHAR10_SEG_NUM
+#define CONF_SLCD_CHAR10_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character10
+//   <id> slcd_arch_char10_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR10_MAPPING_TABLE
+#define CONF_SLCD_CHAR10_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 11 Mapping Setting
+// <id> slcd_arch_char11_setting
+#ifndef CONF_SLCD_CHAR11_ENABLE_SETTING
+#define CONF_SLCD_CHAR11_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character11 COM begin index
+// <id> slcd_arch_char11_com_idx
+#ifndef CONF_SLCD_CHAR11_COM_IDX
+#define CONF_SLCD_CHAR11_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character11 Segment begin index
+// <id> slcd_arch_char11_seg_idx
+#ifndef CONF_SLCD_CHAR11_SEG_IDX
+#define CONF_SLCD_CHAR11_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character11 mapping
+// <id> slcd_arch_char11_seg_num
+#ifndef CONF_SLCD_CHAR11_SEG_NUM
+#define CONF_SLCD_CHAR11_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character11
+//   <id> slcd_arch_char11_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR11_MAPPING_TABLE
+#define CONF_SLCD_CHAR11_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 12 Mapping Setting
+// <id> slcd_arch_char12_setting
+#ifndef CONF_SLCD_CHAR12_ENABLE_SETTING
+#define CONF_SLCD_CHAR12_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character12 COM begin index
+// <id> slcd_arch_char12_com_idx
+#ifndef CONF_SLCD_CHAR12_COM_IDX
+#define CONF_SLCD_CHAR12_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character12 Segment begin index
+// <id> slcd_arch_char12_seg_idx
+#ifndef CONF_SLCD_CHAR12_SEG_IDX
+#define CONF_SLCD_CHAR12_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character12 mapping
+// <id> slcd_arch_char12_seg_num
+#ifndef CONF_SLCD_CHAR12_SEG_NUM
+#define CONF_SLCD_CHAR12_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character12
+//   <id> slcd_arch_char12_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR12_MAPPING_TABLE
+#define CONF_SLCD_CHAR12_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 13 Mapping Setting
+// <id> slcd_arch_char13_setting
+#ifndef CONF_SLCD_CHAR13_ENABLE_SETTING
+#define CONF_SLCD_CHAR13_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character13 COM begin index
+// <id> slcd_arch_char13_com_idx
+#ifndef CONF_SLCD_CHAR13_COM_IDX
+#define CONF_SLCD_CHAR13_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character13 Segment begin index
+// <id> slcd_arch_char13_seg_idx
+#ifndef CONF_SLCD_CHAR13_SEG_IDX
+#define CONF_SLCD_CHAR13_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character13 mapping
+// <id> slcd_arch_char13_seg_num
+#ifndef CONF_SLCD_CHAR13_SEG_NUM
+#define CONF_SLCD_CHAR13_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character13
+//   <id> slcd_arch_char13_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR13_MAPPING_TABLE
+#define CONF_SLCD_CHAR13_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 14 Mapping Setting
+// <id> slcd_arch_char14_setting
+#ifndef CONF_SLCD_CHAR14_ENABLE_SETTING
+#define CONF_SLCD_CHAR14_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character14 COM begin index
+// <id> slcd_arch_char14_com_idx
+#ifndef CONF_SLCD_CHAR14_COM_IDX
+#define CONF_SLCD_CHAR14_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character14 Segment begin index
+// <id> slcd_arch_char14_seg_idx
+#ifndef CONF_SLCD_CHAR14_SEG_IDX
+#define CONF_SLCD_CHAR14_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character14 mapping
+// <id> slcd_arch_char14_seg_num
+#ifndef CONF_SLCD_CHAR14_SEG_NUM
+#define CONF_SLCD_CHAR14_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character14
+//   <id> slcd_arch_char14_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR14_MAPPING_TABLE
+#define CONF_SLCD_CHAR14_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 15 Mapping Setting
+// <id> slcd_arch_char15_setting
+#ifndef CONF_SLCD_CHAR15_ENABLE_SETTING
+#define CONF_SLCD_CHAR15_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character15 COM begin index
+// <id> slcd_arch_char15_com_idx
+#ifndef CONF_SLCD_CHAR15_COM_IDX
+#define CONF_SLCD_CHAR15_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character15 Segment begin index
+// <id> slcd_arch_char15_seg_idx
+#ifndef CONF_SLCD_CHAR15_SEG_IDX
+#define CONF_SLCD_CHAR15_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character15 mapping
+// <id> slcd_arch_char15_seg_num
+#ifndef CONF_SLCD_CHAR15_SEG_NUM
+#define CONF_SLCD_CHAR15_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character15
+//   <id> slcd_arch_char15_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR15_MAPPING_TABLE
+#define CONF_SLCD_CHAR15_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 16 Mapping Setting
+// <id> slcd_arch_char16_setting
+#ifndef CONF_SLCD_CHAR16_ENABLE_SETTING
+#define CONF_SLCD_CHAR16_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character16 COM begin index
+// <id> slcd_arch_char16_com_idx
+#ifndef CONF_SLCD_CHAR16_COM_IDX
+#define CONF_SLCD_CHAR16_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character16 Segment begin index
+// <id> slcd_arch_char16_seg_idx
+#ifndef CONF_SLCD_CHAR16_SEG_IDX
+#define CONF_SLCD_CHAR16_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character16 mapping
+// <id> slcd_arch_char16_seg_num
+#ifndef CONF_SLCD_CHAR16_SEG_NUM
+#define CONF_SLCD_CHAR16_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character16
+//   <id> slcd_arch_char16_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR16_MAPPING_TABLE
+#define CONF_SLCD_CHAR16_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 17 Mapping Setting
+// <id> slcd_arch_char17_setting
+#ifndef CONF_SLCD_CHAR17_ENABLE_SETTING
+#define CONF_SLCD_CHAR17_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character17 COM begin index
+// <id> slcd_arch_char17_com_idx
+#ifndef CONF_SLCD_CHAR17_COM_IDX
+#define CONF_SLCD_CHAR17_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character17 Segment begin index
+// <id> slcd_arch_char17_seg_idx
+#ifndef CONF_SLCD_CHAR17_SEG_IDX
+#define CONF_SLCD_CHAR17_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character17 mapping
+// <id> slcd_arch_char17_seg_num
+#ifndef CONF_SLCD_CHAR17_SEG_NUM
+#define CONF_SLCD_CHAR17_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character17
+//   <id> slcd_arch_char17_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR17_MAPPING_TABLE
+#define CONF_SLCD_CHAR17_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 18 Mapping Setting
+// <id> slcd_arch_char18_setting
+#ifndef CONF_SLCD_CHAR18_ENABLE_SETTING
+#define CONF_SLCD_CHAR18_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character18 COM begin index
+// <id> slcd_arch_char18_com_idx
+#ifndef CONF_SLCD_CHAR18_COM_IDX
+#define CONF_SLCD_CHAR18_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character18 Segment begin index
+// <id> slcd_arch_char18_seg_idx
+#ifndef CONF_SLCD_CHAR18_SEG_IDX
+#define CONF_SLCD_CHAR18_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character18 mapping
+// <id> slcd_arch_char18_seg_num
+#ifndef CONF_SLCD_CHAR18_SEG_NUM
+#define CONF_SLCD_CHAR18_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character18
+//   <id> slcd_arch_char18_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR18_MAPPING_TABLE
+#define CONF_SLCD_CHAR18_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 19 Mapping Setting
+// <id> slcd_arch_char19_setting
+#ifndef CONF_SLCD_CHAR19_ENABLE_SETTING
+#define CONF_SLCD_CHAR19_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character19 COM begin index
+// <id> slcd_arch_char19_com_idx
+#ifndef CONF_SLCD_CHAR19_COM_IDX
+#define CONF_SLCD_CHAR19_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character19 Segment begin index
+// <id> slcd_arch_char19_seg_idx
+#ifndef CONF_SLCD_CHAR19_SEG_IDX
+#define CONF_SLCD_CHAR19_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character19 mapping
+// <id> slcd_arch_char19_seg_num
+#ifndef CONF_SLCD_CHAR19_SEG_NUM
+#define CONF_SLCD_CHAR19_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character19
+//   <id> slcd_arch_char19_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR19_MAPPING_TABLE
+#define CONF_SLCD_CHAR19_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 20 Mapping Setting
+// <id> slcd_arch_char20_setting
+#ifndef CONF_SLCD_CHAR20_ENABLE_SETTING
+#define CONF_SLCD_CHAR20_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character20 COM begin index
+// <id> slcd_arch_char20_com_idx
+#ifndef CONF_SLCD_CHAR20_COM_IDX
+#define CONF_SLCD_CHAR20_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character20 Segment begin index
+// <id> slcd_arch_char20_seg_idx
+#ifndef CONF_SLCD_CHAR20_SEG_IDX
+#define CONF_SLCD_CHAR20_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character20 mapping
+// <id> slcd_arch_char20_seg_num
+#ifndef CONF_SLCD_CHAR20_SEG_NUM
+#define CONF_SLCD_CHAR20_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character20
+//   <id> slcd_arch_char20_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR20_MAPPING_TABLE
+#define CONF_SLCD_CHAR20_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 21 Mapping Setting
+// <id> slcd_arch_char21_setting
+#ifndef CONF_SLCD_CHAR21_ENABLE_SETTING
+#define CONF_SLCD_CHAR21_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character21 COM begin index
+// <id> slcd_arch_char21_com_idx
+#ifndef CONF_SLCD_CHAR21_COM_IDX
+#define CONF_SLCD_CHAR21_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character21 Segment begin index
+// <id> slcd_arch_char21_seg_idx
+#ifndef CONF_SLCD_CHAR21_SEG_IDX
+#define CONF_SLCD_CHAR21_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character21 mapping
+// <id> slcd_arch_char21_seg_num
+#ifndef CONF_SLCD_CHAR21_SEG_NUM
+#define CONF_SLCD_CHAR21_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character21
+//   <id> slcd_arch_char21_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR21_MAPPING_TABLE
+#define CONF_SLCD_CHAR21_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 22 Mapping Setting
+// <id> slcd_arch_char22_setting
+#ifndef CONF_SLCD_CHAR22_ENABLE_SETTING
+#define CONF_SLCD_CHAR22_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character22 COM begin index
+// <id> slcd_arch_char22_com_idx
+#ifndef CONF_SLCD_CHAR22_COM_IDX
+#define CONF_SLCD_CHAR22_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character22 Segment begin index
+// <id> slcd_arch_char22_seg_idx
+#ifndef CONF_SLCD_CHAR22_SEG_IDX
+#define CONF_SLCD_CHAR22_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character22 mapping
+// <id> slcd_arch_char22_seg_num
+#ifndef CONF_SLCD_CHAR22_SEG_NUM
+#define CONF_SLCD_CHAR22_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character22
+//   <id> slcd_arch_char22_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR22_MAPPING_TABLE
+#define CONF_SLCD_CHAR22_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 23 Mapping Setting
+// <id> slcd_arch_char23_setting
+#ifndef CONF_SLCD_CHAR23_ENABLE_SETTING
+#define CONF_SLCD_CHAR23_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character23 COM begin index
+// <id> slcd_arch_char23_com_idx
+#ifndef CONF_SLCD_CHAR23_COM_IDX
+#define CONF_SLCD_CHAR23_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character23 Segment begin index
+// <id> slcd_arch_char23_seg_idx
+#ifndef CONF_SLCD_CHAR23_SEG_IDX
+#define CONF_SLCD_CHAR23_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character23 mapping
+// <id> slcd_arch_char23_seg_num
+#ifndef CONF_SLCD_CHAR23_SEG_NUM
+#define CONF_SLCD_CHAR23_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character23
+//   <id> slcd_arch_char23_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR23_MAPPING_TABLE
+#define CONF_SLCD_CHAR23_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 24 Mapping Setting
+// <id> slcd_arch_char24_setting
+#ifndef CONF_SLCD_CHAR24_ENABLE_SETTING
+#define CONF_SLCD_CHAR24_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character24 COM begin index
+// <id> slcd_arch_char24_com_idx
+#ifndef CONF_SLCD_CHAR24_COM_IDX
+#define CONF_SLCD_CHAR24_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character24 Segment begin index
+// <id> slcd_arch_char24_seg_idx
+#ifndef CONF_SLCD_CHAR24_SEG_IDX
+#define CONF_SLCD_CHAR24_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character24 mapping
+// <id> slcd_arch_char24_seg_num
+#ifndef CONF_SLCD_CHAR24_SEG_NUM
+#define CONF_SLCD_CHAR24_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character24
+//   <id> slcd_arch_char24_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR24_MAPPING_TABLE
+#define CONF_SLCD_CHAR24_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 25 Mapping Setting
+// <id> slcd_arch_char25_setting
+#ifndef CONF_SLCD_CHAR25_ENABLE_SETTING
+#define CONF_SLCD_CHAR25_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character25 COM begin index
+// <id> slcd_arch_char25_com_idx
+#ifndef CONF_SLCD_CHAR25_COM_IDX
+#define CONF_SLCD_CHAR25_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character25 Segment begin index
+// <id> slcd_arch_char25_seg_idx
+#ifndef CONF_SLCD_CHAR25_SEG_IDX
+#define CONF_SLCD_CHAR25_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character25 mapping
+// <id> slcd_arch_char25_seg_num
+#ifndef CONF_SLCD_CHAR25_SEG_NUM
+#define CONF_SLCD_CHAR25_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character25
+//   <id> slcd_arch_char25_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR25_MAPPING_TABLE
+#define CONF_SLCD_CHAR25_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 26 Mapping Setting
+// <id> slcd_arch_char26_setting
+#ifndef CONF_SLCD_CHAR26_ENABLE_SETTING
+#define CONF_SLCD_CHAR26_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character26 COM begin index
+// <id> slcd_arch_char26_com_idx
+#ifndef CONF_SLCD_CHAR26_COM_IDX
+#define CONF_SLCD_CHAR26_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character26 Segment begin index
+// <id> slcd_arch_char26_seg_idx
+#ifndef CONF_SLCD_CHAR26_SEG_IDX
+#define CONF_SLCD_CHAR26_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character26 mapping
+// <id> slcd_arch_char26_seg_num
+#ifndef CONF_SLCD_CHAR26_SEG_NUM
+#define CONF_SLCD_CHAR26_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character26
+//   <id> slcd_arch_char26_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR26_MAPPING_TABLE
+#define CONF_SLCD_CHAR26_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 27 Mapping Setting
+// <id> slcd_arch_char27_setting
+#ifndef CONF_SLCD_CHAR27_ENABLE_SETTING
+#define CONF_SLCD_CHAR27_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character27 COM begin index
+// <id> slcd_arch_char27_com_idx
+#ifndef CONF_SLCD_CHAR27_COM_IDX
+#define CONF_SLCD_CHAR27_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character27 Segment begin index
+// <id> slcd_arch_char27_seg_idx
+#ifndef CONF_SLCD_CHAR27_SEG_IDX
+#define CONF_SLCD_CHAR27_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character27 mapping
+// <id> slcd_arch_char27_seg_num
+#ifndef CONF_SLCD_CHAR27_SEG_NUM
+#define CONF_SLCD_CHAR27_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character27
+//   <id> slcd_arch_char27_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR27_MAPPING_TABLE
+#define CONF_SLCD_CHAR27_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 28 Mapping Setting
+// <id> slcd_arch_char28_setting
+#ifndef CONF_SLCD_CHAR28_ENABLE_SETTING
+#define CONF_SLCD_CHAR28_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character28 COM begin index
+// <id> slcd_arch_char28_com_idx
+#ifndef CONF_SLCD_CHAR28_COM_IDX
+#define CONF_SLCD_CHAR28_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character28 Segment begin index
+// <id> slcd_arch_char28_seg_idx
+#ifndef CONF_SLCD_CHAR28_SEG_IDX
+#define CONF_SLCD_CHAR28_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character28 mapping
+// <id> slcd_arch_char28_seg_num
+#ifndef CONF_SLCD_CHAR28_SEG_NUM
+#define CONF_SLCD_CHAR28_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character28
+//   <id> slcd_arch_char28_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR28_MAPPING_TABLE
+#define CONF_SLCD_CHAR28_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 29 Mapping Setting
+// <id> slcd_arch_char29_setting
+#ifndef CONF_SLCD_CHAR29_ENABLE_SETTING
+#define CONF_SLCD_CHAR29_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character29 COM begin index
+// <id> slcd_arch_char29_com_idx
+#ifndef CONF_SLCD_CHAR29_COM_IDX
+#define CONF_SLCD_CHAR29_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character29 Segment begin index
+// <id> slcd_arch_char29_seg_idx
+#ifndef CONF_SLCD_CHAR29_SEG_IDX
+#define CONF_SLCD_CHAR29_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character29 mapping
+// <id> slcd_arch_char29_seg_num
+#ifndef CONF_SLCD_CHAR29_SEG_NUM
+#define CONF_SLCD_CHAR29_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character29
+//   <id> slcd_arch_char29_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR29_MAPPING_TABLE
+#define CONF_SLCD_CHAR29_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 30 Mapping Setting
+// <id> slcd_arch_char30_setting
+#ifndef CONF_SLCD_CHAR30_ENABLE_SETTING
+#define CONF_SLCD_CHAR30_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character30 COM begin index
+// <id> slcd_arch_char30_com_idx
+#ifndef CONF_SLCD_CHAR30_COM_IDX
+#define CONF_SLCD_CHAR30_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character30 Segment begin index
+// <id> slcd_arch_char30_seg_idx
+#ifndef CONF_SLCD_CHAR30_SEG_IDX
+#define CONF_SLCD_CHAR30_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character30 mapping
+// <id> slcd_arch_char30_seg_num
+#ifndef CONF_SLCD_CHAR30_SEG_NUM
+#define CONF_SLCD_CHAR30_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character30
+//   <id> slcd_arch_char30_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR30_MAPPING_TABLE
+#define CONF_SLCD_CHAR30_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 31 Mapping Setting
+// <id> slcd_arch_char31_setting
+#ifndef CONF_SLCD_CHAR31_ENABLE_SETTING
+#define CONF_SLCD_CHAR31_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character31 COM begin index
+// <id> slcd_arch_char31_com_idx
+#ifndef CONF_SLCD_CHAR31_COM_IDX
+#define CONF_SLCD_CHAR31_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character31 Segment begin index
+// <id> slcd_arch_char31_seg_idx
+#ifndef CONF_SLCD_CHAR31_SEG_IDX
+#define CONF_SLCD_CHAR31_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character31 mapping
+// <id> slcd_arch_char31_seg_num
+#ifndef CONF_SLCD_CHAR31_SEG_NUM
+#define CONF_SLCD_CHAR31_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character31
+//   <id> slcd_arch_char31_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR31_MAPPING_TABLE
+#define CONF_SLCD_CHAR31_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 32 Mapping Setting
+// <id> slcd_arch_char32_setting
+#ifndef CONF_SLCD_CHAR32_ENABLE_SETTING
+#define CONF_SLCD_CHAR32_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character32 COM begin index
+// <id> slcd_arch_char32_com_idx
+#ifndef CONF_SLCD_CHAR32_COM_IDX
+#define CONF_SLCD_CHAR32_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character32 Segment begin index
+// <id> slcd_arch_char32_seg_idx
+#ifndef CONF_SLCD_CHAR32_SEG_IDX
+#define CONF_SLCD_CHAR32_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character32 mapping
+// <id> slcd_arch_char32_seg_num
+#ifndef CONF_SLCD_CHAR32_SEG_NUM
+#define CONF_SLCD_CHAR32_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character32
+//   <id> slcd_arch_char32_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR32_MAPPING_TABLE
+#define CONF_SLCD_CHAR32_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 33 Mapping Setting
+// <id> slcd_arch_char33_setting
+#ifndef CONF_SLCD_CHAR33_ENABLE_SETTING
+#define CONF_SLCD_CHAR33_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character33 COM begin index
+// <id> slcd_arch_char33_com_idx
+#ifndef CONF_SLCD_CHAR33_COM_IDX
+#define CONF_SLCD_CHAR33_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character33 Segment begin index
+// <id> slcd_arch_char33_seg_idx
+#ifndef CONF_SLCD_CHAR33_SEG_IDX
+#define CONF_SLCD_CHAR33_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character33 mapping
+// <id> slcd_arch_char33_seg_num
+#ifndef CONF_SLCD_CHAR33_SEG_NUM
+#define CONF_SLCD_CHAR33_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character33
+//   <id> slcd_arch_char33_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR33_MAPPING_TABLE
+#define CONF_SLCD_CHAR33_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 34 Mapping Setting
+// <id> slcd_arch_char34_setting
+#ifndef CONF_SLCD_CHAR34_ENABLE_SETTING
+#define CONF_SLCD_CHAR34_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character34 COM begin index
+// <id> slcd_arch_char34_com_idx
+#ifndef CONF_SLCD_CHAR34_COM_IDX
+#define CONF_SLCD_CHAR34_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character34 Segment begin index
+// <id> slcd_arch_char34_seg_idx
+#ifndef CONF_SLCD_CHAR34_SEG_IDX
+#define CONF_SLCD_CHAR34_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character34 mapping
+// <id> slcd_arch_char34_seg_num
+#ifndef CONF_SLCD_CHAR34_SEG_NUM
+#define CONF_SLCD_CHAR34_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character34
+//   <id> slcd_arch_char34_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR34_MAPPING_TABLE
+#define CONF_SLCD_CHAR34_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 35 Mapping Setting
+// <id> slcd_arch_char35_setting
+#ifndef CONF_SLCD_CHAR35_ENABLE_SETTING
+#define CONF_SLCD_CHAR35_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character35 COM begin index
+// <id> slcd_arch_char35_com_idx
+#ifndef CONF_SLCD_CHAR35_COM_IDX
+#define CONF_SLCD_CHAR35_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character35 Segment begin index
+// <id> slcd_arch_char35_seg_idx
+#ifndef CONF_SLCD_CHAR35_SEG_IDX
+#define CONF_SLCD_CHAR35_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character35 mapping
+// <id> slcd_arch_char35_seg_num
+#ifndef CONF_SLCD_CHAR35_SEG_NUM
+#define CONF_SLCD_CHAR35_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character35
+//   <id> slcd_arch_char35_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR35_MAPPING_TABLE
+#define CONF_SLCD_CHAR35_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 36 Mapping Setting
+// <id> slcd_arch_char36_setting
+#ifndef CONF_SLCD_CHAR36_ENABLE_SETTING
+#define CONF_SLCD_CHAR36_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character36 COM begin index
+// <id> slcd_arch_char36_com_idx
+#ifndef CONF_SLCD_CHAR36_COM_IDX
+#define CONF_SLCD_CHAR36_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character36 Segment begin index
+// <id> slcd_arch_char36_seg_idx
+#ifndef CONF_SLCD_CHAR36_SEG_IDX
+#define CONF_SLCD_CHAR36_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character36 mapping
+// <id> slcd_arch_char36_seg_num
+#ifndef CONF_SLCD_CHAR36_SEG_NUM
+#define CONF_SLCD_CHAR36_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character36
+//   <id> slcd_arch_char36_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR36_MAPPING_TABLE
+#define CONF_SLCD_CHAR36_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 37 Mapping Setting
+// <id> slcd_arch_char37_setting
+#ifndef CONF_SLCD_CHAR37_ENABLE_SETTING
+#define CONF_SLCD_CHAR37_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character37 COM begin index
+// <id> slcd_arch_char37_com_idx
+#ifndef CONF_SLCD_CHAR37_COM_IDX
+#define CONF_SLCD_CHAR37_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character37 Segment begin index
+// <id> slcd_arch_char37_seg_idx
+#ifndef CONF_SLCD_CHAR37_SEG_IDX
+#define CONF_SLCD_CHAR37_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character37 mapping
+// <id> slcd_arch_char37_seg_num
+#ifndef CONF_SLCD_CHAR37_SEG_NUM
+#define CONF_SLCD_CHAR37_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character37
+//   <id> slcd_arch_char37_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR37_MAPPING_TABLE
+#define CONF_SLCD_CHAR37_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 38 Mapping Setting
+// <id> slcd_arch_char38_setting
+#ifndef CONF_SLCD_CHAR38_ENABLE_SETTING
+#define CONF_SLCD_CHAR38_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character38 COM begin index
+// <id> slcd_arch_char38_com_idx
+#ifndef CONF_SLCD_CHAR38_COM_IDX
+#define CONF_SLCD_CHAR38_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character38 Segment begin index
+// <id> slcd_arch_char38_seg_idx
+#ifndef CONF_SLCD_CHAR38_SEG_IDX
+#define CONF_SLCD_CHAR38_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character38 mapping
+// <id> slcd_arch_char38_seg_num
+#ifndef CONF_SLCD_CHAR38_SEG_NUM
+#define CONF_SLCD_CHAR38_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character38
+//   <id> slcd_arch_char38_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR38_MAPPING_TABLE
+#define CONF_SLCD_CHAR38_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 39 Mapping Setting
+// <id> slcd_arch_char39_setting
+#ifndef CONF_SLCD_CHAR39_ENABLE_SETTING
+#define CONF_SLCD_CHAR39_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character39 COM begin index
+// <id> slcd_arch_char39_com_idx
+#ifndef CONF_SLCD_CHAR39_COM_IDX
+#define CONF_SLCD_CHAR39_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character39 Segment begin index
+// <id> slcd_arch_char39_seg_idx
+#ifndef CONF_SLCD_CHAR39_SEG_IDX
+#define CONF_SLCD_CHAR39_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character39 mapping
+// <id> slcd_arch_char39_seg_num
+#ifndef CONF_SLCD_CHAR39_SEG_NUM
+#define CONF_SLCD_CHAR39_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character39
+//   <id> slcd_arch_char39_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR39_MAPPING_TABLE
+#define CONF_SLCD_CHAR39_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 40 Mapping Setting
+// <id> slcd_arch_char40_setting
+#ifndef CONF_SLCD_CHAR40_ENABLE_SETTING
+#define CONF_SLCD_CHAR40_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character40 COM begin index
+// <id> slcd_arch_char40_com_idx
+#ifndef CONF_SLCD_CHAR40_COM_IDX
+#define CONF_SLCD_CHAR40_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character40 Segment begin index
+// <id> slcd_arch_char40_seg_idx
+#ifndef CONF_SLCD_CHAR40_SEG_IDX
+#define CONF_SLCD_CHAR40_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character40 mapping
+// <id> slcd_arch_char40_seg_num
+#ifndef CONF_SLCD_CHAR40_SEG_NUM
+#define CONF_SLCD_CHAR40_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character40
+//   <id> slcd_arch_char40_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR40_MAPPING_TABLE
+#define CONF_SLCD_CHAR40_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 41 Mapping Setting
+// <id> slcd_arch_char41_setting
+#ifndef CONF_SLCD_CHAR41_ENABLE_SETTING
+#define CONF_SLCD_CHAR41_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character41 COM begin index
+// <id> slcd_arch_char41_com_idx
+#ifndef CONF_SLCD_CHAR41_COM_IDX
+#define CONF_SLCD_CHAR41_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character41 Segment begin index
+// <id> slcd_arch_char41_seg_idx
+#ifndef CONF_SLCD_CHAR41_SEG_IDX
+#define CONF_SLCD_CHAR41_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character41 mapping
+// <id> slcd_arch_char41_seg_num
+#ifndef CONF_SLCD_CHAR41_SEG_NUM
+#define CONF_SLCD_CHAR41_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character41
+//   <id> slcd_arch_char41_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR41_MAPPING_TABLE
+#define CONF_SLCD_CHAR41_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 42 Mapping Setting
+// <id> slcd_arch_char42_setting
+#ifndef CONF_SLCD_CHAR42_ENABLE_SETTING
+#define CONF_SLCD_CHAR42_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character42 COM begin index
+// <id> slcd_arch_char42_com_idx
+#ifndef CONF_SLCD_CHAR42_COM_IDX
+#define CONF_SLCD_CHAR42_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character42 Segment begin index
+// <id> slcd_arch_char42_seg_idx
+#ifndef CONF_SLCD_CHAR42_SEG_IDX
+#define CONF_SLCD_CHAR42_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character42 mapping
+// <id> slcd_arch_char42_seg_num
+#ifndef CONF_SLCD_CHAR42_SEG_NUM
+#define CONF_SLCD_CHAR42_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character42
+//   <id> slcd_arch_char42_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR42_MAPPING_TABLE
+#define CONF_SLCD_CHAR42_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+// <e> Character 43 Mapping Setting
+// <id> slcd_arch_char43_setting
+#ifndef CONF_SLCD_CHAR43_ENABLE_SETTING
+#define CONF_SLCD_CHAR43_ENABLE_SETTING 0
+#endif
+
+// <o> COM index <0-7>
+// <i> Character43 COM begin index
+// <id> slcd_arch_char43_com_idx
+#ifndef CONF_SLCD_CHAR43_COM_IDX
+#define CONF_SLCD_CHAR43_COM_IDX 0
+#endif
+
+// <o> Segment index <0-44>
+// <i> Character43 Segment begin index
+// <id> slcd_arch_char43_seg_idx
+#ifndef CONF_SLCD_CHAR43_SEG_IDX
+#define CONF_SLCD_CHAR43_SEG_IDX 1
+#endif
+
+// <o> Number of Segment <1-24>
+// <i> Number of Segment used for Character43 mapping
+// <id> slcd_arch_char43_seg_num
+#ifndef CONF_SLCD_CHAR43_SEG_NUM
+#define CONF_SLCD_CHAR43_SEG_NUM 1
+#endif
+
+// <o> Mapping Table
+//   <i> Select the char mapping table for Character43
+//   <id> slcd_arch_char43_mapping_table
+//   <7=>7 Segments Mapping Table
+//   <14=>14 Segments Mapping Table
+#ifndef CONF_SLCD_CHAR43_MAPPING_TABLE
+#define CONF_SLCD_CHAR43_MAPPING_SIZE 7
+#endif
+
+// </e>
+
+/**
+ * character lookup table
+ */
+#define SLCD_CHAR_SETTING_TABLE                                                                                        \
+	{                                                                                                                  \
+		{CONF_SLCD_CHAR0_COM_IDX, CONF_SLCD_CHAR0_SEG_IDX, CONF_SLCD_CHAR0_SEG_NUM - 1, CONF_SLCD_CHAR0_MAPPING_SIZE}, \
+		    {CONF_SLCD_CHAR1_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR1_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR1_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR1_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR2_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR2_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR2_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR2_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR3_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR3_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR3_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR3_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR4_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR4_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR4_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR4_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR5_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR5_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR5_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR5_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR6_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR6_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR6_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR6_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR7_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR7_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR7_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR7_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR8_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR8_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR8_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR8_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR9_COM_IDX,                                                                                  \
+		     CONF_SLCD_CHAR9_SEG_IDX,                                                                                  \
+		     CONF_SLCD_CHAR9_SEG_NUM - 1,                                                                              \
+		     CONF_SLCD_CHAR9_MAPPING_SIZE},                                                                            \
+		    {CONF_SLCD_CHAR10_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR10_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR10_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR10_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR11_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR11_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR11_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR11_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR12_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR12_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR12_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR12_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR13_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR13_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR13_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR13_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR14_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR14_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR14_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR14_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR15_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR15_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR15_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR15_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR16_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR16_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR16_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR16_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR17_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR17_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR17_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR17_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR18_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR18_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR18_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR18_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR19_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR19_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR19_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR19_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR20_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR20_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR20_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR20_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR21_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR21_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR21_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR21_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR22_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR22_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR22_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR22_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR23_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR23_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR23_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR23_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR24_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR24_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR24_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR24_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR25_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR25_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR25_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR25_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR26_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR26_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR26_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR26_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR27_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR27_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR27_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR27_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR28_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR28_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR28_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR28_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR29_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR29_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR29_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR29_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR30_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR30_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR30_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR30_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR31_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR31_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR31_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR31_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR32_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR32_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR32_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR32_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR33_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR33_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR33_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR33_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR34_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR34_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR34_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR34_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR35_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR35_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR35_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR35_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR36_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR36_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR36_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR36_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR37_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR37_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR37_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR37_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR38_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR38_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR38_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR38_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR39_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR39_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR39_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR39_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR40_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR40_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR40_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR40_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR41_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR41_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR41_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR41_MAPPING_SIZE},                                                                           \
+		    {CONF_SLCD_CHAR42_COM_IDX,                                                                                 \
+		     CONF_SLCD_CHAR42_SEG_IDX,                                                                                 \
+		     CONF_SLCD_CHAR42_SEG_NUM - 1,                                                                             \
+		     CONF_SLCD_CHAR42_MAPPING_SIZE},                                                                           \
+		{                                                                                                              \
+			CONF_SLCD_CHAR43_COM_IDX, CONF_SLCD_CHAR43_SEG_IDX, CONF_SLCD_CHAR43_SEG_NUM - 1,                          \
+			    CONF_SLCD_CHAR43_MAPPING_SIZE                                                                          \
+		}                                                                                                              \
+	}
+
+#define CONF_SLCD_LPENL                                                                                                \
+	((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 4 | (uint32_t)1 << 5   \
+	 | (uint32_t)1 << 6 | (uint32_t)1 << 7 | (uint32_t)1 << 11 | (uint32_t)1 << 12 | (uint32_t)1 << 13                 \
+	 | (uint32_t)1 << 14 | (uint32_t)1 << 21 | (uint32_t)1 << 22 | (uint32_t)1 << 23 | (uint32_t)1 << 24               \
+	 | (uint32_t)1 << 25 | (uint32_t)1 << 28 | (uint32_t)1 << 29 | (uint32_t)1 << 30 | (uint32_t)1 << 31 | 0)
+
+#define CONF_SLCD_LPENH                                                                                                \
+	((uint32_t)1 << 0 | (uint32_t)1 << 1 | (uint32_t)1 << 2 | (uint32_t)1 << 3 | (uint32_t)1 << 10 | (uint32_t)1 << 11 \
+	 | 0) // </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SLCD_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_systick_config.h b/Smol Watch Project/My Project/Config/hpl_systick_config.h
new file mode 100644
index 0000000..a7f2f36
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_systick_config.h	
@@ -0,0 +1,18 @@
+/* Auto-generated config file hpl_systick_config.h */
+#ifndef HPL_SYSTICK_CONFIG_H
+#define HPL_SYSTICK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Advanced settings
+// <q> SysTick exception request
+// <i> Indicates whether the generation of SysTick exception is enabled or not
+// <id> systick_arch_tickint
+#ifndef CONF_SYSTICK_TICKINT
+#define CONF_SYSTICK_TICKINT 0
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SYSTICK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_tc_config.h b/Smol Watch Project/My Project/Config/hpl_tc_config.h
new file mode 100644
index 0000000..61e5b1b
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_tc_config.h	
@@ -0,0 +1,206 @@
+/* Auto-generated config file hpl_tc_config.h */
+#ifndef HPL_TC_CONFIG_H
+#define HPL_TC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_TC3_ENABLE
+#define CONF_TC3_ENABLE 1
+#endif
+
+// <h> Basic settings
+// <o> Prescaler
+// <0=> No division
+// <1=> Divide by 2
+// <2=> Divide by 4
+// <3=> Divide by 8
+// <4=> Divide by 16
+// <5=> Divide by 64
+// <6=> Divide by 256
+// <7=> Divide by 1024
+// <i> This defines the prescaler value
+// <id> tc_prescaler
+#ifndef CONF_TC3_PRESCALER
+#define CONF_TC3_PRESCALER 0
+#endif
+// </h>
+
+// <h> PWM Waveform Output settings
+// <o> Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// <i> The unit of this value is us.
+// <id> tc_arch_wave_per_val
+#ifndef CONF_TC3_WAVE_PER_VAL
+#define CONF_TC3_WAVE_PER_VAL 0x3e8
+#endif
+
+// <o> Waveform Duty Value (0.1%) <0x00-0x03E8>
+// <i> The unit of this value is 1/1000.
+// <id> tc_arch_wave_duty_val
+#ifndef CONF_TC3_WAVE_DUTY_VAL
+#define CONF_TC3_WAVE_DUTY_VAL 0x1f4
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC3_CC0                                                                                                   \
+	((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+
+#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1))
+#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000)
+#endif
+
+// </h>
+
+// <h> Advanced settings
+// <y> Mode
+// <TC_CTRLA_MODE_COUNT16_Val"> Counter in 16-bit mode
+// <TC_CTRLA_MODE_COUNT32_Val"> Counter in 32-bit mode
+// <i> These bits mode
+// <id> tc_mode
+#ifndef CONF_TC3_MODE
+#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val
+#endif
+
+/*  Unused in 16/32 bit PWM mode */
+#ifndef CONF_TC3_PER
+#define CONF_TC3_PER 0x32
+#endif
+
+// <y> Prescaler and Counter Synchronization Selection
+// <TC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock.
+// <id> tc_arch_presync
+#ifndef CONF_TC3_PRESCSYNC
+#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the will continue running in standby sleep mode or not
+// <id> tc_arch_runstdby
+#ifndef CONF_TC3_RUNSTDBY
+#define CONF_TC3_RUNSTDBY 0
+#endif
+
+// <q> On-Demand
+// <i> Indicates whether the TC3's on-demand mode is on or not
+// <id> tc_arch_ondemand
+#ifndef CONF_TC3_ONDEMAND
+#define CONF_TC3_ONDEMAND 0
+#endif
+
+// <o> Auto Lock
+// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event
+// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event
+// <id> tc_arch_alock
+#ifndef CONF_TC3_ALOCK
+#define CONF_TC3_ALOCK 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_CAPTEN0 0
+//#define CONF_TC3_CAPTEN1 0
+//#define CONF_TC3_COPEN0  0
+//#define CONF_TC3_COPEN1  0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_DIR     0
+//#define CONF_TC3_ONESHOT 0
+//#define CONF_TC3_LUPD    0
+
+// <q> Debug Running Mode
+// <i> Indicates whether the Debug Running Mode is enabled or not
+// <id> tc_arch_dbgrun
+#ifndef CONF_TC3_DBGRUN
+#define CONF_TC3_DBGRUN 0
+#endif
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TC3_EVENT_CONTROL_ENABLE
+#define CONF_TC3_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Output Event On Match or Capture on Channel 0
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo0
+#ifndef CONF_TC3_MCEO0
+#define CONF_TC3_MCEO0 0
+#endif
+
+// <q> Output Event On Match or Capture on Channel 1
+// <i> Enable output of event on timer tick
+// <id> tc_arch_mceo1
+#ifndef CONF_TC3_MCEO1
+#define CONF_TC3_MCEO1 0
+#endif
+
+// <q> Output Event On Timer Tick
+// <i> Enable output of event on timer tick
+// <id> tc_arch_ovfeo
+#ifndef CONF_TC3_OVFEO
+#define CONF_TC3_OVFEO 0
+#endif
+
+// <q> Event Input
+// <i> Enable asynchronous input events
+// <id> tc_arch_tcei
+#ifndef CONF_TC3_TCEI
+#define CONF_TC3_TCEI 0
+#endif
+
+// <q> Inverted Event Input
+// <i> Invert the asynchronous input events
+// <id> tc_arch_tcinv
+#ifndef CONF_TC3_TCINV
+#define CONF_TC3_TCINV 0
+#endif
+
+// <o> Event action
+// <0=> Event action disabled
+// <1=> Start, restart or re-trigger TC on event
+// <2=> Count on event
+// <3=> Start on event
+// <4=> Time stamp capture
+// <5=> Period captured in CC0, pulse width in CC1
+// <6=> Period captured in CC1, pulse width in CC0
+// <7=> Pulse width capture
+// <i> Event which will be performed on an event
+//<id> tc_arch_evact
+#ifndef CONF_TC3_EVACT
+#define CONF_TC3_EVACT 0
+#endif
+// </e>
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_WAVEGEN   TC_CTRLA_WAVEGEN_MFRQ_Val
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_INVEN0 0
+//#define CONF_TC3_INVEN1 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_PERBUF 0
+
+/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */
+//#define CONF_TC3_CCBUF0 0
+//#define CONF_TC3_CCBUF1 0
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/hpl_tcc_config.h b/Smol Watch Project/My Project/Config/hpl_tcc_config.h
new file mode 100644
index 0000000..a8d45f5
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/hpl_tcc_config.h	
@@ -0,0 +1,547 @@
+/* Auto-generated config file hpl_tcc_config.h */
+#ifndef HPL_TCC_CONFIG_H
+#define HPL_TCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+#ifndef CONF_TCC0_ENABLE
+#define CONF_TCC0_ENABLE 1
+#endif
+
+#ifndef CONF_TCC0_PWM_ENABLE
+#define CONF_TCC0_PWM_ENABLE 1
+#endif
+
+// <h> Basic settings
+// <y> TCC0 Prescaler
+// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
+// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
+// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
+// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
+// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
+// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
+// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
+// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
+// <i> This defines the TCC0 prescaler value
+// <id> tcc_prescaler
+#ifndef CONF_TCC0_PRESCALER
+#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
+#endif
+
+// <hidden>
+//<o> TCC0 Period Value <0x000000-0xFFFFFF>
+// <id> tcc_per
+#ifndef CONF_TCC0_PER
+#define CONF_TCC0_PER 0x2710
+#endif
+// </hidden>
+
+// </h>
+
+// <h> PWM Waveform Output settings
+// <o> TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
+// <i> The unit of this value is us.
+// <id> tcc_arch_wave_per_val
+#ifndef CONF_TCC0_WAVE_PER_VAL
+#define CONF_TCC0_WAVE_PER_VAL 0x3e8
+#endif
+
+// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
+// <i> The unit of this value is 1/1000.
+// <id> tcc_arch_wave_duty_val
+#ifndef CONF_TCC0_WAVE_DUTY_VAL
+#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
+#endif
+
+// <o> TCC0 Waveform Channel Select <0x00-0x03>
+// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
+// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
+// <id> tcc_arch_sel_ch
+#ifndef CONF_TCC0_SEL_CH
+#define CONF_TCC0_SEL_CH 0x1
+#endif
+
+/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
+#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG                                                                                              \
+	((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+
+#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
+#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
+#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
+#endif
+// </h>
+
+// <h> Advanced settings
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
+// <q> Run in standby
+// <i> Indicates whether the TCC0 will continue running in standby sleep mode or not
+// <id> tcc_arch_runstdby
+#ifndef CONF_TCC0_RUNSTDBY
+#define CONF_TCC0_RUNSTDBY 0
+#endif
+
+// <y> TCC0 Prescaler and Counter Synchronization Selection
+// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
+// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
+// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
+// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
+// <id> tcc_arch_prescsync
+#ifndef CONF_TCC0_PRESCSYNC
+#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
+#endif
+
+// <y> TCC0 Waveform Generation Selection
+// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
+// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
+// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
+// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
+// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
+// <id> tcc_arch_wavegen
+#ifndef CONF_TCC0_WAVEGEN
+#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
+#endif
+// <q> TCC0 Auto Lock
+// <i> Indicates whether the TCC0 Auto Lock is enabled or not
+// <id> tcc_arch_alock
+#ifndef CONF_TCC0_ALOCK
+#define CONF_TCC0_ALOCK 0
+#endif
+
+// <q> TCC0 Capture Channel 0 Enable
+// <i> Indicates whether the TCC0 Capture Channel 0 is enabled or not
+// <id> tcc_arch_cpten0
+#ifndef CONF_TCC0_CPTEN0
+#define CONF_TCC0_CPTEN0 0
+#endif
+
+// <q> TCC0 Capture Channel 1 Enable
+// <i> Indicates whether the TCC0 Capture Channel 1 is enabled or not
+// <id> tcc_arch_cpten1
+#ifndef CONF_TCC0_CPTEN1
+#define CONF_TCC0_CPTEN1 0
+#endif
+
+// <q> TCC0 Capture Channel 2 Enable
+// <i> Indicates whether the TCC0 Capture Channel 2 is enabled or not
+// <id> tcc_arch_cpten2
+#ifndef CONF_TCC0_CPTEN2
+#define CONF_TCC0_CPTEN2 0
+#endif
+
+// <q> TCC0 Capture Channel 3 Enable
+// <i> Indicates whether the TCC0 Capture Channel 3 is enabled or not
+// <id> tcc_arch_cpten3
+#ifndef CONF_TCC0_CPTEN3
+#define CONF_TCC0_CPTEN3 0
+#endif
+
+// <hidden>
+// <q> TCC0 Capture Channel 4 Enable
+// <i> Indicates whether the TCC0 Capture Channel 4 is enabled or not
+// <id> tcc_arch_cpten4
+#ifndef CONF_TCC0_CPTEN4
+#define CONF_TCC0_CPTEN4 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC0 Capture Channel 5 Enable
+// <i> Indicates whether the TCC0 Capture Channel 5 is enabled or not
+// <id> tcc_arch_cpten5
+#ifndef CONF_TCC0_CPTEN5
+#define CONF_TCC0_CPTEN5 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC0 Capture Channel 6 Enable
+// <i> Indicates whether the TCC0 Capture Channel 6 is enabled or not
+// <id> tcc_arch_cpten6
+#ifndef CONF_TCC0_CPTEN6
+#define CONF_TCC0_CPTEN6 0
+#endif
+// </hidden>
+// <hidden>
+// <q> TCC0 Capture Channel 7 Enable
+// <i> Indicates whether the TCC0 Capture Channel 7 is enabled or not
+// <id> tcc_arch_cpten7
+#ifndef CONF_TCC0_CPTEN7
+#define CONF_TCC0_CPTEN7 0
+#endif
+// </hidden>
+
+// <q> TCC0 Lock update
+// <i> Indicates whether the TCC0 Lock update is enabled or not
+// <id> tcc_arch_lupd
+#ifndef CONF_TCC0_LUPD
+#define CONF_TCC0_LUPD 1
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_DIR     0
+//#define CONF_TCC0_ONESHOT 0
+
+/* Commented intentionally. No fault control for timers. */
+/*#define CONF_TCC0_FAULT_A_SRC       TCC_FCTRLA_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_A_KEEP        0
+#define CONF_TCC0_FAULT_A_QUAL        0
+#define CONF_TCC0_FAULT_A_BLANK       TCC_FCTRLA_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_A_RESTART     0
+#define CONF_TCC0_FAULT_A_HALT        TCC_FCTRLA_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_A_CHSEL       TCC_FCTRLA_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_A_CAPTURE     TCC_FCTRLA_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_A_BLANKVAL    0
+#define CONF_TCC0_FAULT_A_FILTERVAL   0
+
+#define CONF_TCC0_FAULT_B_SRC         TCC_FCTRLB_SRC_DISABLE_Val
+#define CONF_TCC0_FAULT_B_KEEP        0
+#define CONF_TCC0_FAULT_B_QUAL        0
+#define CONF_TCC0_FAULT_B_BLANK       TCC_FCTRLB_BLANK_DISABLE_Val
+#define CONF_TCC0_FAULT_B_RESTART     0
+#define CONF_TCC0_FAULT_B_HALT        TCC_FCTRLB_HALT_DISABLE_Val
+#define CONF_TCC0_FAULT_B_CHSEL       TCC_FCTRLB_CHSEL_CC0_Val
+#define CONF_TCC0_FAULT_B_CAPTURE     TCC_FCTRLB_CAPTURE_DISABLE_Val
+#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
+#define CONF_TCC0_FAULT_B_BLANKVAL    0
+#define CONF_TCC0_FAULT_B_FILTERVAL   0*/
+
+/* Commented intentionally. No dead-time control for timers. */
+/*#define CONF_TCC0_OTMX   0
+#define CONF_TCC0_DTIEN0 0
+#define CONF_TCC0_DTIEN1 0
+#define CONF_TCC0_DTIEN2 0
+#define CONF_TCC0_DTIEN3 0
+#define CONF_TCC0_DTHS   0*/
+
+/* Commented intentionally. No driver control for timers. */
+/*#define CONF_TCC0_NRE0       0
+#define CONF_TCC0_NRE1       0
+#define CONF_TCC0_NRE2       0
+#define CONF_TCC0_NRE3       0
+#define CONF_TCC0_NRE4       0
+#define CONF_TCC0_NRE5       0
+#define CONF_TCC0_NRE6       0
+#define CONF_TCC0_NRE7       0
+#define CONF_TCC0_NVR0       0
+#define CONF_TCC0_NVR1       0
+#define CONF_TCC0_NVR2       0
+#define CONF_TCC0_NVR3       0
+#define CONF_TCC0_NVR4       0
+#define CONF_TCC0_NVR5       0
+#define CONF_TCC0_NVR6       0
+#define CONF_TCC0_NVR7       0
+#define CONF_TCC0_INVEN0     0
+#define CONF_TCC0_INVEN1     0
+#define CONF_TCC0_INVEN2     0
+#define CONF_TCC0_INVEN3     0
+#define CONF_TCC0_INVEN4     0
+#define CONF_TCC0_INVEN5     0
+#define CONF_TCC0_INVEN6     0
+#define CONF_TCC0_INVEN7     0
+#define CONF_TCC0_FILTERVAL0 0
+#define CONF_TCC0_FILTERVAL1 0*/
+
+// <q> TCC0 Debug Running Mode
+// <i> Indicates whether the TCC0 Debug Running Mode is enabled or not
+// <id> tcc_arch_dbgrun
+#ifndef CONF_TCC0_DBGRUN
+#define CONF_TCC0_DBGRUN 0
+#endif
+
+/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
+ * May be used by other abstractions based on TC. */
+//#define CONF_TCC0_FDDBD  0
+
+// <e> Event control
+// <id> timer_event_control
+#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
+#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
+#endif
+
+// <q> Match or Capture Channel 0 Event Output
+// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
+// <id> tcc_arch_mceo0
+#ifndef CONF_TCC0_MCEO0
+#define CONF_TCC0_MCEO0 0
+#endif
+
+// <q> Match or Capture Channel 0 Event Input
+// <i> This bit indicates whether match/capture 0 incoming event is enabled
+// <id> tcc_arch_mcei0
+#ifndef CONF_TCC0_MCEI0
+#define CONF_TCC0_MCEI0 0
+#endif
+// <q> Match or Capture Channel 1 Event Output
+// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
+// <id> tcc_arch_mceo1
+#ifndef CONF_TCC0_MCEO1
+#define CONF_TCC0_MCEO1 0
+#endif
+
+// <q> Match or Capture Channel 1 Event Input
+// <i> This bit indicates whether match/capture 1 incoming event is enabled
+// <id> tcc_arch_mcei1
+#ifndef CONF_TCC0_MCEI1
+#define CONF_TCC0_MCEI1 0
+#endif
+// <q> Match or Capture Channel 2 Event Output
+// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
+// <id> tcc_arch_mceo2
+#ifndef CONF_TCC0_MCEO2
+#define CONF_TCC0_MCEO2 0
+#endif
+
+// <q> Match or Capture Channel 2 Event Input
+// <i> This bit indicates whether match/capture 2 incoming event is enabled
+// <id> tcc_arch_mcei2
+#ifndef CONF_TCC0_MCEI2
+#define CONF_TCC0_MCEI2 0
+#endif
+// <q> Match or Capture Channel 3 Event Output
+// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
+// <id> tcc_arch_mceo3
+#ifndef CONF_TCC0_MCEO3
+#define CONF_TCC0_MCEO3 0
+#endif
+
+// <q> Match or Capture Channel 3 Event Input
+// <i> This bit indicates whether match/capture 3 incoming event is enabled
+// <id> tcc_arch_mcei3
+#ifndef CONF_TCC0_MCEI3
+#define CONF_TCC0_MCEI3 0
+#endif
+
+// <q> Timer/Counter Event Input 0
+// <i> This bit is used to enable input event 0 to the TCC
+// <id> tcc_arch_tcei0
+#ifndef CONF_TCC0_TCEI0
+#define CONF_TCC0_TCEI0 0
+#endif
+
+// <q> Timer/Counter Event Input 0 Invert
+// <i> This bit inverts the event 0 input
+// <id> tcc_arch_tceinv0
+#ifndef CONF_TCC0_TCINV0
+#define CONF_TCC0_TCINV0 0
+#endif
+// <q> Timer/Counter Event Input 1
+// <i> This bit is used to enable input event 1 to the TCC
+// <id> tcc_arch_tcei1
+#ifndef CONF_TCC0_TCEI1
+#define CONF_TCC0_TCEI1 0
+#endif
+
+// <q> Timer/Counter Event Input 1 Invert
+// <i> This bit inverts the event 1 input
+// <id> tcc_arch_tceinv1
+#ifndef CONF_TCC0_TCINV1
+#define CONF_TCC0_TCINV1 0
+#endif
+
+// <q> Timer/Counter Event Output
+// <i> This bit is used to enable the counter cycle event.
+//<id> tcc_arch_cnteo
+#ifndef CONF_TCC0_CNTEO
+#define CONF_TCC0_CNTEO 0
+#endif
+
+// <q> Re-trigger Event Output
+// <i> This bit is used to enable the counter re-trigger event.
+//<id> tcc_arch_trgeo
+#ifndef CONF_TCC0_TRGEO
+#define CONF_TCC0_TRGEO 0
+#endif
+
+// <q> Overflow/Underflow Event Output
+// <i> This bit is used to enable enable event on overflow/underflow.
+//<id> tcc_arch_ovfeo
+#ifndef CONF_TCC0_OVFEO
+#define CONF_TCC0_OVFEO 0
+#endif
+
+// <o> Timer/Counter Interrupt and Event Output Selection
+// <0=> An interrupt/event is generated when a new counter cycle starts
+// <1=> An interrupt/event is generated when a counter cycle ends
+// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
+// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
+// <i> These bits define on which part of the counter cycle the counter event output is generated
+// <id> tcc_arch_cntsel
+#ifndef CONF_TCC0_CNTSEL
+#define CONF_TCC0_CNTSEL 0
+#endif
+
+// <o> Timer/Counter Event Input 0 Action
+// <0=>Event action disabled
+// <1=>Start restart or re-trigger on event
+// <2=>Count on event
+// <3=>Start on event
+// <4=>Increment on event
+// <5=>Count on active state of asynchronous event
+// <6=>Capture overflow times (Max value)
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact0
+#ifndef CONF_TCC0_EVACT0
+#define CONF_TCC0_EVACT0 0
+#endif
+
+// <o> Timer/Counter Event Input 1 Action
+// <0=>Event action disabled
+// <1=>Re-trigger counter on event
+// <2=>Direction control
+// <3=>Stop counter on event
+// <4=>Decrement counter on event
+// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
+// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
+// <7=>Non-recoverable fault
+// <i> These bits define the action the TCC performs on TCE0 event input 0
+// <id> tcc_arch_evact1
+#ifndef CONF_TCC0_EVACT1
+#define CONF_TCC0_EVACT1 0
+#endif
+// </e>
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PGE0 0
+#define CONF_TCC0_PGE1 0
+#define CONF_TCC0_PGE2 0
+#define CONF_TCC0_PGE3 0
+#define CONF_TCC0_PGE4 0
+#define CONF_TCC0_PGE5 0
+#define CONF_TCC0_PGE6 0
+#define CONF_TCC0_PGE7 0
+#define CONF_TCC0_PGV0 0
+#define CONF_TCC0_PGV1 0
+#define CONF_TCC0_PGV2 0
+#define CONF_TCC0_PGV3 0
+#define CONF_TCC0_PGV4 0
+#define CONF_TCC0_PGV5 0
+#define CONF_TCC0_PGV6 0
+#define CONF_TCC0_PGV7 0*/
+
+/* Commented intentionally. No pattern waveform control for timers. */
+/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
+#define CONF_TCC0_RAMP    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPEREN 0
+#define CONF_TCC0_CICCEN0 0
+#define CONF_TCC0_CICCEN1 0
+#define CONF_TCC0_CICCEN2 0
+#define CONF_TCC0_CICCEN3 0
+#define CONF_TCC0_POL0    0
+#define CONF_TCC0_POL1    0
+#define CONF_TCC0_POL2    0
+#define CONF_TCC0_POL3    0
+#define CONF_TCC0_POL4    0
+#define CONF_TCC0_POL5    0
+#define CONF_TCC0_POL6    0
+#define CONF_TCC0_POL7    0
+#define CONF_TCC0_SWAP0   0
+#define CONF_TCC0_SWAP1   0
+#define CONF_TCC0_SWAP2   0
+#define CONF_TCC0_SWAP3   0*/
+
+//<o> TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc0
+#ifndef CONF_TCC0_CC0
+#define CONF_TCC0_CC0 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc1
+#ifndef CONF_TCC0_CC1
+#define CONF_TCC0_CC1 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc2
+#ifndef CONF_TCC0_CC2
+#define CONF_TCC0_CC2 0x0
+#endif
+
+//<o> TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
+// <id> tcc_arch_cc3
+#ifndef CONF_TCC0_CC3
+#define CONF_TCC0_CC3 0x0
+#endif
+
+/* Commented intentionally. No pattern control for timers. */
+/*#define CONF_TCC0_PATTB_PGEB0 0
+#define CONF_TCC0_PATTB_PGEB1 0
+#define CONF_TCC0_PATTB_PGEB2 0
+#define CONF_TCC0_PATTB_PGEB3 0
+#define CONF_TCC0_PATTB_PGEB4 0
+#define CONF_TCC0_PATTB_PGEB5 0
+#define CONF_TCC0_PATTB_PGEB6 0
+#define CONF_TCC0_PATTB_PGEB7 0
+#define CONF_TCC0_PATTB_PGVB0 0
+#define CONF_TCC0_PATTB_PGVB1 0
+#define CONF_TCC0_PATTB_PGVB2 0
+#define CONF_TCC0_PATTB_PGVB3 0
+#define CONF_TCC0_PATTB_PGVB4 0
+#define CONF_TCC0_PATTB_PGVB5 0
+#define CONF_TCC0_PATTB_PGVB6 0
+#define CONF_TCC0_PATTB_PGVB7 0*/
+
+/* Commented intentionally. No waveform control for timers. */
+/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
+#define CONF_TCC0_RAMPB    TCC_WAVE_RAMP_RAMP1_Val
+#define CONF_TCC0_CIPERENB 0
+#define CONF_TCC0_CICCEN0B 0
+#define CONF_TCC0_CICCEN1B 0
+#define CONF_TCC0_CICCEN2B 0
+#define CONF_TCC0_CICCEN3B 0
+#define CONF_TCC0_POL0B    0
+#define CONF_TCC0_POL1B    0
+#define CONF_TCC0_POL2B    0
+#define CONF_TCC0_POL3B    0
+#define CONF_TCC0_POL4B    0
+#define CONF_TCC0_POL5B    0
+#define CONF_TCC0_POL6B    0
+#define CONF_TCC0_POL7B    0
+#define CONF_TCC0_SWAP0B   0
+#define CONF_TCC0_SWAP1B   0
+#define CONF_TCC0_SWAP2B   0
+#define CONF_TCC0_SWAP3B   0*/
+
+/* Commented intentionally. No buffering for timers. */
+/*#define CONF_TCC0_PERB 0
+#define CONF_TCC0_CCB0 0
+#define CONF_TCC0_CCB1 0
+#define CONF_TCC0_CCB2 0
+#define CONF_TCC0_CCB3 0*/
+// </h>
+
+#define CONF_TCC0_CTRLA                                                                                                \
+	TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos)                          \
+	    | TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos)                        \
+	    | (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos)                      \
+	    | (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
+#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
+#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
+#define CONF_TCC0_EVCTRL                                                                                               \
+	TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos)                                    \
+	    | (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos)                        \
+	    | (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos)                        \
+	    | (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos)                        \
+	    | (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos)                        \
+	    | (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos)                        \
+	    | (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos)                        \
+	    | (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos)                    \
+	    | TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TCC_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/peripheral_clk_config.h b/Smol Watch Project/My Project/Config/peripheral_clk_config.h
new file mode 100644
index 0000000..9050e80
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/peripheral_clk_config.h	
@@ -0,0 +1,214 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC_SRC
+#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC_FREQUENCY
+ * \brief ADC's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC_FREQUENCY
+#define CONF_GCLK_ADC_FREQUENCY 4000000
+#endif
+
+// <y> EIC Clock Source
+// <id> eic_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for EIC.
+#ifndef CONF_GCLK_EIC_SRC
+#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_EIC_FREQUENCY
+ * \brief EIC's Clock frequency
+ */
+#ifndef CONF_GCLK_EIC_FREQUENCY
+#define CONF_GCLK_EIC_FREQUENCY 32768
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 4000000
+#endif
+
+// <y> RTC Clock Source
+// <id> rtc_clk_selection
+// <RTC_CLOCK_SOURCE"> RTC source
+// <i> Select the clock source for RTC.
+#ifndef CONF_GCLK_RTC_SRC
+#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_RTC_FREQUENCY
+ * \brief RTC's Clock frequency
+ */
+#ifndef CONF_GCLK_RTC_FREQUENCY
+#define CONF_GCLK_RTC_FREQUENCY 1024
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> TC Clock Source
+// <id> tc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for TC.
+#ifndef CONF_GCLK_TC3_SRC
+#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TC3_FREQUENCY
+ * \brief TC3's Clock frequency
+ */
+#ifndef CONF_GCLK_TC3_FREQUENCY
+#define CONF_GCLK_TC3_FREQUENCY 4000000
+#endif
+
+// <y> TCC Clock Source
+// <id> tcc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for TCC.
+#ifndef CONF_GCLK_TCC0_SRC
+#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_TCC0_FREQUENCY
+ * \brief TCC0's Clock frequency
+ */
+#ifndef CONF_GCLK_TCC0_FREQUENCY
+#define CONF_GCLK_TCC0_FREQUENCY 4000000
+#endif
+
+#include <hpl_osc32kctrl_config.h>
+
+// <y> SLCD Clock Source
+// <id> slcd_clk_selection
+// <SLCD_CLOCK_SOURCE"> SLCD source
+// <i> Select the clock source for SLCD.
+#ifndef CONF_GCLK_SLCD_SRC
+#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
+#endif
+
+/**
+ * \def CONF_GCLK_SLCD_FREQUENCY
+ * \brief SLCD's Clock frequency
+ */
+#ifndef CONF_GCLK_SLCD_FREQUENCY
+#define CONF_GCLK_SLCD_FREQUENCY 32768
+#endif
+
+#ifndef SLCD_FRAME_FREQUENCY
+#define SLCD_FRAME_FREQUENCY                                                                                           \
+	(CONF_GCLK_SLCD_FREQUENCY                                                                                          \
+	 / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1)                                                           \
+	    * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/Smol Watch Project/My Project/Config/sleep_manager_config.h b/Smol Watch Project/My Project/Config/sleep_manager_config.h
new file mode 100644
index 0000000..ae673ea
--- /dev/null
+++ b/Smol Watch Project/My Project/Config/sleep_manager_config.h	
@@ -0,0 +1,9 @@
+/* Auto-generated config file sleep_manager_config.h */
+#ifndef SLEEP_MANAGER_CONFIG_H
+#define SLEEP_MANAGER_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <<< end of configuration section >>>
+
+#endif // SLEEP_MANAGER_CONFIG_H
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d
new file mode 100644
index 0000000..6faec5e
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.d	
@@ -0,0 +1,239 @@
+Device_Startup/startup_saml22.d Device_Startup/startup_saml22.o: \
+ ../Device_Startup/startup_saml22.c \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
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+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
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+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
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+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
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+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o
new file mode 100644
index 0000000..3f44c5a
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/Device_Startup/startup_saml22.o differ
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d
new file mode 100644
index 0000000..32952d2
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.d	
@@ -0,0 +1,239 @@
+Device_Startup/system_saml22.d Device_Startup/system_saml22.o: \
+ ../Device_Startup/system_saml22.c \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
diff --git a/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o
new file mode 100644
index 0000000..b295d06
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/Device_Startup/system_saml22.o differ
diff --git a/Smol Watch Project/My Project/Debug/Makefile b/Smol Watch Project/My Project/Debug/Makefile
new file mode 100644
index 0000000..43608ce
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/Makefile	
@@ -0,0 +1,641 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS := 
+PROJ := 
+
+O_SRCS := 
+C_SRCS := 
+S_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+PREPROCESSING_SRCS := 
+OBJS := 
+OBJS_AS_ARGS := 
+C_DEPS := 
+C_DEPS_AS_ARGS := 
+EXECUTABLES := 
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS :=  \
+../Config/ \
+../Device_Startup/ \
+../documentation/ \
+../examples/ \
+../hal/ \
+../hal/documentation/ \
+../hal/include/ \
+../hal/src/ \
+../hal/utils/ \
+../hal/utils/include/ \
+../hal/utils/src/ \
+../hpl/ \
+../hpl/adc/ \
+../hpl/core/ \
+../hpl/dmac/ \
+../hpl/eic/ \
+../hpl/gclk/ \
+../hpl/mclk/ \
+../hpl/osc32kctrl/ \
+../hpl/oscctrl/ \
+../hpl/pm/ \
+../hpl/port/ \
+../hpl/rtc/ \
+../hpl/sercom/ \
+../hpl/slcd/ \
+../hpl/systick/ \
+../hpl/tcc/ \
+../hpl/tc/ \
+../hri/ \
+../sleep_manager/ \
+../watch-library
+
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS +=  \
+../atmel_start.c \
+../Device_Startup/startup_saml22.c \
+../Device_Startup/system_saml22.c \
+../driver_init.c \
+../examples/driver_examples.c \
+../hal/src/hal_adc_sync.c \
+../hal/src/hal_atomic.c \
+../hal/src/hal_calendar.c \
+../hal/src/hal_delay.c \
+../hal/src/hal_ext_irq.c \
+../hal/src/hal_gpio.c \
+../hal/src/hal_i2c_m_sync.c \
+../hal/src/hal_init.c \
+../hal/src/hal_io.c \
+../hal/src/hal_pwm.c \
+../hal/src/hal_slcd_sync.c \
+../hal/src/hal_sleep.c \
+../hal/utils/src/utils_assert.c \
+../hal/utils/src/utils_event.c \
+../hal/utils/src/utils_list.c \
+../hal/utils/src/utils_syscalls.c \
+../hpl/adc/hpl_adc.c \
+../hpl/core/hpl_core_m0plus_base.c \
+../hpl/core/hpl_init.c \
+../hpl/dmac/hpl_dmac.c \
+../hpl/eic/hpl_eic.c \
+../hpl/gclk/hpl_gclk.c \
+../hpl/mclk/hpl_mclk.c \
+../hpl/osc32kctrl/hpl_osc32kctrl.c \
+../hpl/oscctrl/hpl_oscctrl.c \
+../hpl/pm/hpl_pm.c \
+../hpl/rtc/hpl_rtc.c \
+../hpl/sercom/hpl_sercom.c \
+../hpl/slcd/hpl_slcd.c \
+../hpl/systick/hpl_systick.c \
+../hpl/tcc/hpl_tcc.c \
+../hpl/tc/hpl_tc.c \
+../main.c \
+../sleep_manager/sleep_manager.c \
+../sleep_manager_main.c \
+../watch-library/watch.c
+
+
+PREPROCESSING_SRCS += 
+
+
+ASM_SRCS += 
+
+
+OBJS +=  \
+atmel_start.o \
+Device_Startup/startup_saml22.o \
+Device_Startup/system_saml22.o \
+driver_init.o \
+examples/driver_examples.o \
+hal/src/hal_adc_sync.o \
+hal/src/hal_atomic.o \
+hal/src/hal_calendar.o \
+hal/src/hal_delay.o \
+hal/src/hal_ext_irq.o \
+hal/src/hal_gpio.o \
+hal/src/hal_i2c_m_sync.o \
+hal/src/hal_init.o \
+hal/src/hal_io.o \
+hal/src/hal_pwm.o \
+hal/src/hal_slcd_sync.o \
+hal/src/hal_sleep.o \
+hal/utils/src/utils_assert.o \
+hal/utils/src/utils_event.o \
+hal/utils/src/utils_list.o \
+hal/utils/src/utils_syscalls.o \
+hpl/adc/hpl_adc.o \
+hpl/core/hpl_core_m0plus_base.o \
+hpl/core/hpl_init.o \
+hpl/dmac/hpl_dmac.o \
+hpl/eic/hpl_eic.o \
+hpl/gclk/hpl_gclk.o \
+hpl/mclk/hpl_mclk.o \
+hpl/osc32kctrl/hpl_osc32kctrl.o \
+hpl/oscctrl/hpl_oscctrl.o \
+hpl/pm/hpl_pm.o \
+hpl/rtc/hpl_rtc.o \
+hpl/sercom/hpl_sercom.o \
+hpl/slcd/hpl_slcd.o \
+hpl/systick/hpl_systick.o \
+hpl/tcc/hpl_tcc.o \
+hpl/tc/hpl_tc.o \
+main.o \
+sleep_manager/sleep_manager.o \
+sleep_manager_main.o \
+watch-library/watch.o
+
+OBJS_AS_ARGS +=  \
+atmel_start.o \
+Device_Startup/startup_saml22.o \
+Device_Startup/system_saml22.o \
+driver_init.o \
+examples/driver_examples.o \
+hal/src/hal_adc_sync.o \
+hal/src/hal_atomic.o \
+hal/src/hal_calendar.o \
+hal/src/hal_delay.o \
+hal/src/hal_ext_irq.o \
+hal/src/hal_gpio.o \
+hal/src/hal_i2c_m_sync.o \
+hal/src/hal_init.o \
+hal/src/hal_io.o \
+hal/src/hal_pwm.o \
+hal/src/hal_slcd_sync.o \
+hal/src/hal_sleep.o \
+hal/utils/src/utils_assert.o \
+hal/utils/src/utils_event.o \
+hal/utils/src/utils_list.o \
+hal/utils/src/utils_syscalls.o \
+hpl/adc/hpl_adc.o \
+hpl/core/hpl_core_m0plus_base.o \
+hpl/core/hpl_init.o \
+hpl/dmac/hpl_dmac.o \
+hpl/eic/hpl_eic.o \
+hpl/gclk/hpl_gclk.o \
+hpl/mclk/hpl_mclk.o \
+hpl/osc32kctrl/hpl_osc32kctrl.o \
+hpl/oscctrl/hpl_oscctrl.o \
+hpl/pm/hpl_pm.o \
+hpl/rtc/hpl_rtc.o \
+hpl/sercom/hpl_sercom.o \
+hpl/slcd/hpl_slcd.o \
+hpl/systick/hpl_systick.o \
+hpl/tcc/hpl_tcc.o \
+hpl/tc/hpl_tc.o \
+main.o \
+sleep_manager/sleep_manager.o \
+sleep_manager_main.o \
+watch-library/watch.o
+
+C_DEPS +=  \
+atmel_start.d \
+Device_Startup/startup_saml22.d \
+Device_Startup/system_saml22.d \
+driver_init.d \
+examples/driver_examples.d \
+hal/src/hal_adc_sync.d \
+hal/src/hal_atomic.d \
+hal/src/hal_calendar.d \
+hal/src/hal_delay.d \
+hal/src/hal_ext_irq.d \
+hal/src/hal_gpio.d \
+hal/src/hal_i2c_m_sync.d \
+hal/src/hal_init.d \
+hal/src/hal_io.d \
+hal/src/hal_pwm.d \
+hal/src/hal_slcd_sync.d \
+hal/src/hal_sleep.d \
+hal/utils/src/utils_assert.d \
+hal/utils/src/utils_event.d \
+hal/utils/src/utils_list.d \
+hal/utils/src/utils_syscalls.d \
+hpl/adc/hpl_adc.d \
+hpl/core/hpl_core_m0plus_base.d \
+hpl/core/hpl_init.d \
+hpl/dmac/hpl_dmac.d \
+hpl/eic/hpl_eic.d \
+hpl/gclk/hpl_gclk.d \
+hpl/mclk/hpl_mclk.d \
+hpl/osc32kctrl/hpl_osc32kctrl.d \
+hpl/oscctrl/hpl_oscctrl.d \
+hpl/pm/hpl_pm.d \
+hpl/rtc/hpl_rtc.d \
+hpl/sercom/hpl_sercom.d \
+hpl/slcd/hpl_slcd.d \
+hpl/systick/hpl_systick.d \
+hpl/tcc/hpl_tcc.d \
+hpl/tc/hpl_tc.d \
+main.d \
+sleep_manager/sleep_manager.d \
+sleep_manager_main.d \
+watch-library/watch.d
+
+C_DEPS_AS_ARGS +=  \
+atmel_start.d \
+Device_Startup/startup_saml22.d \
+Device_Startup/system_saml22.d \
+driver_init.d \
+examples/driver_examples.d \
+hal/src/hal_adc_sync.d \
+hal/src/hal_atomic.d \
+hal/src/hal_calendar.d \
+hal/src/hal_delay.d \
+hal/src/hal_ext_irq.d \
+hal/src/hal_gpio.d \
+hal/src/hal_i2c_m_sync.d \
+hal/src/hal_init.d \
+hal/src/hal_io.d \
+hal/src/hal_pwm.d \
+hal/src/hal_slcd_sync.d \
+hal/src/hal_sleep.d \
+hal/utils/src/utils_assert.d \
+hal/utils/src/utils_event.d \
+hal/utils/src/utils_list.d \
+hal/utils/src/utils_syscalls.d \
+hpl/adc/hpl_adc.d \
+hpl/core/hpl_core_m0plus_base.d \
+hpl/core/hpl_init.d \
+hpl/dmac/hpl_dmac.d \
+hpl/eic/hpl_eic.d \
+hpl/gclk/hpl_gclk.d \
+hpl/mclk/hpl_mclk.d \
+hpl/osc32kctrl/hpl_osc32kctrl.d \
+hpl/oscctrl/hpl_oscctrl.d \
+hpl/pm/hpl_pm.d \
+hpl/rtc/hpl_rtc.d \
+hpl/sercom/hpl_sercom.d \
+hpl/slcd/hpl_slcd.d \
+hpl/systick/hpl_systick.d \
+hpl/tcc/hpl_tcc.d \
+hpl/tc/hpl_tc.d \
+main.d \
+sleep_manager/sleep_manager.d \
+sleep_manager_main.d \
+watch-library/watch.d
+
+OUTPUT_FILE_PATH +=My\ Project.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +="My Project.elf"
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+= 
+
+LINKER_SCRIPT_DEP+=  \
+../Device_Startup/saml22j18a_flash.ld \
+../Device_Startup/saml22j18a_sram.ld
+
+
+# AVR32/GNU C Compiler
+./atmel_start.o: .././atmel_start.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+Device_Startup/startup_saml22.o: ../Device_Startup/startup_saml22.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+Device_Startup/system_saml22.o: ../Device_Startup/system_saml22.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+./driver_init.o: .././driver_init.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+examples/driver_examples.o: ../examples/driver_examples.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_adc_sync.o: ../hal/src/hal_adc_sync.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_atomic.o: ../hal/src/hal_atomic.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_calendar.o: ../hal/src/hal_calendar.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_delay.o: ../hal/src/hal_delay.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_gpio.o: ../hal/src/hal_gpio.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_i2c_m_sync.o: ../hal/src/hal_i2c_m_sync.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_init.o: ../hal/src/hal_init.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_io.o: ../hal/src/hal_io.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_pwm.o: ../hal/src/hal_pwm.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_slcd_sync.o: ../hal/src/hal_slcd_sync.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/src/hal_sleep.o: ../hal/src/hal_sleep.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/utils/src/utils_assert.o: ../hal/utils/src/utils_assert.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/utils/src/utils_event.o: ../hal/utils/src/utils_event.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/utils/src/utils_list.o: ../hal/utils/src/utils_list.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hal/utils/src/utils_syscalls.o: ../hal/utils/src/utils_syscalls.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/adc/hpl_adc.o: ../hpl/adc/hpl_adc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/core/hpl_core_m0plus_base.o: ../hpl/core/hpl_core_m0plus_base.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/core/hpl_init.o: ../hpl/core/hpl_init.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/eic/hpl_eic.o: ../hpl/eic/hpl_eic.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/osc32kctrl/hpl_osc32kctrl.o: ../hpl/osc32kctrl/hpl_osc32kctrl.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/oscctrl/hpl_oscctrl.o: ../hpl/oscctrl/hpl_oscctrl.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/rtc/hpl_rtc.o: ../hpl/rtc/hpl_rtc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/sercom/hpl_sercom.o: ../hpl/sercom/hpl_sercom.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/slcd/hpl_slcd.o: ../hpl/slcd/hpl_slcd.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/systick/hpl_systick.o: ../hpl/systick/hpl_systick.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/tcc/hpl_tcc.o: ../hpl/tcc/hpl_tcc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+hpl/tc/hpl_tc.o: ../hpl/tc/hpl_tc.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+./main.o: .././main.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+sleep_manager/sleep_manager.o: ../sleep_manager/sleep_manager.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+./sleep_manager_main.o: .././sleep_manager_main.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+watch-library/watch.o: ../watch-library/watch.c
+	@echo Building file: $<
+	@echo Invoking: ARM/GNU C Compiler : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE)  -x c -mthumb -D__SAML22J18A__ -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"../sleep_manager" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include"  -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
+	@echo Finished building: $<
+	
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables 
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
+	@echo Building target: $@
+	@echo Invoking: ARM/GNU Linker : 6.3.1
+	$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="My Project.map" --specs=nano.specs -Wl,--start-group -lm  -Wl,--end-group -L"..\\Device_Startup"  -Wl,--gc-sections -mcpu=cortex-m0plus -Tsaml22j18a_flash.ld  
+	@echo Finished building target: $@
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "My Project.elf" "My Project.bin"
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature  "My Project.elf" "My Project.hex"
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "My Project.elf" "My Project.eep" || exit 0
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "My Project.elf" > "My Project.lss"
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature  "My Project.elf" "My Project.srec"
+	"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "My Project.elf"
+	
+	
+
+
+
+
+
+# Other Targets
+clean:
+	-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)  
+	-$(RM) $(C_DEPS_AS_ARGS)   
+	rm -rf "My Project.elf" "My Project.a" "My Project.hex" "My Project.bin" "My Project.lss" "My Project.eep" "My Project.map" "My Project.srec"
+	
\ No newline at end of file
diff --git a/Smol Watch Project/My Project/Debug/My Project.bin b/Smol Watch Project/My Project/Debug/My Project.bin
new file mode 100644
index 0000000..bbfb568
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/My Project.bin differ
diff --git a/Smol Watch Project/My Project/Debug/My Project.eep b/Smol Watch Project/My Project/Debug/My Project.eep
new file mode 100644
index 0000000..e69de29
diff --git a/Smol Watch Project/My Project/Debug/My Project.elf b/Smol Watch Project/My Project/Debug/My Project.elf
new file mode 100644
index 0000000..14870a6
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/My Project.elf differ
diff --git a/Smol Watch Project/My Project/Debug/My Project.hex b/Smol Watch Project/My Project/Debug/My Project.hex
new file mode 100644
index 0000000..06e00b4
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/My Project.hex	
@@ -0,0 +1,537 @@
+:1000000020210020210100001D0100001D01000031
+:1000100000000000000000000000000000000000E0
+:100020000000000000000000000000001D010000B2
+:1000300000000000000000001D0100001D01000084
+:100040001D0100001D010000890E0000350C00009C
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+:100070001D0100000000000000000000AD150000A0
+:100080001D0100001D0100001D010000E519000018
+:100090001D0100001D0100001D0100001D010000E8
+:1000A0001D0100001D01000010B5064C2378002B37
+:1000B00007D1054B002B02D0044800E000BF01230C
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+:1000D000084B10B5002B03D00749084800E000BFCB
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+:1001300011681960043304320C498B42F8D30C4B1C
+:1001400002E000221A6004330A4A9342F9D30A4AB1
+:10015000FF210A4B8B439360094B9847094B984703
+:10016000FEE7C046402100000000002038000020CB
+:10017000380000201C01002000ED00E0000000001D
+:10018000B11E0000F9190000034A516980239B0049
+:100190000B4353617047C0460008004010B5034B45
+:1001A000984703490348044B984710BD8901000054
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diff --git a/Smol Watch Project/My Project/Debug/My Project.lss b/Smol Watch Project/My Project/Debug/My Project.lss
new file mode 100644
index 0000000..b6e56b2
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/My Project.lss	
@@ -0,0 +1,5931 @@
+
+My Project.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .text         00002140  00000000  00000000  00010000  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .relocate     00000038  20000000  00002140  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          000000e4  20000038  00002178  00020038  2**2
+                  ALLOC
+  3 .stack        00002004  2000011c  0000225c  00020038  2**0
+                  ALLOC
+  4 .ARM.attributes 00000028  00000000  00000000  00020038  2**0
+                  CONTENTS, READONLY
+  5 .comment      00000059  00000000  00000000  00020060  2**0
+                  CONTENTS, READONLY
+  6 .debug_info   000315e1  00000000  00000000  000200b9  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  7 .debug_abbrev 00004084  00000000  00000000  0005169a  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  8 .debug_loc    00011a80  00000000  00000000  0005571e  2**0
+                  CONTENTS, READONLY, DEBUGGING
+  9 .debug_aranges 00000d00  00000000  00000000  0006719e  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 10 .debug_ranges 00000d80  00000000  00000000  00067e9e  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_macro  0001de3f  00000000  00000000  00068c1e  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_line   00015702  00000000  00000000  00086a5d  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_str    000912d9  00000000  00000000  0009c15f  2**0
+                  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_frame  000020dc  00000000  00000000  0012d438  2**2
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+       0:	20 21 00 20 21 01 00 00 1d 01 00 00 1d 01 00 00      !. !...........
+	...
+      2c:	1d 01 00 00 00 00 00 00 00 00 00 00 1d 01 00 00     ................
+      3c:	1d 01 00 00 1d 01 00 00 1d 01 00 00 89 0e 00 00     ................
+      4c:	35 0c 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00     5...............
+      5c:	1d 01 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00     ................
+      6c:	1d 01 00 00 1d 01 00 00 00 00 00 00 00 00 00 00     ................
+      7c:	ad 15 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00     ................
+      8c:	e5 19 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00     ................
+      9c:	1d 01 00 00 1d 01 00 00 1d 01 00 00                 ............
+
+000000a8 <__do_global_dtors_aux>:
+      a8:	b510      	push	{r4, lr}
+      aa:	4c06      	ldr	r4, [pc, #24]	; (c4 <__do_global_dtors_aux+0x1c>)
+      ac:	7823      	ldrb	r3, [r4, #0]
+      ae:	2b00      	cmp	r3, #0
+      b0:	d107      	bne.n	c2 <__do_global_dtors_aux+0x1a>
+      b2:	4b05      	ldr	r3, [pc, #20]	; (c8 <__do_global_dtors_aux+0x20>)
+      b4:	2b00      	cmp	r3, #0
+      b6:	d002      	beq.n	be <__do_global_dtors_aux+0x16>
+      b8:	4804      	ldr	r0, [pc, #16]	; (cc <__do_global_dtors_aux+0x24>)
+      ba:	e000      	b.n	be <__do_global_dtors_aux+0x16>
+      bc:	bf00      	nop
+      be:	2301      	movs	r3, #1
+      c0:	7023      	strb	r3, [r4, #0]
+      c2:	bd10      	pop	{r4, pc}
+      c4:	20000038 	.word	0x20000038
+      c8:	00000000 	.word	0x00000000
+      cc:	00002140 	.word	0x00002140
+
+000000d0 <frame_dummy>:
+      d0:	4b08      	ldr	r3, [pc, #32]	; (f4 <frame_dummy+0x24>)
+      d2:	b510      	push	{r4, lr}
+      d4:	2b00      	cmp	r3, #0
+      d6:	d003      	beq.n	e0 <frame_dummy+0x10>
+      d8:	4907      	ldr	r1, [pc, #28]	; (f8 <frame_dummy+0x28>)
+      da:	4808      	ldr	r0, [pc, #32]	; (fc <frame_dummy+0x2c>)
+      dc:	e000      	b.n	e0 <frame_dummy+0x10>
+      de:	bf00      	nop
+      e0:	4807      	ldr	r0, [pc, #28]	; (100 <frame_dummy+0x30>)
+      e2:	6803      	ldr	r3, [r0, #0]
+      e4:	2b00      	cmp	r3, #0
+      e6:	d100      	bne.n	ea <frame_dummy+0x1a>
+      e8:	bd10      	pop	{r4, pc}
+      ea:	4b06      	ldr	r3, [pc, #24]	; (104 <frame_dummy+0x34>)
+      ec:	2b00      	cmp	r3, #0
+      ee:	d0fb      	beq.n	e8 <frame_dummy+0x18>
+      f0:	4798      	blx	r3
+      f2:	e7f9      	b.n	e8 <frame_dummy+0x18>
+      f4:	00000000 	.word	0x00000000
+      f8:	2000003c 	.word	0x2000003c
+      fc:	00002140 	.word	0x00002140
+     100:	00002140 	.word	0x00002140
+     104:	00000000 	.word	0x00000000
+
+00000108 <atmel_start_init>:
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+     108:	b510      	push	{r4, lr}
+	system_init();
+     10a:	4b02      	ldr	r3, [pc, #8]	; (114 <atmel_start_init+0xc>)
+     10c:	4798      	blx	r3
+	sleep_manager_init();
+     10e:	4b02      	ldr	r3, [pc, #8]	; (118 <atmel_start_init+0x10>)
+     110:	4798      	blx	r3
+}
+     112:	bd10      	pop	{r4, pc}
+     114:	00000309 	.word	0x00000309
+     118:	00001b8d 	.word	0x00001b8d
+
+0000011c <Dummy_Handler>:
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+     11c:	e7fe      	b.n	11c <Dummy_Handler>
+	...
+
+00000120 <Reset_Handler>:
+{
+     120:	b510      	push	{r4, lr}
+        if (pSrc != pDest) {
+     122:	4a10      	ldr	r2, [pc, #64]	; (164 <Reset_Handler+0x44>)
+     124:	4b10      	ldr	r3, [pc, #64]	; (168 <Reset_Handler+0x48>)
+     126:	429a      	cmp	r2, r3
+     128:	d009      	beq.n	13e <Reset_Handler+0x1e>
+     12a:	4b0f      	ldr	r3, [pc, #60]	; (168 <Reset_Handler+0x48>)
+     12c:	4a0d      	ldr	r2, [pc, #52]	; (164 <Reset_Handler+0x44>)
+     12e:	e003      	b.n	138 <Reset_Handler+0x18>
+                        *pDest++ = *pSrc++;
+     130:	6811      	ldr	r1, [r2, #0]
+     132:	6019      	str	r1, [r3, #0]
+     134:	3304      	adds	r3, #4
+     136:	3204      	adds	r2, #4
+                for (; pDest < &_erelocate;) {
+     138:	490c      	ldr	r1, [pc, #48]	; (16c <Reset_Handler+0x4c>)
+     13a:	428b      	cmp	r3, r1
+     13c:	d3f8      	bcc.n	130 <Reset_Handler+0x10>
+                        *pDest++ = *pSrc++;
+     13e:	4b0c      	ldr	r3, [pc, #48]	; (170 <Reset_Handler+0x50>)
+     140:	e002      	b.n	148 <Reset_Handler+0x28>
+                *pDest++ = 0;
+     142:	2200      	movs	r2, #0
+     144:	601a      	str	r2, [r3, #0]
+     146:	3304      	adds	r3, #4
+        for (pDest = &_szero; pDest < &_ezero;) {
+     148:	4a0a      	ldr	r2, [pc, #40]	; (174 <Reset_Handler+0x54>)
+     14a:	4293      	cmp	r3, r2
+     14c:	d3f9      	bcc.n	142 <Reset_Handler+0x22>
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+     14e:	4a0a      	ldr	r2, [pc, #40]	; (178 <Reset_Handler+0x58>)
+     150:	21ff      	movs	r1, #255	; 0xff
+     152:	4b0a      	ldr	r3, [pc, #40]	; (17c <Reset_Handler+0x5c>)
+     154:	438b      	bics	r3, r1
+     156:	6093      	str	r3, [r2, #8]
+        __libc_init_array();
+     158:	4b09      	ldr	r3, [pc, #36]	; (180 <Reset_Handler+0x60>)
+     15a:	4798      	blx	r3
+        main();
+     15c:	4b09      	ldr	r3, [pc, #36]	; (184 <Reset_Handler+0x64>)
+     15e:	4798      	blx	r3
+     160:	e7fe      	b.n	160 <Reset_Handler+0x40>
+     162:	46c0      	nop			; (mov r8, r8)
+     164:	00002140 	.word	0x00002140
+     168:	20000000 	.word	0x20000000
+     16c:	20000038 	.word	0x20000038
+     170:	20000038 	.word	0x20000038
+     174:	2000011c 	.word	0x2000011c
+     178:	e000ed00 	.word	0xe000ed00
+     17c:	00000000 	.word	0x00000000
+     180:	00001eb1 	.word	0x00001eb1
+     184:	000019f9 	.word	0x000019f9
+
+00000188 <CALENDAR_0_CLOCK_init>:
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     188:	4a03      	ldr	r2, [pc, #12]	; (198 <CALENDAR_0_CLOCK_init+0x10>)
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     18a:	6951      	ldr	r1, [r2, #20]
+     18c:	2380      	movs	r3, #128	; 0x80
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     18e:	009b      	lsls	r3, r3, #2
+     190:	430b      	orrs	r3, r1
+	tmp |= PORT_PMUX_PMUXE(data);
+     192:	6153      	str	r3, [r2, #20]
+     194:	4770      	bx	lr
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     196:	46c0      	nop			; (mov r8, r8)
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     198:	40000800 	.word	0x40000800
+
+0000019c <CALENDAR_0_init>:
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     19c:	b510      	push	{r4, lr}
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     19e:	4b03      	ldr	r3, [pc, #12]	; (1ac <CALENDAR_0_init+0x10>)
+     1a0:	4798      	blx	r3
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     1a2:	4903      	ldr	r1, [pc, #12]	; (1b0 <CALENDAR_0_init+0x14>)
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     1a4:	4803      	ldr	r0, [pc, #12]	; (1b4 <CALENDAR_0_init+0x18>)
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     1a6:	4b04      	ldr	r3, [pc, #16]	; (1b8 <CALENDAR_0_init+0x1c>)
+	tmp |= PORT_PMUX_PMUXO(data);
+     1a8:	4798      	blx	r3
+     1aa:	bd10      	pop	{r4, pc}
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     1ac:	00000189 	.word	0x00000189
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     1b0:	40002400 	.word	0x40002400
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     1b4:	200000b4 	.word	0x200000b4
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     1b8:	000006b5 	.word	0x000006b5
+
+000001bc <I2C_0_PORT_init>:
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     1bc:	b570      	push	{r4, r5, r6, lr}
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     1be:	4b13      	ldr	r3, [pc, #76]	; (20c <I2C_0_PORT_init+0x50>)
+     1c0:	20de      	movs	r0, #222	; 0xde
+	tmp |= PORT_PMUX_PMUXE(data);
+     1c2:	5c19      	ldrb	r1, [r3, r0]
+     1c4:	2204      	movs	r2, #4
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     1c6:	4391      	bics	r1, r2
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     1c8:	5419      	strb	r1, [r3, r0]
+     1ca:	5c19      	ldrb	r1, [r3, r0]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     1cc:	2501      	movs	r5, #1
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     1ce:	43a9      	bics	r1, r5
+     1d0:	2401      	movs	r4, #1
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     1d2:	4321      	orrs	r1, r4
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     1d4:	b2c9      	uxtb	r1, r1
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     1d6:	5419      	strb	r1, [r3, r0]
+	tmp |= PORT_PMUX_PMUXO(data);
+     1d8:	381f      	subs	r0, #31
+     1da:	5c19      	ldrb	r1, [r3, r0]
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     1dc:	260f      	movs	r6, #15
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     1de:	43b1      	bics	r1, r6
+     1e0:	2602      	movs	r6, #2
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     1e2:	4331      	orrs	r1, r6
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     1e4:	b2c9      	uxtb	r1, r1
+     1e6:	5419      	strb	r1, [r3, r0]
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     1e8:	21df      	movs	r1, #223	; 0xdf
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     1ea:	5c5e      	ldrb	r6, [r3, r1]
+     1ec:	4396      	bics	r6, r2
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     1ee:	545e      	strb	r6, [r3, r1]
+     1f0:	5c5a      	ldrb	r2, [r3, r1]
+	tmp |= PORT_PMUX_PMUXE(data);
+     1f2:	43aa      	bics	r2, r5
+     1f4:	4322      	orrs	r2, r4
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     1f6:	b2d2      	uxtb	r2, r2
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     1f8:	545a      	strb	r2, [r3, r1]
+     1fa:	5c1a      	ldrb	r2, [r3, r0]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     1fc:	39d0      	subs	r1, #208	; 0xd0
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     1fe:	400a      	ands	r2, r1
+     200:	2120      	movs	r1, #32
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     202:	430a      	orrs	r2, r1
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     204:	b2d2      	uxtb	r2, r2
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     206:	541a      	strb	r2, [r3, r0]
+	tmp |= PORT_PMUX_PMUXO(data);
+     208:	bd70      	pop	{r4, r5, r6, pc}
+     20a:	46c0      	nop			; (mov r8, r8)
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     20c:	41006000 	.word	0x41006000
+
+00000210 <I2C_0_CLOCK_init>:
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     210:	4b06      	ldr	r3, [pc, #24]	; (22c <I2C_0_CLOCK_init+0x1c>)
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     212:	2140      	movs	r1, #64	; 0x40
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     214:	22c4      	movs	r2, #196	; 0xc4
+     216:	5099      	str	r1, [r3, r2]
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     218:	3103      	adds	r1, #3
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     21a:	3a08      	subs	r2, #8
+     21c:	5099      	str	r1, [r3, r2]
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     21e:	4a04      	ldr	r2, [pc, #16]	; (230 <I2C_0_CLOCK_init+0x20>)
+     220:	69d3      	ldr	r3, [r2, #28]
+	tmp |= PORT_PMUX_PMUXE(data);
+     222:	393f      	subs	r1, #63	; 0x3f
+     224:	430b      	orrs	r3, r1
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     226:	61d3      	str	r3, [r2, #28]
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     228:	4770      	bx	lr
+     22a:	46c0      	nop			; (mov r8, r8)
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     22c:	40001c00 	.word	0x40001c00
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     230:	40000800 	.word	0x40000800
+
+00000234 <I2C_0_init>:
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     234:	b510      	push	{r4, lr}
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     236:	4b04      	ldr	r3, [pc, #16]	; (248 <I2C_0_init+0x14>)
+	tmp |= PORT_PMUX_PMUXO(data);
+     238:	4798      	blx	r3
+     23a:	4904      	ldr	r1, [pc, #16]	; (24c <I2C_0_init+0x18>)
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     23c:	4804      	ldr	r0, [pc, #16]	; (250 <I2C_0_init+0x1c>)
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     23e:	4b05      	ldr	r3, [pc, #20]	; (254 <I2C_0_init+0x20>)
+     240:	4798      	blx	r3
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     242:	4b05      	ldr	r3, [pc, #20]	; (258 <I2C_0_init+0x24>)
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     244:	4798      	blx	r3
+     246:	bd10      	pop	{r4, pc}
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     248:	00000211 	.word	0x00000211
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     24c:	42000800 	.word	0x42000800
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     250:	200000f8 	.word	0x200000f8
+	tmp |= PORT_PMUX_PMUXE(data);
+     254:	000008a9 	.word	0x000008a9
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     258:	000001bd 	.word	0x000001bd
+
+0000025c <delay_driver_init>:
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     25c:	b510      	push	{r4, lr}
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     25e:	4802      	ldr	r0, [pc, #8]	; (268 <delay_driver_init+0xc>)
+     260:	4b02      	ldr	r3, [pc, #8]	; (26c <delay_driver_init+0x10>)
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     262:	4798      	blx	r3
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     264:	bd10      	pop	{r4, pc}
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     266:	46c0      	nop			; (mov r8, r8)
+	tmp |= PORT_PMUX_PMUXO(data);
+     268:	e000e010 	.word	0xe000e010
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     26c:	0000082d 	.word	0x0000082d
+
+00000270 <PWM_0_PORT_init>:
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     270:	b530      	push	{r4, r5, lr}
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     272:	4b0f      	ldr	r3, [pc, #60]	; (2b0 <PWM_0_PORT_init+0x40>)
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     274:	2254      	movs	r2, #84	; 0x54
+     276:	5c99      	ldrb	r1, [r3, r2]
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     278:	2501      	movs	r5, #1
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     27a:	43a9      	bics	r1, r5
+     27c:	2401      	movs	r4, #1
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+     27e:	4321      	orrs	r1, r4
+     280:	b2c9      	uxtb	r1, r1
+     282:	5499      	strb	r1, [r3, r2]
+	tmp |= PORT_PMUX_PMUXE(data);
+     284:	203a      	movs	r0, #58	; 0x3a
+     286:	5c19      	ldrb	r1, [r3, r0]
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     288:	3a45      	subs	r2, #69	; 0x45
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     28a:	4391      	bics	r1, r2
+     28c:	2204      	movs	r2, #4
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     28e:	4311      	orrs	r1, r2
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+     290:	b2c9      	uxtb	r1, r1
+     292:	5419      	strb	r1, [r3, r0]
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     294:	2155      	movs	r1, #85	; 0x55
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+     296:	5c5a      	ldrb	r2, [r3, r1]
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+     298:	43aa      	bics	r2, r5
+	tmp |= PORT_PMUX_PMUXO(data);
+     29a:	4322      	orrs	r2, r4
+     29c:	b2d2      	uxtb	r2, r2
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+     29e:	545a      	strb	r2, [r3, r1]
+	gpio_set_pin_function(SEG21, PINMUX_PA19B_SLCD_LP35);
+
+	gpio_set_pin_function(SEG22, PINMUX_PB16B_SLCD_LP42);
+
+	gpio_set_pin_function(SEG23, PINMUX_PB17B_SLCD_LP43);
+}
+     2a0:	5c1a      	ldrb	r2, [r3, r0]
+     2a2:	3946      	subs	r1, #70	; 0x46
+     2a4:	400a      	ands	r2, r1
+     2a6:	2140      	movs	r1, #64	; 0x40
+     2a8:	430a      	orrs	r2, r1
+     2aa:	b2d2      	uxtb	r2, r2
+     2ac:	541a      	strb	r2, [r3, r0]
+}
+     2ae:	bd30      	pop	{r4, r5, pc}
+     2b0:	41006000 	.word	0x41006000
+
+000002b4 <PWM_0_CLOCK_init>:
+}
+
+static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
+     2b4:	4a05      	ldr	r2, [pc, #20]	; (2cc <PWM_0_CLOCK_init+0x18>)
+     2b6:	69d1      	ldr	r1, [r2, #28]
+     2b8:	2380      	movs	r3, #128	; 0x80
+     2ba:	011b      	lsls	r3, r3, #4
+     2bc:	430b      	orrs	r3, r1
+     2be:	61d3      	str	r3, [r2, #28]
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+     2c0:	2140      	movs	r1, #64	; 0x40
+     2c2:	23e0      	movs	r3, #224	; 0xe0
+     2c4:	4a02      	ldr	r2, [pc, #8]	; (2d0 <PWM_0_CLOCK_init+0x1c>)
+     2c6:	50d1      	str	r1, [r2, r3]
+}
+     2c8:	4770      	bx	lr
+     2ca:	46c0      	nop			; (mov r8, r8)
+     2cc:	40000800 	.word	0x40000800
+     2d0:	40001c00 	.word	0x40001c00
+
+000002d4 <PWM_0_init>:
+{
+     2d4:	b510      	push	{r4, lr}
+	PWM_0_CLOCK_init();
+     2d6:	4b06      	ldr	r3, [pc, #24]	; (2f0 <PWM_0_init+0x1c>)
+     2d8:	4798      	blx	r3
+	PWM_0_PORT_init();
+     2da:	4b06      	ldr	r3, [pc, #24]	; (2f4 <PWM_0_init+0x20>)
+     2dc:	4798      	blx	r3
+	pwm_init(&PWM_0, TC3, _tc_get_pwm());
+     2de:	4b06      	ldr	r3, [pc, #24]	; (2f8 <PWM_0_init+0x24>)
+     2e0:	4798      	blx	r3
+     2e2:	0002      	movs	r2, r0
+     2e4:	4905      	ldr	r1, [pc, #20]	; (2fc <PWM_0_init+0x28>)
+     2e6:	4806      	ldr	r0, [pc, #24]	; (300 <PWM_0_init+0x2c>)
+     2e8:	4b06      	ldr	r3, [pc, #24]	; (304 <PWM_0_init+0x30>)
+     2ea:	4798      	blx	r3
+}
+     2ec:	bd10      	pop	{r4, pc}
+     2ee:	46c0      	nop			; (mov r8, r8)
+     2f0:	000002b5 	.word	0x000002b5
+     2f4:	00000271 	.word	0x00000271
+     2f8:	000019d9 	.word	0x000019d9
+     2fc:	42002c00 	.word	0x42002c00
+     300:	20000090 	.word	0x20000090
+     304:	00000999 	.word	0x00000999
+
+00000308 <system_init>:
+	slcd_sync_init(&SEGMENT_LCD_0, SLCD);
+	SEGMENT_LCD_0_PORT_init();
+}
+
+void system_init(void)
+{
+     308:	b5f0      	push	{r4, r5, r6, r7, lr}
+     30a:	46c6      	mov	lr, r8
+     30c:	b500      	push	{lr}
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+	_init_chip();
+     30e:	4b1c      	ldr	r3, [pc, #112]	; (380 <system_init+0x78>)
+     310:	4798      	blx	r3
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+     312:	22c0      	movs	r2, #192	; 0xc0
+     314:	05d2      	lsls	r2, r2, #23
+     316:	2404      	movs	r4, #4
+     318:	6054      	str	r4, [r2, #4]
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+     31a:	4b1a      	ldr	r3, [pc, #104]	; (384 <system_init+0x7c>)
+     31c:	491a      	ldr	r1, [pc, #104]	; (388 <system_init+0x80>)
+     31e:	6299      	str	r1, [r3, #40]	; 0x28
+     320:	491a      	ldr	r1, [pc, #104]	; (38c <system_init+0x84>)
+     322:	6299      	str	r1, [r3, #40]	; 0x28
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+     324:	6054      	str	r4, [r2, #4]
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+     326:	2042      	movs	r0, #66	; 0x42
+     328:	5c19      	ldrb	r1, [r3, r0]
+     32a:	2504      	movs	r5, #4
+     32c:	4329      	orrs	r1, r5
+     32e:	b2c9      	uxtb	r1, r1
+     330:	5419      	strb	r1, [r3, r0]
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+     332:	6154      	str	r4, [r2, #20]
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     334:	5c1c      	ldrb	r4, [r3, r0]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     336:	2101      	movs	r1, #1
+     338:	438c      	bics	r4, r1
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     33a:	541c      	strb	r4, [r3, r0]
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+     33c:	2794      	movs	r7, #148	; 0x94
+     33e:	51d1      	str	r1, [r2, r7]
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+     340:	2688      	movs	r6, #136	; 0x88
+     342:	5191      	str	r1, [r2, r6]
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+     344:	3066      	adds	r0, #102	; 0x66
+     346:	4c12      	ldr	r4, [pc, #72]	; (390 <system_init+0x88>)
+     348:	501c      	str	r4, [r3, r0]
+     34a:	24c0      	movs	r4, #192	; 0xc0
+     34c:	0624      	lsls	r4, r4, #24
+     34e:	46a0      	mov	r8, r4
+     350:	501c      	str	r4, [r3, r0]
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     352:	24c0      	movs	r4, #192	; 0xc0
+     354:	46a4      	mov	ip, r4
+     356:	5d1c      	ldrb	r4, [r3, r4]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     358:	438c      	bics	r4, r1
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     35a:	4665      	mov	r5, ip
+     35c:	555c      	strb	r4, [r3, r5]
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+     35e:	2408      	movs	r4, #8
+     360:	51d4      	str	r4, [r2, r7]
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+     362:	5194      	str	r4, [r2, r6]
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+     364:	4a0b      	ldr	r2, [pc, #44]	; (394 <system_init+0x8c>)
+     366:	501a      	str	r2, [r3, r0]
+     368:	4642      	mov	r2, r8
+     36a:	501a      	str	r2, [r3, r0]
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+     36c:	301b      	adds	r0, #27
+     36e:	5c1a      	ldrb	r2, [r3, r0]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+     370:	438a      	bics	r2, r1
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+     372:	541a      	strb	r2, [r3, r0]
+	// Set pin direction to output
+	gpio_set_pin_direction(D0, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(D0, GPIO_PIN_FUNCTION_OFF);
+
+	delay_driver_init();
+     374:	4b08      	ldr	r3, [pc, #32]	; (398 <system_init+0x90>)
+     376:	4798      	blx	r3
+	PWM_0_init();
+
+	PWM_1_init();
+	SEGMENT_LCD_0_init();
+*/
+}
+     378:	bc04      	pop	{r2}
+     37a:	4690      	mov	r8, r2
+     37c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     37e:	46c0      	nop			; (mov r8, r8)
+     380:	00000b3d 	.word	0x00000b3d
+     384:	41006000 	.word	0x41006000
+     388:	40020004 	.word	0x40020004
+     38c:	c0020000 	.word	0xc0020000
+     390:	40000001 	.word	0x40000001
+     394:	40000008 	.word	0x40000008
+     398:	0000025d 	.word	0x0000025d
+
+0000039c <leap_year>:
+ *  \retval false  not leap year.
+ *  \retval true  leap year.
+ */
+static bool leap_year(uint16_t year)
+{
+	if (year & 3) {
+     39c:	0783      	lsls	r3, r0, #30
+     39e:	d101      	bne.n	3a4 <leap_year+0x8>
+		return false;
+	} else {
+		return true;
+     3a0:	2001      	movs	r0, #1
+	}
+}
+     3a2:	4770      	bx	lr
+		return false;
+     3a4:	2000      	movs	r0, #0
+     3a6:	e7fc      	b.n	3a2 <leap_year+0x6>
+
+000003a8 <get_secs_in_month>:
+
+/** \brief calculate the seconds in specified year/month
+ *  \retval 0  month error.
+ */
+static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
+{
+     3a8:	b510      	push	{r4, lr}
+     3aa:	000c      	movs	r4, r1
+	uint32_t sec_in_month = 0;
+
+	if (leap_year(year)) {
+     3ac:	b280      	uxth	r0, r0
+     3ae:	4b10      	ldr	r3, [pc, #64]	; (3f0 <get_secs_in_month+0x48>)
+     3b0:	4798      	blx	r3
+     3b2:	2800      	cmp	r0, #0
+     3b4:	d00b      	beq.n	3ce <get_secs_in_month+0x26>
+		switch (month) {
+     3b6:	2c0c      	cmp	r4, #12
+     3b8:	d803      	bhi.n	3c2 <get_secs_in_month+0x1a>
+     3ba:	00a4      	lsls	r4, r4, #2
+     3bc:	4b0d      	ldr	r3, [pc, #52]	; (3f4 <get_secs_in_month+0x4c>)
+     3be:	591b      	ldr	r3, [r3, r4]
+     3c0:	469f      	mov	pc, r3
+	uint32_t sec_in_month = 0;
+     3c2:	2000      	movs	r0, #0
+     3c4:	e010      	b.n	3e8 <get_secs_in_month+0x40>
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_29DAYS;
+     3c6:	480c      	ldr	r0, [pc, #48]	; (3f8 <get_secs_in_month+0x50>)
+			break;
+     3c8:	e00e      	b.n	3e8 <get_secs_in_month+0x40>
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+     3ca:	480c      	ldr	r0, [pc, #48]	; (3fc <get_secs_in_month+0x54>)
+			break;
+     3cc:	e00c      	b.n	3e8 <get_secs_in_month+0x40>
+		default:
+			break;
+		}
+	} else {
+		switch (month) {
+     3ce:	2c0c      	cmp	r4, #12
+     3d0:	d803      	bhi.n	3da <get_secs_in_month+0x32>
+     3d2:	00a4      	lsls	r4, r4, #2
+     3d4:	4b0a      	ldr	r3, [pc, #40]	; (400 <get_secs_in_month+0x58>)
+     3d6:	591b      	ldr	r3, [r3, r4]
+     3d8:	469f      	mov	pc, r3
+	uint32_t sec_in_month = 0;
+     3da:	2000      	movs	r0, #0
+     3dc:	e004      	b.n	3e8 <get_secs_in_month+0x40>
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_28DAYS;
+     3de:	4809      	ldr	r0, [pc, #36]	; (404 <get_secs_in_month+0x5c>)
+			break;
+     3e0:	e002      	b.n	3e8 <get_secs_in_month+0x40>
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+     3e2:	4806      	ldr	r0, [pc, #24]	; (3fc <get_secs_in_month+0x54>)
+			break;
+     3e4:	e000      	b.n	3e8 <get_secs_in_month+0x40>
+			sec_in_month = SECS_IN_31DAYS;
+     3e6:	4808      	ldr	r0, [pc, #32]	; (408 <get_secs_in_month+0x60>)
+			break;
+		}
+	}
+
+	return sec_in_month;
+}
+     3e8:	bd10      	pop	{r4, pc}
+			sec_in_month = SECS_IN_31DAYS;
+     3ea:	4807      	ldr	r0, [pc, #28]	; (408 <get_secs_in_month+0x60>)
+	return sec_in_month;
+     3ec:	e7fc      	b.n	3e8 <get_secs_in_month+0x40>
+     3ee:	46c0      	nop			; (mov r8, r8)
+     3f0:	0000039d 	.word	0x0000039d
+     3f4:	00001ef8 	.word	0x00001ef8
+     3f8:	00263b80 	.word	0x00263b80
+     3fc:	00278d00 	.word	0x00278d00
+     400:	00001f2c 	.word	0x00001f2c
+     404:	0024ea00 	.word	0x0024ea00
+     408:	0028de80 	.word	0x0028de80
+
+0000040c <convert_timestamp_to_datetime>:
+
+/** \brief convert timestamp to date/time
+ */
+static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
+                                             struct calendar_date_time *dt)
+{
+     40c:	b5f0      	push	{r4, r5, r6, r7, lr}
+     40e:	46c6      	mov	lr, r8
+     410:	b500      	push	{lr}
+     412:	000c      	movs	r4, r1
+     414:	4690      	mov	r8, r2
+	uint32_t tmp, sec_in_year, sec_in_month;
+	uint32_t tmp_year    = calendar->base_year;
+     416:	6986      	ldr	r6, [r0, #24]
+     418:	e004      	b.n	424 <convert_timestamp_to_datetime+0x18>
+
+	tmp = ts;
+
+	/* Find year */
+	while (true) {
+		sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+     41a:	4b1f      	ldr	r3, [pc, #124]	; (498 <convert_timestamp_to_datetime+0x8c>)
+
+		if (tmp >= sec_in_year) {
+     41c:	429c      	cmp	r4, r3
+     41e:	d309      	bcc.n	434 <convert_timestamp_to_datetime+0x28>
+			tmp -= sec_in_year;
+     420:	1ae4      	subs	r4, r4, r3
+			tmp_year++;
+     422:	3601      	adds	r6, #1
+		sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+     424:	b2b7      	uxth	r7, r6
+     426:	0038      	movs	r0, r7
+     428:	4b1c      	ldr	r3, [pc, #112]	; (49c <convert_timestamp_to_datetime+0x90>)
+     42a:	4798      	blx	r3
+     42c:	2800      	cmp	r0, #0
+     42e:	d0f4      	beq.n	41a <convert_timestamp_to_datetime+0xe>
+     430:	4b1b      	ldr	r3, [pc, #108]	; (4a0 <convert_timestamp_to_datetime+0x94>)
+     432:	e7f3      	b.n	41c <convert_timestamp_to_datetime+0x10>
+     434:	2501      	movs	r5, #1
+			break;
+		}
+	}
+	/* Find month of year */
+	while (true) {
+		sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+     436:	0029      	movs	r1, r5
+     438:	0030      	movs	r0, r6
+     43a:	4b1a      	ldr	r3, [pc, #104]	; (4a4 <convert_timestamp_to_datetime+0x98>)
+     43c:	4798      	blx	r3
+
+		if (tmp >= sec_in_month) {
+     43e:	4284      	cmp	r4, r0
+     440:	d303      	bcc.n	44a <convert_timestamp_to_datetime+0x3e>
+			tmp -= sec_in_month;
+     442:	1a24      	subs	r4, r4, r0
+			tmp_month++;
+     444:	3501      	adds	r5, #1
+     446:	b2ed      	uxtb	r5, r5
+		sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+     448:	e7f5      	b.n	436 <convert_timestamp_to_datetime+0x2a>
+     44a:	2101      	movs	r1, #1
+			break;
+		}
+	}
+	/* Find day of month */
+	while (true) {
+		if (tmp >= SECS_IN_DAY) {
+     44c:	4b16      	ldr	r3, [pc, #88]	; (4a8 <convert_timestamp_to_datetime+0x9c>)
+     44e:	429c      	cmp	r4, r3
+     450:	d905      	bls.n	45e <convert_timestamp_to_datetime+0x52>
+			tmp -= SECS_IN_DAY;
+     452:	4b16      	ldr	r3, [pc, #88]	; (4ac <convert_timestamp_to_datetime+0xa0>)
+     454:	469c      	mov	ip, r3
+     456:	4464      	add	r4, ip
+			tmp_day++;
+     458:	3101      	adds	r1, #1
+     45a:	b2c9      	uxtb	r1, r1
+		if (tmp >= SECS_IN_DAY) {
+     45c:	e7f6      	b.n	44c <convert_timestamp_to_datetime+0x40>
+     45e:	2200      	movs	r2, #0
+			break;
+		}
+	}
+	/* Find hour of day */
+	while (true) {
+		if (tmp >= SECS_IN_HOUR) {
+     460:	4b13      	ldr	r3, [pc, #76]	; (4b0 <convert_timestamp_to_datetime+0xa4>)
+     462:	429c      	cmp	r4, r3
+     464:	d905      	bls.n	472 <convert_timestamp_to_datetime+0x66>
+			tmp -= SECS_IN_HOUR;
+     466:	4b13      	ldr	r3, [pc, #76]	; (4b4 <convert_timestamp_to_datetime+0xa8>)
+     468:	469c      	mov	ip, r3
+     46a:	4464      	add	r4, ip
+			tmp_hour++;
+     46c:	3201      	adds	r2, #1
+     46e:	b2d2      	uxtb	r2, r2
+		if (tmp >= SECS_IN_HOUR) {
+     470:	e7f6      	b.n	460 <convert_timestamp_to_datetime+0x54>
+     472:	2300      	movs	r3, #0
+			break;
+		}
+	}
+	/* Find minute in hour */
+	while (true) {
+		if (tmp >= SECS_IN_MINUTE) {
+     474:	2c3b      	cmp	r4, #59	; 0x3b
+     476:	d903      	bls.n	480 <convert_timestamp_to_datetime+0x74>
+			tmp -= SECS_IN_MINUTE;
+     478:	3c3c      	subs	r4, #60	; 0x3c
+			tmp_minutes++;
+     47a:	3301      	adds	r3, #1
+     47c:	b2db      	uxtb	r3, r3
+		if (tmp >= SECS_IN_MINUTE) {
+     47e:	e7f9      	b.n	474 <convert_timestamp_to_datetime+0x68>
+		} else {
+			break;
+		}
+	}
+
+	dt->date.year  = tmp_year;
+     480:	4640      	mov	r0, r8
+     482:	80c7      	strh	r7, [r0, #6]
+	dt->date.month = tmp_month;
+     484:	7145      	strb	r5, [r0, #5]
+	dt->date.day   = tmp_day;
+     486:	7101      	strb	r1, [r0, #4]
+	dt->time.hour  = tmp_hour;
+     488:	7082      	strb	r2, [r0, #2]
+	dt->time.min   = tmp_minutes;
+     48a:	7043      	strb	r3, [r0, #1]
+	dt->time.sec   = tmp;
+     48c:	7004      	strb	r4, [r0, #0]
+
+	return ERR_NONE;
+}
+     48e:	2000      	movs	r0, #0
+     490:	bc04      	pop	{r2}
+     492:	4690      	mov	r8, r2
+     494:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     496:	46c0      	nop			; (mov r8, r8)
+     498:	01e13380 	.word	0x01e13380
+     49c:	0000039d 	.word	0x0000039d
+     4a0:	01e28500 	.word	0x01e28500
+     4a4:	000003a9 	.word	0x000003a9
+     4a8:	0001517f 	.word	0x0001517f
+     4ac:	fffeae80 	.word	0xfffeae80
+     4b0:	00000e0f 	.word	0x00000e0f
+     4b4:	fffff1f0 	.word	0xfffff1f0
+
+000004b8 <convert_datetime_to_timestamp>:
+
+/** \brief convert date/time to timestamp
+ *  \return timestamp
+ */
+static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
+{
+     4b8:	b5f0      	push	{r4, r5, r6, r7, lr}
+     4ba:	46de      	mov	lr, fp
+     4bc:	4657      	mov	r7, sl
+     4be:	464e      	mov	r6, r9
+     4c0:	4645      	mov	r5, r8
+     4c2:	b5e0      	push	{r5, r6, r7, lr}
+     4c4:	b083      	sub	sp, #12
+	uint32_t tmp = 0;
+	uint32_t i   = 0;
+	uint8_t  year, month, day, hour, minutes, seconds;
+
+	year    = dt->date.year - calendar->base_year;
+     4c6:	88cb      	ldrh	r3, [r1, #6]
+     4c8:	9300      	str	r3, [sp, #0]
+     4ca:	b2de      	uxtb	r6, r3
+     4cc:	6983      	ldr	r3, [r0, #24]
+     4ce:	4699      	mov	r9, r3
+     4d0:	466a      	mov	r2, sp
+     4d2:	7113      	strb	r3, [r2, #4]
+     4d4:	7913      	ldrb	r3, [r2, #4]
+     4d6:	1af6      	subs	r6, r6, r3
+     4d8:	b2f6      	uxtb	r6, r6
+	month   = dt->date.month;
+     4da:	794f      	ldrb	r7, [r1, #5]
+	day     = dt->date.day;
+     4dc:	790b      	ldrb	r3, [r1, #4]
+     4de:	469a      	mov	sl, r3
+	hour    = dt->time.hour;
+     4e0:	788b      	ldrb	r3, [r1, #2]
+     4e2:	4698      	mov	r8, r3
+	minutes = dt->time.min;
+     4e4:	784b      	ldrb	r3, [r1, #1]
+     4e6:	469b      	mov	fp, r3
+	seconds = dt->time.sec;
+     4e8:	780b      	ldrb	r3, [r1, #0]
+     4ea:	9301      	str	r3, [sp, #4]
+
+	/* tot up year field */
+	for (i = 0; i < year; ++i) {
+     4ec:	2500      	movs	r5, #0
+	uint32_t tmp = 0;
+     4ee:	2400      	movs	r4, #0
+	for (i = 0; i < year; ++i) {
+     4f0:	e003      	b.n	4fa <convert_datetime_to_timestamp+0x42>
+		if (leap_year(calendar->base_year + i)) {
+			tmp += SECS_IN_LEAP_YEAR;
+		} else {
+			tmp += SECS_IN_NON_LEAP_YEAR;
+     4f2:	4b1a      	ldr	r3, [pc, #104]	; (55c <convert_datetime_to_timestamp+0xa4>)
+     4f4:	469c      	mov	ip, r3
+     4f6:	4464      	add	r4, ip
+	for (i = 0; i < year; ++i) {
+     4f8:	3501      	adds	r5, #1
+     4fa:	42b5      	cmp	r5, r6
+     4fc:	d20a      	bcs.n	514 <convert_datetime_to_timestamp+0x5c>
+		if (leap_year(calendar->base_year + i)) {
+     4fe:	464b      	mov	r3, r9
+     500:	1958      	adds	r0, r3, r5
+     502:	b280      	uxth	r0, r0
+     504:	4b16      	ldr	r3, [pc, #88]	; (560 <convert_datetime_to_timestamp+0xa8>)
+     506:	4798      	blx	r3
+     508:	2800      	cmp	r0, #0
+     50a:	d0f2      	beq.n	4f2 <convert_datetime_to_timestamp+0x3a>
+			tmp += SECS_IN_LEAP_YEAR;
+     50c:	4b15      	ldr	r3, [pc, #84]	; (564 <convert_datetime_to_timestamp+0xac>)
+     50e:	469c      	mov	ip, r3
+     510:	4464      	add	r4, ip
+     512:	e7f1      	b.n	4f8 <convert_datetime_to_timestamp+0x40>
+     514:	2501      	movs	r5, #1
+     516:	e005      	b.n	524 <convert_datetime_to_timestamp+0x6c>
+		}
+	}
+
+	/* tot up month field */
+	for (i = 1; i < month; ++i) {
+		tmp += get_secs_in_month(dt->date.year, i);
+     518:	b2e9      	uxtb	r1, r5
+     51a:	9800      	ldr	r0, [sp, #0]
+     51c:	4b12      	ldr	r3, [pc, #72]	; (568 <convert_datetime_to_timestamp+0xb0>)
+     51e:	4798      	blx	r3
+     520:	1824      	adds	r4, r4, r0
+	for (i = 1; i < month; ++i) {
+     522:	3501      	adds	r5, #1
+     524:	42bd      	cmp	r5, r7
+     526:	d3f7      	bcc.n	518 <convert_datetime_to_timestamp+0x60>
+	}
+
+	/* tot up day/hour/minute/second fields */
+	tmp += (day - 1) * SECS_IN_DAY;
+     528:	4653      	mov	r3, sl
+     52a:	3b01      	subs	r3, #1
+     52c:	480f      	ldr	r0, [pc, #60]	; (56c <convert_datetime_to_timestamp+0xb4>)
+     52e:	4358      	muls	r0, r3
+     530:	1824      	adds	r4, r4, r0
+	tmp += hour * SECS_IN_HOUR;
+     532:	20e1      	movs	r0, #225	; 0xe1
+     534:	0100      	lsls	r0, r0, #4
+     536:	4643      	mov	r3, r8
+     538:	4358      	muls	r0, r3
+     53a:	1820      	adds	r0, r4, r0
+	tmp += minutes * SECS_IN_MINUTE;
+     53c:	465b      	mov	r3, fp
+     53e:	011b      	lsls	r3, r3, #4
+     540:	465a      	mov	r2, fp
+     542:	1a9b      	subs	r3, r3, r2
+     544:	009c      	lsls	r4, r3, #2
+     546:	1900      	adds	r0, r0, r4
+	tmp += seconds;
+     548:	9b01      	ldr	r3, [sp, #4]
+     54a:	469c      	mov	ip, r3
+     54c:	4460      	add	r0, ip
+
+	return tmp;
+}
+     54e:	b003      	add	sp, #12
+     550:	bc3c      	pop	{r2, r3, r4, r5}
+     552:	4690      	mov	r8, r2
+     554:	4699      	mov	r9, r3
+     556:	46a2      	mov	sl, r4
+     558:	46ab      	mov	fp, r5
+     55a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     55c:	01e13380 	.word	0x01e13380
+     560:	0000039d 	.word	0x0000039d
+     564:	01e28500 	.word	0x01e28500
+     568:	000003a9 	.word	0x000003a9
+     56c:	00015180 	.word	0x00015180
+
+00000570 <calibrate_timestamp>:
+
+/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
+ */
+static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
+                                struct calendar_alarm *current_dt)
+{
+     570:	b570      	push	{r4, r5, r6, lr}
+     572:	000c      	movs	r4, r1
+	uint32_t alarm_ts;
+	uint32_t current_ts = current_dt->cal_alarm.timestamp;
+     574:	68d0      	ldr	r0, [r2, #12]
+
+	alarm_ts = alarm->cal_alarm.timestamp;
+     576:	68cd      	ldr	r5, [r1, #12]
+
+	/* calibrate timestamp */
+	switch (alarm->cal_alarm.option) {
+     578:	7c0b      	ldrb	r3, [r1, #16]
+     57a:	2b05      	cmp	r3, #5
+     57c:	d806      	bhi.n	58c <calibrate_timestamp+0x1c>
+     57e:	009b      	lsls	r3, r3, #2
+     580:	4915      	ldr	r1, [pc, #84]	; (5d8 <calibrate_timestamp+0x68>)
+     582:	58cb      	ldr	r3, [r1, r3]
+     584:	469f      	mov	pc, r3
+	case CALENDAR_ALARM_MATCH_SEC:
+
+		if (alarm_ts <= current_ts) {
+     586:	42a8      	cmp	r0, r5
+     588:	d300      	bcc.n	58c <calibrate_timestamp+0x1c>
+			alarm_ts += SECS_IN_MINUTE;
+     58a:	353c      	adds	r5, #60	; 0x3c
+	default:
+		break;
+	}
+
+	/* desired timestamp after calibration */
+	alarm->cal_alarm.timestamp = alarm_ts;
+     58c:	60e5      	str	r5, [r4, #12]
+}
+     58e:	bd70      	pop	{r4, r5, r6, pc}
+		if (alarm_ts <= current_ts) {
+     590:	42a8      	cmp	r0, r5
+     592:	d3fb      	bcc.n	58c <calibrate_timestamp+0x1c>
+			alarm_ts += SECS_IN_HOUR;
+     594:	23e1      	movs	r3, #225	; 0xe1
+     596:	011b      	lsls	r3, r3, #4
+     598:	469c      	mov	ip, r3
+     59a:	4465      	add	r5, ip
+     59c:	e7f6      	b.n	58c <calibrate_timestamp+0x1c>
+		if (alarm_ts <= current_ts) {
+     59e:	42a8      	cmp	r0, r5
+     5a0:	d3f4      	bcc.n	58c <calibrate_timestamp+0x1c>
+			alarm_ts += SECS_IN_DAY;
+     5a2:	4b0e      	ldr	r3, [pc, #56]	; (5dc <calibrate_timestamp+0x6c>)
+     5a4:	469c      	mov	ip, r3
+     5a6:	4465      	add	r5, ip
+     5a8:	e7f0      	b.n	58c <calibrate_timestamp+0x1c>
+		if (alarm_ts <= current_ts) {
+     5aa:	42a8      	cmp	r0, r5
+     5ac:	d3ee      	bcc.n	58c <calibrate_timestamp+0x1c>
+			alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
+     5ae:	8950      	ldrh	r0, [r2, #10]
+     5b0:	7a51      	ldrb	r1, [r2, #9]
+     5b2:	4b0b      	ldr	r3, [pc, #44]	; (5e0 <calibrate_timestamp+0x70>)
+     5b4:	4798      	blx	r3
+     5b6:	182d      	adds	r5, r5, r0
+     5b8:	e7e8      	b.n	58c <calibrate_timestamp+0x1c>
+		if (alarm_ts <= current_ts) {
+     5ba:	42a8      	cmp	r0, r5
+     5bc:	d3e6      	bcc.n	58c <calibrate_timestamp+0x1c>
+			if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
+     5be:	8950      	ldrh	r0, [r2, #10]
+     5c0:	4b08      	ldr	r3, [pc, #32]	; (5e4 <calibrate_timestamp+0x74>)
+     5c2:	4798      	blx	r3
+     5c4:	2800      	cmp	r0, #0
+     5c6:	d103      	bne.n	5d0 <calibrate_timestamp+0x60>
+				alarm_ts += SECS_IN_NON_LEAP_YEAR;
+     5c8:	4b07      	ldr	r3, [pc, #28]	; (5e8 <calibrate_timestamp+0x78>)
+     5ca:	469c      	mov	ip, r3
+     5cc:	4465      	add	r5, ip
+     5ce:	e7dd      	b.n	58c <calibrate_timestamp+0x1c>
+				alarm_ts += SECS_IN_LEAP_YEAR;
+     5d0:	4b06      	ldr	r3, [pc, #24]	; (5ec <calibrate_timestamp+0x7c>)
+     5d2:	469c      	mov	ip, r3
+     5d4:	4465      	add	r5, ip
+     5d6:	e7d9      	b.n	58c <calibrate_timestamp+0x1c>
+     5d8:	00001f60 	.word	0x00001f60
+     5dc:	00015180 	.word	0x00015180
+     5e0:	000003a9 	.word	0x000003a9
+     5e4:	0000039d 	.word	0x0000039d
+     5e8:	01e13380 	.word	0x01e13380
+     5ec:	01e28500 	.word	0x01e28500
+
+000005f0 <fill_alarm>:
+
+/** \brief complete alarm to absolute date/time, then fill up the timestamp
+ */
+static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
+{
+     5f0:	b570      	push	{r4, r5, r6, lr}
+     5f2:	b086      	sub	sp, #24
+     5f4:	0005      	movs	r5, r0
+     5f6:	000c      	movs	r4, r1
+	struct calendar_alarm current_dt;
+	uint32_t              tmp, current_ts;
+
+	/* get current date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+     5f8:	4b29      	ldr	r3, [pc, #164]	; (6a0 <fill_alarm+0xb0>)
+     5fa:	4798      	blx	r3
+     5fc:	0006      	movs	r6, r0
+	convert_timestamp_to_datetime(calendar, current_ts, &current_dt.cal_alarm.datetime);
+     5fe:	aa01      	add	r2, sp, #4
+     600:	0001      	movs	r1, r0
+     602:	0028      	movs	r0, r5
+     604:	4b27      	ldr	r3, [pc, #156]	; (6a4 <fill_alarm+0xb4>)
+     606:	4798      	blx	r3
+
+	current_dt.cal_alarm.timestamp = current_ts;
+     608:	9603      	str	r6, [sp, #12]
+
+	/* complete alarm */
+	switch (alarm->cal_alarm.option) {
+     60a:	7c23      	ldrb	r3, [r4, #16]
+     60c:	2b05      	cmp	r3, #5
+     60e:	d812      	bhi.n	636 <fill_alarm+0x46>
+     610:	009b      	lsls	r3, r3, #2
+     612:	4a25      	ldr	r2, [pc, #148]	; (6a8 <fill_alarm+0xb8>)
+     614:	58d3      	ldr	r3, [r2, r3]
+     616:	469f      	mov	pc, r3
+	case CALENDAR_ALARM_MATCH_SEC:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+     618:	466b      	mov	r3, sp
+     61a:	895b      	ldrh	r3, [r3, #10]
+     61c:	8163      	strh	r3, [r4, #10]
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+     61e:	466b      	mov	r3, sp
+     620:	7a5b      	ldrb	r3, [r3, #9]
+     622:	7263      	strb	r3, [r4, #9]
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+     624:	466b      	mov	r3, sp
+     626:	7a1b      	ldrb	r3, [r3, #8]
+     628:	7223      	strb	r3, [r4, #8]
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+     62a:	466b      	mov	r3, sp
+     62c:	799b      	ldrb	r3, [r3, #6]
+     62e:	71a3      	strb	r3, [r4, #6]
+		alarm->cal_alarm.datetime.time.min   = current_dt.cal_alarm.datetime.time.min;
+     630:	466b      	mov	r3, sp
+     632:	795b      	ldrb	r3, [r3, #5]
+     634:	7163      	strb	r3, [r4, #5]
+	default:
+		break;
+	}
+
+	/* fill up the timestamp */
+	tmp                        = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
+     636:	1d26      	adds	r6, r4, #4
+     638:	0031      	movs	r1, r6
+     63a:	0028      	movs	r0, r5
+     63c:	4b1b      	ldr	r3, [pc, #108]	; (6ac <fill_alarm+0xbc>)
+     63e:	4798      	blx	r3
+	alarm->cal_alarm.timestamp = tmp;
+     640:	60e0      	str	r0, [r4, #12]
+
+	/* calibrate the timestamp */
+	calibrate_timestamp(calendar, alarm, &current_dt);
+     642:	466a      	mov	r2, sp
+     644:	0021      	movs	r1, r4
+     646:	0028      	movs	r0, r5
+     648:	4b19      	ldr	r3, [pc, #100]	; (6b0 <fill_alarm+0xc0>)
+     64a:	4798      	blx	r3
+	convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
+     64c:	68e1      	ldr	r1, [r4, #12]
+     64e:	0032      	movs	r2, r6
+     650:	0028      	movs	r0, r5
+     652:	4b14      	ldr	r3, [pc, #80]	; (6a4 <fill_alarm+0xb4>)
+     654:	4798      	blx	r3
+}
+     656:	b006      	add	sp, #24
+     658:	bd70      	pop	{r4, r5, r6, pc}
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+     65a:	466b      	mov	r3, sp
+     65c:	895b      	ldrh	r3, [r3, #10]
+     65e:	8163      	strh	r3, [r4, #10]
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+     660:	466b      	mov	r3, sp
+     662:	7a5b      	ldrb	r3, [r3, #9]
+     664:	7263      	strb	r3, [r4, #9]
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+     666:	466b      	mov	r3, sp
+     668:	7a1b      	ldrb	r3, [r3, #8]
+     66a:	7223      	strb	r3, [r4, #8]
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+     66c:	466b      	mov	r3, sp
+     66e:	799b      	ldrb	r3, [r3, #6]
+     670:	71a3      	strb	r3, [r4, #6]
+		break;
+     672:	e7e0      	b.n	636 <fill_alarm+0x46>
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+     674:	466b      	mov	r3, sp
+     676:	895b      	ldrh	r3, [r3, #10]
+     678:	8163      	strh	r3, [r4, #10]
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+     67a:	466b      	mov	r3, sp
+     67c:	7a5b      	ldrb	r3, [r3, #9]
+     67e:	7263      	strb	r3, [r4, #9]
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+     680:	466b      	mov	r3, sp
+     682:	7a1b      	ldrb	r3, [r3, #8]
+     684:	7223      	strb	r3, [r4, #8]
+		break;
+     686:	e7d6      	b.n	636 <fill_alarm+0x46>
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+     688:	466b      	mov	r3, sp
+     68a:	895b      	ldrh	r3, [r3, #10]
+     68c:	8163      	strh	r3, [r4, #10]
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+     68e:	466b      	mov	r3, sp
+     690:	7a5b      	ldrb	r3, [r3, #9]
+     692:	7263      	strb	r3, [r4, #9]
+		break;
+     694:	e7cf      	b.n	636 <fill_alarm+0x46>
+		alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+     696:	466b      	mov	r3, sp
+     698:	895b      	ldrh	r3, [r3, #10]
+     69a:	8163      	strh	r3, [r4, #10]
+		break;
+     69c:	e7cb      	b.n	636 <fill_alarm+0x46>
+     69e:	46c0      	nop			; (mov r8, r8)
+     6a0:	00000e55 	.word	0x00000e55
+     6a4:	0000040d 	.word	0x0000040d
+     6a8:	00001f78 	.word	0x00001f78
+     6ac:	000004b9 	.word	0x000004b9
+     6b0:	00000571 	.word	0x00000571
+
+000006b4 <calendar_init>:
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+     6b4:	b570      	push	{r4, r5, r6, lr}
+     6b6:	0004      	movs	r4, r0
+     6b8:	000d      	movs	r5, r1
+	int32_t ret = 0;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     6ba:	1e43      	subs	r3, r0, #1
+     6bc:	4198      	sbcs	r0, r3
+     6be:	b2c0      	uxtb	r0, r0
+     6c0:	22e0      	movs	r2, #224	; 0xe0
+     6c2:	0052      	lsls	r2, r2, #1
+     6c4:	4909      	ldr	r1, [pc, #36]	; (6ec <calendar_init+0x38>)
+     6c6:	4b0a      	ldr	r3, [pc, #40]	; (6f0 <calendar_init+0x3c>)
+     6c8:	4798      	blx	r3
+
+	if (calendar->device.hw == hw) {
+     6ca:	6823      	ldr	r3, [r4, #0]
+     6cc:	42ab      	cmp	r3, r5
+     6ce:	d008      	beq.n	6e2 <calendar_init+0x2e>
+		/* Already initialized with current configuration */
+		return ERR_NONE;
+	} else if (calendar->device.hw != NULL) {
+     6d0:	2b00      	cmp	r3, #0
+     6d2:	d108      	bne.n	6e6 <calendar_init+0x32>
+		/* Initialized with another configuration */
+		return ERR_ALREADY_INITIALIZED;
+	}
+	calendar->device.hw = (void *)hw;
+     6d4:	6025      	str	r5, [r4, #0]
+	ret                 = _calendar_init(&calendar->device);
+     6d6:	0020      	movs	r0, r4
+     6d8:	4b06      	ldr	r3, [pc, #24]	; (6f4 <calendar_init+0x40>)
+     6da:	4798      	blx	r3
+	calendar->base_year = DEFAULT_BASE_YEAR;
+     6dc:	4b06      	ldr	r3, [pc, #24]	; (6f8 <calendar_init+0x44>)
+     6de:	61a3      	str	r3, [r4, #24]
+
+	return ret;
+}
+     6e0:	bd70      	pop	{r4, r5, r6, pc}
+		return ERR_NONE;
+     6e2:	2000      	movs	r0, #0
+     6e4:	e7fc      	b.n	6e0 <calendar_init+0x2c>
+		return ERR_ALREADY_INITIALIZED;
+     6e6:	2012      	movs	r0, #18
+     6e8:	4240      	negs	r0, r0
+     6ea:	e7f9      	b.n	6e0 <calendar_init+0x2c>
+     6ec:	00001f90 	.word	0x00001f90
+     6f0:	00000a69 	.word	0x00000a69
+     6f4:	00000d49 	.word	0x00000d49
+     6f8:	000007b2 	.word	0x000007b2
+
+000006fc <calendar_enable>:
+}
+
+/** \brief Enable the Calendar
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar)
+{
+     6fc:	b510      	push	{r4, lr}
+     6fe:	0004      	movs	r4, r0
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     700:	1e43      	subs	r3, r0, #1
+     702:	4198      	sbcs	r0, r3
+     704:	b2c0      	uxtb	r0, r0
+     706:	22e6      	movs	r2, #230	; 0xe6
+     708:	32ff      	adds	r2, #255	; 0xff
+     70a:	4904      	ldr	r1, [pc, #16]	; (71c <calendar_enable+0x20>)
+     70c:	4b04      	ldr	r3, [pc, #16]	; (720 <calendar_enable+0x24>)
+     70e:	4798      	blx	r3
+
+	_calendar_enable(&calendar->device);
+     710:	0020      	movs	r0, r4
+     712:	4b04      	ldr	r3, [pc, #16]	; (724 <calendar_enable+0x28>)
+     714:	4798      	blx	r3
+
+	return ERR_NONE;
+}
+     716:	2000      	movs	r0, #0
+     718:	bd10      	pop	{r4, pc}
+     71a:	46c0      	nop			; (mov r8, r8)
+     71c:	00001f90 	.word	0x00001f90
+     720:	00000a69 	.word	0x00000a69
+     724:	00000dd9 	.word	0x00000dd9
+
+00000728 <calendar_set_time>:
+}
+
+/** \brief Set time for calendar
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
+{
+     728:	b530      	push	{r4, r5, lr}
+     72a:	b083      	sub	sp, #12
+     72c:	0004      	movs	r4, r0
+     72e:	000d      	movs	r5, r1
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     730:	1e43      	subs	r3, r0, #1
+     732:	4198      	sbcs	r0, r3
+     734:	b2c0      	uxtb	r0, r0
+     736:	2283      	movs	r2, #131	; 0x83
+     738:	0092      	lsls	r2, r2, #2
+     73a:	490e      	ldr	r1, [pc, #56]	; (774 <calendar_set_time+0x4c>)
+     73c:	4b0e      	ldr	r3, [pc, #56]	; (778 <calendar_set_time+0x50>)
+     73e:	4798      	blx	r3
+
+	/* convert time to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+     740:	0020      	movs	r0, r4
+     742:	4b0e      	ldr	r3, [pc, #56]	; (77c <calendar_set_time+0x54>)
+     744:	4798      	blx	r3
+     746:	0001      	movs	r1, r0
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+     748:	466a      	mov	r2, sp
+     74a:	0020      	movs	r0, r4
+     74c:	4b0c      	ldr	r3, [pc, #48]	; (780 <calendar_set_time+0x58>)
+     74e:	4798      	blx	r3
+	dt.time.sec  = p_calendar_time->sec;
+     750:	782b      	ldrb	r3, [r5, #0]
+     752:	466a      	mov	r2, sp
+     754:	7013      	strb	r3, [r2, #0]
+	dt.time.min  = p_calendar_time->min;
+     756:	786b      	ldrb	r3, [r5, #1]
+     758:	7053      	strb	r3, [r2, #1]
+	dt.time.hour = p_calendar_time->hour;
+     75a:	78ab      	ldrb	r3, [r5, #2]
+     75c:	7093      	strb	r3, [r2, #2]
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+     75e:	4669      	mov	r1, sp
+     760:	0020      	movs	r0, r4
+     762:	4b08      	ldr	r3, [pc, #32]	; (784 <calendar_set_time+0x5c>)
+     764:	4798      	blx	r3
+     766:	0001      	movs	r1, r0
+
+	_calendar_set_counter(&calendar->device, new_ts);
+     768:	0020      	movs	r0, r4
+     76a:	4b07      	ldr	r3, [pc, #28]	; (788 <calendar_set_time+0x60>)
+     76c:	4798      	blx	r3
+
+	return ERR_NONE;
+}
+     76e:	2000      	movs	r0, #0
+     770:	b003      	add	sp, #12
+     772:	bd30      	pop	{r4, r5, pc}
+     774:	00001f90 	.word	0x00001f90
+     778:	00000a69 	.word	0x00000a69
+     77c:	00000e55 	.word	0x00000e55
+     780:	0000040d 	.word	0x0000040d
+     784:	000004b9 	.word	0x000004b9
+     788:	00000e1d 	.word	0x00000e1d
+
+0000078c <calendar_set_date>:
+
+/** \brief Set date for calendar
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
+{
+     78c:	b530      	push	{r4, r5, lr}
+     78e:	b083      	sub	sp, #12
+     790:	0004      	movs	r4, r0
+     792:	000d      	movs	r5, r1
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     794:	1e43      	subs	r3, r0, #1
+     796:	4198      	sbcs	r0, r3
+     798:	b2c0      	uxtb	r0, r0
+     79a:	2289      	movs	r2, #137	; 0x89
+     79c:	0092      	lsls	r2, r2, #2
+     79e:	490e      	ldr	r1, [pc, #56]	; (7d8 <calendar_set_date+0x4c>)
+     7a0:	4b0e      	ldr	r3, [pc, #56]	; (7dc <calendar_set_date+0x50>)
+     7a2:	4798      	blx	r3
+
+	/* convert date to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+     7a4:	0020      	movs	r0, r4
+     7a6:	4b0e      	ldr	r3, [pc, #56]	; (7e0 <calendar_set_date+0x54>)
+     7a8:	4798      	blx	r3
+     7aa:	0001      	movs	r1, r0
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+     7ac:	466a      	mov	r2, sp
+     7ae:	0020      	movs	r0, r4
+     7b0:	4b0c      	ldr	r3, [pc, #48]	; (7e4 <calendar_set_date+0x58>)
+     7b2:	4798      	blx	r3
+	dt.date.day   = p_calendar_date->day;
+     7b4:	782b      	ldrb	r3, [r5, #0]
+     7b6:	466a      	mov	r2, sp
+     7b8:	7113      	strb	r3, [r2, #4]
+	dt.date.month = p_calendar_date->month;
+     7ba:	786b      	ldrb	r3, [r5, #1]
+     7bc:	7153      	strb	r3, [r2, #5]
+	dt.date.year  = p_calendar_date->year;
+     7be:	886b      	ldrh	r3, [r5, #2]
+     7c0:	80d3      	strh	r3, [r2, #6]
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+     7c2:	4669      	mov	r1, sp
+     7c4:	0020      	movs	r0, r4
+     7c6:	4b08      	ldr	r3, [pc, #32]	; (7e8 <calendar_set_date+0x5c>)
+     7c8:	4798      	blx	r3
+     7ca:	0001      	movs	r1, r0
+
+	_calendar_set_counter(&calendar->device, new_ts);
+     7cc:	0020      	movs	r0, r4
+     7ce:	4b07      	ldr	r3, [pc, #28]	; (7ec <calendar_set_date+0x60>)
+     7d0:	4798      	blx	r3
+
+	return ERR_NONE;
+}
+     7d2:	2000      	movs	r0, #0
+     7d4:	b003      	add	sp, #12
+     7d6:	bd30      	pop	{r4, r5, pc}
+     7d8:	00001f90 	.word	0x00001f90
+     7dc:	00000a69 	.word	0x00000a69
+     7e0:	00000e55 	.word	0x00000e55
+     7e4:	0000040d 	.word	0x0000040d
+     7e8:	000004b9 	.word	0x000004b9
+     7ec:	00000e1d 	.word	0x00000e1d
+
+000007f0 <calendar_get_date_time>:
+
+/** \brief Get date/time for calendar
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time)
+{
+     7f0:	b570      	push	{r4, r5, r6, lr}
+     7f2:	0004      	movs	r4, r0
+     7f4:	000d      	movs	r5, r1
+	uint32_t current_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+     7f6:	1e43      	subs	r3, r0, #1
+     7f8:	4198      	sbcs	r0, r3
+     7fa:	b2c0      	uxtb	r0, r0
+     7fc:	4a06      	ldr	r2, [pc, #24]	; (818 <calendar_get_date_time+0x28>)
+     7fe:	4907      	ldr	r1, [pc, #28]	; (81c <calendar_get_date_time+0x2c>)
+     800:	4b07      	ldr	r3, [pc, #28]	; (820 <calendar_get_date_time+0x30>)
+     802:	4798      	blx	r3
+
+	/* convert current timestamp to date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+     804:	0020      	movs	r0, r4
+     806:	4b07      	ldr	r3, [pc, #28]	; (824 <calendar_get_date_time+0x34>)
+     808:	4798      	blx	r3
+     80a:	0001      	movs	r1, r0
+	convert_timestamp_to_datetime(calendar, current_ts, date_time);
+     80c:	002a      	movs	r2, r5
+     80e:	0020      	movs	r0, r4
+     810:	4b05      	ldr	r3, [pc, #20]	; (828 <calendar_get_date_time+0x38>)
+     812:	4798      	blx	r3
+
+	return ERR_NONE;
+}
+     814:	2000      	movs	r0, #0
+     816:	bd70      	pop	{r4, r5, r6, pc}
+     818:	0000023b 	.word	0x0000023b
+     81c:	00001f90 	.word	0x00001f90
+     820:	00000a69 	.word	0x00000a69
+     824:	00000e55 	.word	0x00000e55
+     828:	0000040d 	.word	0x0000040d
+
+0000082c <delay_init>:
+
+/**
+ * \brief Initialize Delay driver
+ */
+void delay_init(void *const hw)
+{
+     82c:	b510      	push	{r4, lr}
+	_delay_init(hardware = hw);
+     82e:	4b02      	ldr	r3, [pc, #8]	; (838 <delay_init+0xc>)
+     830:	6018      	str	r0, [r3, #0]
+     832:	4b02      	ldr	r3, [pc, #8]	; (83c <delay_init+0x10>)
+     834:	4798      	blx	r3
+}
+     836:	bd10      	pop	{r4, pc}
+     838:	20000054 	.word	0x20000054
+     83c:	00001571 	.word	0x00001571
+
+00000840 <i2c_m_sync_write>:
+
+/**
+ * \brief Sync version of I2C I/O write
+ */
+static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
+{
+     840:	b510      	push	{r4, lr}
+     842:	b084      	sub	sp, #16
+	struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+	struct _i2c_m_msg       msg;
+	int32_t                 ret;
+
+	msg.addr   = i2c->slave_addr;
+     844:	3814      	subs	r0, #20
+     846:	8b84      	ldrh	r4, [r0, #28]
+     848:	ab01      	add	r3, sp, #4
+     84a:	801c      	strh	r4, [r3, #0]
+	msg.len    = n;
+     84c:	0014      	movs	r4, r2
+     84e:	9202      	str	r2, [sp, #8]
+	msg.flags  = I2C_M_STOP;
+     850:	4a06      	ldr	r2, [pc, #24]	; (86c <i2c_m_sync_write+0x2c>)
+     852:	805a      	strh	r2, [r3, #2]
+	msg.buffer = (uint8_t *)buf;
+     854:	9103      	str	r1, [sp, #12]
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+     856:	0019      	movs	r1, r3
+     858:	4b05      	ldr	r3, [pc, #20]	; (870 <i2c_m_sync_write+0x30>)
+     85a:	4798      	blx	r3
+
+	if (ret) {
+     85c:	2800      	cmp	r0, #0
+     85e:	d102      	bne.n	866 <i2c_m_sync_write+0x26>
+		return ret;
+	}
+
+	return n;
+}
+     860:	0020      	movs	r0, r4
+     862:	b004      	add	sp, #16
+     864:	bd10      	pop	{r4, pc}
+		return ret;
+     866:	0004      	movs	r4, r0
+     868:	e7fa      	b.n	860 <i2c_m_sync_write+0x20>
+     86a:	46c0      	nop			; (mov r8, r8)
+     86c:	ffff8000 	.word	0xffff8000
+     870:	000012e1 	.word	0x000012e1
+
+00000874 <i2c_m_sync_read>:
+{
+     874:	b510      	push	{r4, lr}
+     876:	b084      	sub	sp, #16
+	msg.addr   = i2c->slave_addr;
+     878:	3814      	subs	r0, #20
+     87a:	8b84      	ldrh	r4, [r0, #28]
+     87c:	ab01      	add	r3, sp, #4
+     87e:	801c      	strh	r4, [r3, #0]
+	msg.len    = n;
+     880:	0014      	movs	r4, r2
+     882:	9202      	str	r2, [sp, #8]
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+     884:	4a06      	ldr	r2, [pc, #24]	; (8a0 <i2c_m_sync_read+0x2c>)
+     886:	805a      	strh	r2, [r3, #2]
+	msg.buffer = buf;
+     888:	9103      	str	r1, [sp, #12]
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+     88a:	0019      	movs	r1, r3
+     88c:	4b05      	ldr	r3, [pc, #20]	; (8a4 <i2c_m_sync_read+0x30>)
+     88e:	4798      	blx	r3
+	if (ret) {
+     890:	2800      	cmp	r0, #0
+     892:	d102      	bne.n	89a <i2c_m_sync_read+0x26>
+}
+     894:	0020      	movs	r0, r4
+     896:	b004      	add	sp, #16
+     898:	bd10      	pop	{r4, pc}
+		return ret;
+     89a:	0004      	movs	r4, r0
+     89c:	e7fa      	b.n	894 <i2c_m_sync_read+0x20>
+     89e:	46c0      	nop			; (mov r8, r8)
+     8a0:	ffff8001 	.word	0xffff8001
+     8a4:	000012e1 	.word	0x000012e1
+
+000008a8 <i2c_m_sync_init>:
+
+/**
+ * \brief Sync version of i2c initialize
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
+{
+     8a8:	b570      	push	{r4, r5, r6, lr}
+     8aa:	0004      	movs	r4, r0
+     8ac:	000d      	movs	r5, r1
+	int32_t init_status;
+	ASSERT(i2c);
+     8ae:	1e43      	subs	r3, r0, #1
+     8b0:	4198      	sbcs	r0, r3
+     8b2:	b2c0      	uxtb	r0, r0
+     8b4:	225e      	movs	r2, #94	; 0x5e
+     8b6:	4907      	ldr	r1, [pc, #28]	; (8d4 <i2c_m_sync_init+0x2c>)
+     8b8:	4b07      	ldr	r3, [pc, #28]	; (8d8 <i2c_m_sync_init+0x30>)
+     8ba:	4798      	blx	r3
+
+	init_status = _i2c_m_sync_init(&i2c->device, hw);
+     8bc:	0029      	movs	r1, r5
+     8be:	0020      	movs	r0, r4
+     8c0:	4b06      	ldr	r3, [pc, #24]	; (8dc <i2c_m_sync_init+0x34>)
+     8c2:	4798      	blx	r3
+	if (init_status) {
+     8c4:	2800      	cmp	r0, #0
+     8c6:	d103      	bne.n	8d0 <i2c_m_sync_init+0x28>
+		return init_status;
+	}
+
+	/* Init I/O */
+	i2c->io.read  = i2c_m_sync_read;
+     8c8:	4b05      	ldr	r3, [pc, #20]	; (8e0 <i2c_m_sync_init+0x38>)
+     8ca:	61a3      	str	r3, [r4, #24]
+	i2c->io.write = i2c_m_sync_write;
+     8cc:	4b05      	ldr	r3, [pc, #20]	; (8e4 <i2c_m_sync_init+0x3c>)
+     8ce:	6163      	str	r3, [r4, #20]
+
+	return ERR_NONE;
+}
+     8d0:	bd70      	pop	{r4, r5, r6, pc}
+     8d2:	46c0      	nop			; (mov r8, r8)
+     8d4:	00001fac 	.word	0x00001fac
+     8d8:	00000a69 	.word	0x00000a69
+     8dc:	00001231 	.word	0x00001231
+     8e0:	00000875 	.word	0x00000875
+     8e4:	00000841 	.word	0x00000841
+
+000008e8 <i2c_m_sync_enable>:
+
+/**
+ * \brief Sync version of i2c enable
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
+{
+     8e8:	b510      	push	{r4, lr}
+	return _i2c_m_sync_enable(&i2c->device);
+     8ea:	4b01      	ldr	r3, [pc, #4]	; (8f0 <i2c_m_sync_enable+0x8>)
+     8ec:	4798      	blx	r3
+}
+     8ee:	bd10      	pop	{r4, pc}
+     8f0:	00001261 	.word	0x00001261
+
+000008f4 <i2c_m_sync_set_slaveaddr>:
+/**
+ * \brief Sync version of i2c set slave address
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
+{
+	return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
+     8f4:	0589      	lsls	r1, r1, #22
+     8f6:	0d89      	lsrs	r1, r1, #22
+     8f8:	2380      	movs	r3, #128	; 0x80
+     8fa:	00db      	lsls	r3, r3, #3
+     8fc:	401a      	ands	r2, r3
+     8fe:	430a      	orrs	r2, r1
+     900:	8382      	strh	r2, [r0, #28]
+}
+     902:	0010      	movs	r0, r2
+     904:	4770      	bx	lr
+
+00000906 <i2c_m_sync_get_io_descriptor>:
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
+{
+	*io = &i2c->io;
+     906:	3014      	adds	r0, #20
+     908:	6008      	str	r0, [r1, #0]
+	return ERR_NONE;
+}
+     90a:	2000      	movs	r0, #0
+     90c:	4770      	bx	lr
+	...
+
+00000910 <io_write>:
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+     910:	b570      	push	{r4, r5, r6, lr}
+     912:	0004      	movs	r4, r0
+     914:	000d      	movs	r5, r1
+     916:	0016      	movs	r6, r2
+	ASSERT(io_descr && buf);
+     918:	2800      	cmp	r0, #0
+     91a:	d00e      	beq.n	93a <io_write+0x2a>
+     91c:	2900      	cmp	r1, #0
+     91e:	d00a      	beq.n	936 <io_write+0x26>
+     920:	2001      	movs	r0, #1
+     922:	2234      	movs	r2, #52	; 0x34
+     924:	4906      	ldr	r1, [pc, #24]	; (940 <io_write+0x30>)
+     926:	4b07      	ldr	r3, [pc, #28]	; (944 <io_write+0x34>)
+     928:	4798      	blx	r3
+	return io_descr->write(io_descr, buf, length);
+     92a:	6823      	ldr	r3, [r4, #0]
+     92c:	0032      	movs	r2, r6
+     92e:	0029      	movs	r1, r5
+     930:	0020      	movs	r0, r4
+     932:	4798      	blx	r3
+}
+     934:	bd70      	pop	{r4, r5, r6, pc}
+	ASSERT(io_descr && buf);
+     936:	2000      	movs	r0, #0
+     938:	e7f3      	b.n	922 <io_write+0x12>
+     93a:	2000      	movs	r0, #0
+     93c:	e7f1      	b.n	922 <io_write+0x12>
+     93e:	46c0      	nop			; (mov r8, r8)
+     940:	00001fc8 	.word	0x00001fc8
+     944:	00000a69 	.word	0x00000a69
+
+00000948 <io_read>:
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+     948:	b570      	push	{r4, r5, r6, lr}
+     94a:	0004      	movs	r4, r0
+     94c:	000d      	movs	r5, r1
+     94e:	0016      	movs	r6, r2
+	ASSERT(io_descr && buf);
+     950:	2800      	cmp	r0, #0
+     952:	d00e      	beq.n	972 <io_read+0x2a>
+     954:	2900      	cmp	r1, #0
+     956:	d00a      	beq.n	96e <io_read+0x26>
+     958:	2001      	movs	r0, #1
+     95a:	223d      	movs	r2, #61	; 0x3d
+     95c:	4906      	ldr	r1, [pc, #24]	; (978 <io_read+0x30>)
+     95e:	4b07      	ldr	r3, [pc, #28]	; (97c <io_read+0x34>)
+     960:	4798      	blx	r3
+	return io_descr->read(io_descr, buf, length);
+     962:	6863      	ldr	r3, [r4, #4]
+     964:	0032      	movs	r2, r6
+     966:	0029      	movs	r1, r5
+     968:	0020      	movs	r0, r4
+     96a:	4798      	blx	r3
+}
+     96c:	bd70      	pop	{r4, r5, r6, pc}
+	ASSERT(io_descr && buf);
+     96e:	2000      	movs	r0, #0
+     970:	e7f3      	b.n	95a <io_read+0x12>
+     972:	2000      	movs	r0, #0
+     974:	e7f1      	b.n	95a <io_read+0x12>
+     976:	46c0      	nop			; (mov r8, r8)
+     978:	00001fc8 	.word	0x00001fc8
+     97c:	00000a69 	.word	0x00000a69
+
+00000980 <pwm_period_expired>:
+
+/**
+ * \internal Process interrupts caused by period experied
+ */
+static void pwm_period_expired(struct _pwm_device *device)
+{
+     980:	b510      	push	{r4, lr}
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.period) {
+     982:	6943      	ldr	r3, [r0, #20]
+     984:	2b00      	cmp	r3, #0
+     986:	d000      	beq.n	98a <pwm_period_expired+0xa>
+		descr->pwm_cb.period(descr);
+     988:	4798      	blx	r3
+	}
+}
+     98a:	bd10      	pop	{r4, pc}
+
+0000098c <pwm_detect_fault>:
+
+/**
+ * \internal Process interrupts caused by pwm fault
+ */
+static void pwm_detect_fault(struct _pwm_device *device)
+{
+     98c:	b510      	push	{r4, lr}
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.error) {
+     98e:	6983      	ldr	r3, [r0, #24]
+     990:	2b00      	cmp	r3, #0
+     992:	d000      	beq.n	996 <pwm_detect_fault+0xa>
+		descr->pwm_cb.error(descr);
+     994:	4798      	blx	r3
+	}
+}
+     996:	bd10      	pop	{r4, pc}
+
+00000998 <pwm_init>:
+{
+     998:	b570      	push	{r4, r5, r6, lr}
+     99a:	0004      	movs	r4, r0
+     99c:	000d      	movs	r5, r1
+     99e:	0016      	movs	r6, r2
+	ASSERT(descr && hw && func);
+     9a0:	2800      	cmp	r0, #0
+     9a2:	d015      	beq.n	9d0 <pwm_init+0x38>
+     9a4:	2900      	cmp	r1, #0
+     9a6:	d015      	beq.n	9d4 <pwm_init+0x3c>
+     9a8:	2a00      	cmp	r2, #0
+     9aa:	d00f      	beq.n	9cc <pwm_init+0x34>
+     9ac:	2001      	movs	r0, #1
+     9ae:	2233      	movs	r2, #51	; 0x33
+     9b0:	4909      	ldr	r1, [pc, #36]	; (9d8 <pwm_init+0x40>)
+     9b2:	4b0a      	ldr	r3, [pc, #40]	; (9dc <pwm_init+0x44>)
+     9b4:	4798      	blx	r3
+	descr->func = func;
+     9b6:	61e6      	str	r6, [r4, #28]
+	descr->func->init(&descr->device, hw);
+     9b8:	6833      	ldr	r3, [r6, #0]
+     9ba:	0029      	movs	r1, r5
+     9bc:	0020      	movs	r0, r4
+     9be:	4798      	blx	r3
+	descr->device.callback.pwm_period_cb = pwm_period_expired;
+     9c0:	4b07      	ldr	r3, [pc, #28]	; (9e0 <pwm_init+0x48>)
+     9c2:	6023      	str	r3, [r4, #0]
+	descr->device.callback.pwm_error_cb  = pwm_detect_fault;
+     9c4:	4b07      	ldr	r3, [pc, #28]	; (9e4 <pwm_init+0x4c>)
+     9c6:	6063      	str	r3, [r4, #4]
+}
+     9c8:	2000      	movs	r0, #0
+     9ca:	bd70      	pop	{r4, r5, r6, pc}
+	ASSERT(descr && hw && func);
+     9cc:	2000      	movs	r0, #0
+     9ce:	e7ee      	b.n	9ae <pwm_init+0x16>
+     9d0:	2000      	movs	r0, #0
+     9d2:	e7ec      	b.n	9ae <pwm_init+0x16>
+     9d4:	2000      	movs	r0, #0
+     9d6:	e7ea      	b.n	9ae <pwm_init+0x16>
+     9d8:	00001fdc 	.word	0x00001fdc
+     9dc:	00000a69 	.word	0x00000a69
+     9e0:	00000981 	.word	0x00000981
+     9e4:	0000098d 	.word	0x0000098d
+
+000009e8 <pwm_enable>:
+{
+     9e8:	b510      	push	{r4, lr}
+     9ea:	1e04      	subs	r4, r0, #0
+	ASSERT(descr && descr->func);
+     9ec:	d015      	beq.n	a1a <pwm_enable+0x32>
+     9ee:	69c3      	ldr	r3, [r0, #28]
+     9f0:	2b00      	cmp	r3, #0
+     9f2:	d010      	beq.n	a16 <pwm_enable+0x2e>
+     9f4:	2001      	movs	r0, #1
+     9f6:	224b      	movs	r2, #75	; 0x4b
+     9f8:	490a      	ldr	r1, [pc, #40]	; (a24 <pwm_enable+0x3c>)
+     9fa:	4b0b      	ldr	r3, [pc, #44]	; (a28 <pwm_enable+0x40>)
+     9fc:	4798      	blx	r3
+	if (descr->func->is_pwm_enabled(&descr->device)) {
+     9fe:	69e3      	ldr	r3, [r4, #28]
+     a00:	695b      	ldr	r3, [r3, #20]
+     a02:	0020      	movs	r0, r4
+     a04:	4798      	blx	r3
+     a06:	2800      	cmp	r0, #0
+     a08:	d109      	bne.n	a1e <pwm_enable+0x36>
+	descr->func->start_pwm(&descr->device);
+     a0a:	69e3      	ldr	r3, [r4, #28]
+     a0c:	689b      	ldr	r3, [r3, #8]
+     a0e:	0020      	movs	r0, r4
+     a10:	4798      	blx	r3
+	return ERR_NONE;
+     a12:	2000      	movs	r0, #0
+}
+     a14:	bd10      	pop	{r4, pc}
+	ASSERT(descr && descr->func);
+     a16:	2000      	movs	r0, #0
+     a18:	e7ed      	b.n	9f6 <pwm_enable+0xe>
+     a1a:	2000      	movs	r0, #0
+     a1c:	e7eb      	b.n	9f6 <pwm_enable+0xe>
+		return ERR_DENIED;
+     a1e:	2011      	movs	r0, #17
+     a20:	4240      	negs	r0, r0
+     a22:	e7f7      	b.n	a14 <pwm_enable+0x2c>
+     a24:	00001fdc 	.word	0x00001fdc
+     a28:	00000a69 	.word	0x00000a69
+
+00000a2c <pwm_set_parameters>:
+{
+     a2c:	b570      	push	{r4, r5, r6, lr}
+     a2e:	0004      	movs	r4, r0
+     a30:	000d      	movs	r5, r1
+     a32:	0016      	movs	r6, r2
+	ASSERT(descr && descr->func);
+     a34:	2800      	cmp	r0, #0
+     a36:	d011      	beq.n	a5c <pwm_set_parameters+0x30>
+     a38:	69c3      	ldr	r3, [r0, #28]
+     a3a:	2b00      	cmp	r3, #0
+     a3c:	d00c      	beq.n	a58 <pwm_set_parameters+0x2c>
+     a3e:	2001      	movs	r0, #1
+     a40:	227d      	movs	r2, #125	; 0x7d
+     a42:	4907      	ldr	r1, [pc, #28]	; (a60 <pwm_set_parameters+0x34>)
+     a44:	4b07      	ldr	r3, [pc, #28]	; (a64 <pwm_set_parameters+0x38>)
+     a46:	4798      	blx	r3
+	descr->func->set_pwm_param(&descr->device, period, duty_cycle);
+     a48:	69e3      	ldr	r3, [r4, #28]
+     a4a:	691b      	ldr	r3, [r3, #16]
+     a4c:	0032      	movs	r2, r6
+     a4e:	0029      	movs	r1, r5
+     a50:	0020      	movs	r0, r4
+     a52:	4798      	blx	r3
+}
+     a54:	2000      	movs	r0, #0
+     a56:	bd70      	pop	{r4, r5, r6, pc}
+	ASSERT(descr && descr->func);
+     a58:	2000      	movs	r0, #0
+     a5a:	e7f1      	b.n	a40 <pwm_set_parameters+0x14>
+     a5c:	2000      	movs	r0, #0
+     a5e:	e7ef      	b.n	a40 <pwm_set_parameters+0x14>
+     a60:	00001fdc 	.word	0x00001fdc
+     a64:	00000a69 	.word	0x00000a69
+
+00000a68 <assert>:
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+	if (!(condition)) {
+     a68:	2800      	cmp	r0, #0
+     a6a:	d100      	bne.n	a6e <assert+0x6>
+		__asm("BKPT #0");
+     a6c:	be00      	bkpt	0x0000
+	}
+	(void)file;
+	(void)line;
+}
+     a6e:	4770      	bx	lr
+
+00000a70 <event_subscribe>:
+
+static struct list_descriptor events;
+static uint8_t                subscribed[EVENT_MASK_SIZE];
+
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb)
+{
+     a70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+     a72:	0005      	movs	r5, r0
+     a74:	0017      	movs	r7, r2
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t position = id >> 3;
+     a76:	08ce      	lsrs	r6, r1, #3
+	const uint8_t mask     = 1 << (id & 0x7);
+     a78:	2307      	movs	r3, #7
+     a7a:	400b      	ands	r3, r1
+     a7c:	2401      	movs	r4, #1
+     a7e:	409c      	lsls	r4, r3
+     a80:	b2e4      	uxtb	r4, r4
+
+	ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+     a82:	2800      	cmp	r0, #0
+     a84:	d01e      	beq.n	ac4 <event_subscribe+0x54>
+     a86:	2a00      	cmp	r2, #0
+     a88:	d01e      	beq.n	ac8 <event_subscribe+0x58>
+     a8a:	2907      	cmp	r1, #7
+     a8c:	d91e      	bls.n	acc <event_subscribe+0x5c>
+     a8e:	2000      	movs	r0, #0
+     a90:	2231      	movs	r2, #49	; 0x31
+     a92:	4914      	ldr	r1, [pc, #80]	; (ae4 <event_subscribe+0x74>)
+     a94:	4b14      	ldr	r3, [pc, #80]	; (ae8 <event_subscribe+0x78>)
+     a96:	4798      	blx	r3
+
+	if (event->mask[position] & mask) {
+     a98:	19ab      	adds	r3, r5, r6
+     a9a:	791b      	ldrb	r3, [r3, #4]
+     a9c:	4223      	tst	r3, r4
+     a9e:	d11e      	bne.n	ade <event_subscribe+0x6e>
+		return ERR_NO_CHANGE; /* Already subscribed */
+	}
+
+	if (!is_list_element(&events, event)) {
+     aa0:	0029      	movs	r1, r5
+     aa2:	4812      	ldr	r0, [pc, #72]	; (aec <event_subscribe+0x7c>)
+     aa4:	4b12      	ldr	r3, [pc, #72]	; (af0 <event_subscribe+0x80>)
+     aa6:	4798      	blx	r3
+     aa8:	2800      	cmp	r0, #0
+     aaa:	d011      	beq.n	ad0 <event_subscribe+0x60>
+		memset(event->mask, 0, EVENT_MASK_SIZE);
+		list_insert_as_head(&events, event);
+	}
+	event->cb = cb;
+     aac:	60af      	str	r7, [r5, #8]
+	event->mask[position] |= mask;
+     aae:	19ad      	adds	r5, r5, r6
+     ab0:	792b      	ldrb	r3, [r5, #4]
+     ab2:	4323      	orrs	r3, r4
+     ab4:	712b      	strb	r3, [r5, #4]
+
+	subscribed[position] |= mask;
+     ab6:	4b0d      	ldr	r3, [pc, #52]	; (aec <event_subscribe+0x7c>)
+     ab8:	199b      	adds	r3, r3, r6
+     aba:	791a      	ldrb	r2, [r3, #4]
+     abc:	4314      	orrs	r4, r2
+     abe:	711c      	strb	r4, [r3, #4]
+
+	return ERR_NONE;
+     ac0:	2000      	movs	r0, #0
+}
+     ac2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+	ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+     ac4:	2000      	movs	r0, #0
+     ac6:	e7e3      	b.n	a90 <event_subscribe+0x20>
+     ac8:	2000      	movs	r0, #0
+     aca:	e7e1      	b.n	a90 <event_subscribe+0x20>
+     acc:	2001      	movs	r0, #1
+     ace:	e7df      	b.n	a90 <event_subscribe+0x20>
+		memset(event->mask, 0, EVENT_MASK_SIZE);
+     ad0:	2300      	movs	r3, #0
+     ad2:	712b      	strb	r3, [r5, #4]
+		list_insert_as_head(&events, event);
+     ad4:	0029      	movs	r1, r5
+     ad6:	4805      	ldr	r0, [pc, #20]	; (aec <event_subscribe+0x7c>)
+     ad8:	4b06      	ldr	r3, [pc, #24]	; (af4 <event_subscribe+0x84>)
+     ada:	4798      	blx	r3
+     adc:	e7e6      	b.n	aac <event_subscribe+0x3c>
+		return ERR_NO_CHANGE; /* Already subscribed */
+     ade:	2002      	movs	r0, #2
+     ae0:	4240      	negs	r0, r0
+     ae2:	e7ee      	b.n	ac2 <event_subscribe+0x52>
+     ae4:	00001ff4 	.word	0x00001ff4
+     ae8:	00000a69 	.word	0x00000a69
+     aec:	20000058 	.word	0x20000058
+     af0:	00000af9 	.word	0x00000af9
+     af4:	00000b11 	.word	0x00000b11
+
+00000af8 <is_list_element>:
+ * \brief Check whether element belongs to list
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element)
+{
+	struct list_element *it;
+	for (it = list->head; it; it = it->next) {
+     af8:	6803      	ldr	r3, [r0, #0]
+     afa:	2b00      	cmp	r3, #0
+     afc:	d003      	beq.n	b06 <is_list_element+0xe>
+		if (it == element) {
+     afe:	428b      	cmp	r3, r1
+     b00:	d003      	beq.n	b0a <is_list_element+0x12>
+	for (it = list->head; it; it = it->next) {
+     b02:	681b      	ldr	r3, [r3, #0]
+     b04:	e7f9      	b.n	afa <is_list_element+0x2>
+			return true;
+		}
+	}
+
+	return false;
+     b06:	2000      	movs	r0, #0
+}
+     b08:	4770      	bx	lr
+			return true;
+     b0a:	2001      	movs	r0, #1
+     b0c:	e7fc      	b.n	b08 <is_list_element+0x10>
+	...
+
+00000b10 <list_insert_as_head>:
+
+/**
+ * \brief Insert an element as list head
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element)
+{
+     b10:	b570      	push	{r4, r5, r6, lr}
+     b12:	0004      	movs	r4, r0
+     b14:	000d      	movs	r5, r1
+	ASSERT(!is_list_element(list, element));
+     b16:	4b06      	ldr	r3, [pc, #24]	; (b30 <list_insert_as_head+0x20>)
+     b18:	4798      	blx	r3
+     b1a:	2301      	movs	r3, #1
+     b1c:	4058      	eors	r0, r3
+     b1e:	b2c0      	uxtb	r0, r0
+     b20:	2239      	movs	r2, #57	; 0x39
+     b22:	4904      	ldr	r1, [pc, #16]	; (b34 <list_insert_as_head+0x24>)
+     b24:	4b04      	ldr	r3, [pc, #16]	; (b38 <list_insert_as_head+0x28>)
+     b26:	4798      	blx	r3
+
+	((struct list_element *)element)->next = list->head;
+     b28:	6823      	ldr	r3, [r4, #0]
+     b2a:	602b      	str	r3, [r5, #0]
+	list->head                             = (struct list_element *)element;
+     b2c:	6025      	str	r5, [r4, #0]
+}
+     b2e:	bd70      	pop	{r4, r5, r6, pc}
+     b30:	00000af9 	.word	0x00000af9
+     b34:	00002014 	.word	0x00002014
+     b38:	00000a69 	.word	0x00000a69
+
+00000b3c <_init_chip>:
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+     b3c:	b510      	push	{r4, lr}
+}
+
+static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
+     b3e:	4b09      	ldr	r3, [pc, #36]	; (b64 <_init_chip+0x28>)
+     b40:	685a      	ldr	r2, [r3, #4]
+     b42:	605a      	str	r2, [r3, #4]
+	hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+	_set_performance_level(2);
+     b44:	2002      	movs	r0, #2
+     b46:	4b08      	ldr	r3, [pc, #32]	; (b68 <_init_chip+0x2c>)
+     b48:	4798      	blx	r3
+
+	_osc32kctrl_init_sources();
+     b4a:	4b08      	ldr	r3, [pc, #32]	; (b6c <_init_chip+0x30>)
+     b4c:	4798      	blx	r3
+	_oscctrl_init_sources();
+     b4e:	4b08      	ldr	r3, [pc, #32]	; (b70 <_init_chip+0x34>)
+     b50:	4798      	blx	r3
+	_mclk_init();
+     b52:	4b08      	ldr	r3, [pc, #32]	; (b74 <_init_chip+0x38>)
+     b54:	4798      	blx	r3
+#if _GCLK_INIT_1ST
+	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+	_oscctrl_init_referenced_generators();
+     b56:	4b08      	ldr	r3, [pc, #32]	; (b78 <_init_chip+0x3c>)
+     b58:	4798      	blx	r3
+	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+     b5a:	201f      	movs	r0, #31
+     b5c:	4b07      	ldr	r3, [pc, #28]	; (b7c <_init_chip+0x40>)
+     b5e:	4798      	blx	r3
+#endif
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+	_port_event_init();
+#endif
+}
+     b60:	bd10      	pop	{r4, pc}
+     b62:	46c0      	nop			; (mov r8, r8)
+     b64:	41004000 	.word	0x41004000
+     b68:	00000ce9 	.word	0x00000ce9
+     b6c:	00000c89 	.word	0x00000c89
+     b70:	00000cad 	.word	0x00000cad
+     b74:	00000c79 	.word	0x00000c79
+     b78:	00000ce5 	.word	0x00000ce5
+     b7c:	00000c41 	.word	0x00000c41
+
+00000b80 <_ext_irq_handler>:
+
+/**
+ * \brief Inter EIC interrupt handler
+ */
+static void _ext_irq_handler(void)
+{
+     b80:	b5f0      	push	{r4, r5, r6, r7, lr}
+     b82:	b083      	sub	sp, #12
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+     b84:	4b25      	ldr	r3, [pc, #148]	; (c1c <_ext_irq_handler+0x9c>)
+     b86:	695a      	ldr	r2, [r3, #20]
+	volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
+     b88:	9201      	str	r2, [sp, #4]
+	int8_t            pos;
+	uint32_t          pin = INVALID_PIN_NUMBER;
+
+	hri_eic_clear_INTFLAG_reg(EIC, flags);
+     b8a:	9a01      	ldr	r2, [sp, #4]
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+     b8c:	615a      	str	r2, [r3, #20]
+
+	ASSERT(callback);
+     b8e:	4b24      	ldr	r3, [pc, #144]	; (c20 <_ext_irq_handler+0xa0>)
+     b90:	6818      	ldr	r0, [r3, #0]
+     b92:	1e43      	subs	r3, r0, #1
+     b94:	4198      	sbcs	r0, r3
+     b96:	b2c0      	uxtb	r0, r0
+     b98:	22da      	movs	r2, #218	; 0xda
+     b9a:	4922      	ldr	r1, [pc, #136]	; (c24 <_ext_irq_handler+0xa4>)
+     b9c:	4b22      	ldr	r3, [pc, #136]	; (c28 <_ext_irq_handler+0xa8>)
+     b9e:	4798      	blx	r3
+	uint32_t          pin = INVALID_PIN_NUMBER;
+     ba0:	2501      	movs	r5, #1
+     ba2:	426d      	negs	r5, r5
+
+	while (flags) {
+     ba4:	e02f      	b.n	c06 <_ext_irq_handler+0x86>
+			uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+			while (upper >= lower) {
+				middle = (upper + lower) >> 1;
+				if (_map[middle].extint == pos) {
+					pin = _map[middle].pin;
+     ba6:	00db      	lsls	r3, r3, #3
+     ba8:	4a20      	ldr	r2, [pc, #128]	; (c2c <_ext_irq_handler+0xac>)
+     baa:	18d3      	adds	r3, r2, r3
+     bac:	685d      	ldr	r5, [r3, #4]
+				} else {
+					upper = middle - 1;
+				}
+			}
+
+			if (INVALID_PIN_NUMBER != pin) {
+     bae:	1c6b      	adds	r3, r5, #1
+     bb0:	d003      	beq.n	bba <_ext_irq_handler+0x3a>
+				callback(pin);
+     bb2:	4b1b      	ldr	r3, [pc, #108]	; (c20 <_ext_irq_handler+0xa0>)
+     bb4:	681b      	ldr	r3, [r3, #0]
+     bb6:	0028      	movs	r0, r5
+     bb8:	4798      	blx	r3
+			}
+			flags &= ~(1ul << pos);
+     bba:	2201      	movs	r2, #1
+     bbc:	40a2      	lsls	r2, r4
+     bbe:	9b01      	ldr	r3, [sp, #4]
+     bc0:	4393      	bics	r3, r2
+     bc2:	9301      	str	r3, [sp, #4]
+			pos = ffs(flags) - 1;
+     bc4:	9801      	ldr	r0, [sp, #4]
+     bc6:	4b1a      	ldr	r3, [pc, #104]	; (c30 <_ext_irq_handler+0xb0>)
+     bc8:	4798      	blx	r3
+     bca:	3801      	subs	r0, #1
+     bcc:	b244      	sxtb	r4, r0
+		while (-1 != pos) {
+     bce:	1c63      	adds	r3, r4, #1
+     bd0:	d014      	beq.n	bfc <_ext_irq_handler+0x7c>
+     bd2:	2603      	movs	r6, #3
+     bd4:	2000      	movs	r0, #0
+     bd6:	e001      	b.n	bdc <_ext_irq_handler+0x5c>
+					upper = middle - 1;
+     bd8:	3901      	subs	r1, #1
+     bda:	b2ce      	uxtb	r6, r1
+			while (upper >= lower) {
+     bdc:	42b0      	cmp	r0, r6
+     bde:	d8e6      	bhi.n	bae <_ext_irq_handler+0x2e>
+				middle = (upper + lower) >> 1;
+     be0:	1833      	adds	r3, r6, r0
+     be2:	105b      	asrs	r3, r3, #1
+     be4:	b2d9      	uxtb	r1, r3
+     be6:	22ff      	movs	r2, #255	; 0xff
+     be8:	4013      	ands	r3, r2
+				if (_map[middle].extint == pos) {
+     bea:	00df      	lsls	r7, r3, #3
+     bec:	4a0f      	ldr	r2, [pc, #60]	; (c2c <_ext_irq_handler+0xac>)
+     bee:	5cba      	ldrb	r2, [r7, r2]
+     bf0:	42a2      	cmp	r2, r4
+     bf2:	d0d8      	beq.n	ba6 <_ext_irq_handler+0x26>
+				if (_map[middle].extint < pos) {
+     bf4:	daf0      	bge.n	bd8 <_ext_irq_handler+0x58>
+					lower = middle + 1;
+     bf6:	3101      	adds	r1, #1
+     bf8:	b2c8      	uxtb	r0, r1
+     bfa:	e7ef      	b.n	bdc <_ext_irq_handler+0x5c>
+	return ((Eic *)hw)->INTFLAG.reg;
+     bfc:	4b07      	ldr	r3, [pc, #28]	; (c1c <_ext_irq_handler+0x9c>)
+     bfe:	695a      	ldr	r2, [r3, #20]
+		}
+		flags = hri_eic_read_INTFLAG_reg(EIC);
+     c00:	9201      	str	r2, [sp, #4]
+		hri_eic_clear_INTFLAG_reg(EIC, flags);
+     c02:	9a01      	ldr	r2, [sp, #4]
+	((Eic *)hw)->INTFLAG.reg = mask;
+     c04:	615a      	str	r2, [r3, #20]
+	while (flags) {
+     c06:	9b01      	ldr	r3, [sp, #4]
+     c08:	2b00      	cmp	r3, #0
+     c0a:	d005      	beq.n	c18 <_ext_irq_handler+0x98>
+		pos = ffs(flags) - 1;
+     c0c:	9801      	ldr	r0, [sp, #4]
+     c0e:	4b08      	ldr	r3, [pc, #32]	; (c30 <_ext_irq_handler+0xb0>)
+     c10:	4798      	blx	r3
+     c12:	3801      	subs	r0, #1
+     c14:	b244      	sxtb	r4, r0
+		while (-1 != pos) {
+     c16:	e7da      	b.n	bce <_ext_irq_handler+0x4e>
+	}
+}
+     c18:	b003      	add	sp, #12
+     c1a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+     c1c:	40002800 	.word	0x40002800
+     c20:	20000060 	.word	0x20000060
+     c24:	0000204c 	.word	0x0000204c
+     c28:	00000a69 	.word	0x00000a69
+     c2c:	00002034 	.word	0x00002034
+     c30:	00001e5d 	.word	0x00001e5d
+
+00000c34 <EIC_Handler>:
+
+/**
+ * \brief EIC interrupt handler
+ */
+void EIC_Handler(void)
+{
+     c34:	b510      	push	{r4, lr}
+	_ext_irq_handler();
+     c36:	4b01      	ldr	r3, [pc, #4]	; (c3c <EIC_Handler+0x8>)
+     c38:	4798      	blx	r3
+}
+     c3a:	bd10      	pop	{r4, pc}
+     c3c:	00000b81 	.word	0x00000b81
+
+00000c40 <_gclk_init_generators_by_fref>:
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	if (bm & (1ul << 0)) {
+     c40:	07c3      	lsls	r3, r0, #31
+     c42:	d507      	bpl.n	c54 <_gclk_init_generators_by_fref+0x14>
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+     c44:	4a09      	ldr	r2, [pc, #36]	; (c6c <_gclk_init_generators_by_fref+0x2c>)
+     c46:	4b0a      	ldr	r3, [pc, #40]	; (c70 <_gclk_init_generators_by_fref+0x30>)
+     c48:	621a      	str	r2, [r3, #32]
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+     c4a:	4b09      	ldr	r3, [pc, #36]	; (c70 <_gclk_init_generators_by_fref+0x30>)
+     c4c:	685b      	ldr	r3, [r3, #4]
+     c4e:	227d      	movs	r2, #125	; 0x7d
+     c50:	421a      	tst	r2, r3
+     c52:	d1fa      	bne.n	c4a <_gclk_init_generators_by_fref+0xa>
+		        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	if (bm & (1ul << 3)) {
+     c54:	0703      	lsls	r3, r0, #28
+     c56:	d507      	bpl.n	c68 <_gclk_init_generators_by_fref+0x28>
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+     c58:	4a06      	ldr	r2, [pc, #24]	; (c74 <_gclk_init_generators_by_fref+0x34>)
+     c5a:	4b05      	ldr	r3, [pc, #20]	; (c70 <_gclk_init_generators_by_fref+0x30>)
+     c5c:	62da      	str	r2, [r3, #44]	; 0x2c
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+     c5e:	4b04      	ldr	r3, [pc, #16]	; (c70 <_gclk_init_generators_by_fref+0x30>)
+     c60:	685b      	ldr	r3, [r3, #4]
+     c62:	227d      	movs	r2, #125	; 0x7d
+     c64:	421a      	tst	r2, r3
+     c66:	d1fa      	bne.n	c5e <_gclk_init_generators_by_fref+0x1e>
+		        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+	}
+#endif
+}
+     c68:	4770      	bx	lr
+     c6a:	46c0      	nop			; (mov r8, r8)
+     c6c:	00010105 	.word	0x00010105
+     c70:	40001c00 	.word	0x40001c00
+     c74:	00012304 	.word	0x00012304
+
+00000c78 <_mclk_init>:
+	((Mclk *)hw)->BUPDIV.reg = data;
+     c78:	4b02      	ldr	r3, [pc, #8]	; (c84 <_mclk_init+0xc>)
+     c7a:	2208      	movs	r2, #8
+     c7c:	719a      	strb	r2, [r3, #6]
+	((Mclk *)hw)->CPUDIV.reg = data;
+     c7e:	3a07      	subs	r2, #7
+     c80:	711a      	strb	r2, [r3, #4]
+void _mclk_init(void)
+{
+	void *hw = (void *)MCLK;
+	hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV));
+	hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV));
+}
+     c82:	4770      	bx	lr
+     c84:	40000800 	.word	0x40000800
+
+00000c88 <_osc32kctrl_init_sources>:
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+     c88:	4a07      	ldr	r2, [pc, #28]	; (ca8 <_osc32kctrl_init_sources+0x20>)
+     c8a:	239e      	movs	r3, #158	; 0x9e
+     c8c:	8293      	strh	r3, [r2, #20]
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+     c8e:	2300      	movs	r3, #0
+     c90:	7593      	strb	r3, [r2, #22]
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+     c92:	75d3      	strb	r3, [r2, #23]
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+     c94:	69d3      	ldr	r3, [r2, #28]
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+     c96:	0a1b      	lsrs	r3, r3, #8
+	calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
+	hri_osc32kctrl_write_OSCULP32K_reg(hw,
+#if CONF_OSC32K_CALIB_ENABLE == 1
+	                                   OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
+#else
+	                                   OSC32KCTRL_OSCULP32K_CALIB(calib)
+     c98:	021b      	lsls	r3, r3, #8
+     c9a:	21f8      	movs	r1, #248	; 0xf8
+     c9c:	0149      	lsls	r1, r1, #5
+     c9e:	400b      	ands	r3, r1
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+     ca0:	61d3      	str	r3, [r2, #28]
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+     ca2:	2304      	movs	r3, #4
+     ca4:	7413      	strb	r3, [r2, #16]
+#endif
+#endif
+
+	hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+	(void)calib;
+}
+     ca6:	4770      	bx	lr
+     ca8:	40001400 	.word	0x40001400
+
+00000cac <_oscctrl_init_sources>:
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg = data;
+     cac:	2282      	movs	r2, #130	; 0x82
+     cae:	4b0c      	ldr	r3, [pc, #48]	; (ce0 <_oscctrl_init_sources+0x34>)
+     cb0:	751a      	strb	r2, [r3, #20]
+	while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+     cb2:	2338      	movs	r3, #56	; 0x38
+     cb4:	4a0a      	ldr	r2, [pc, #40]	; (ce0 <_oscctrl_init_sources+0x34>)
+     cb6:	5cd3      	ldrb	r3, [r2, r3]
+     cb8:	079b      	lsls	r3, r3, #30
+     cba:	d4fa      	bmi.n	cb2 <_oscctrl_init_sources+0x6>
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos;
+     cbc:	4b08      	ldr	r3, [pc, #32]	; (ce0 <_oscctrl_init_sources+0x34>)
+     cbe:	68db      	ldr	r3, [r3, #12]
+#endif
+#endif
+
+#if CONF_OSC16M_CONFIG == 1
+#if CONF_OSC16M_ENABLE == 1
+	while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw))
+     cc0:	06db      	lsls	r3, r3, #27
+     cc2:	d5fb      	bpl.n	cbc <_oscctrl_init_sources+0x10>
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND;
+     cc4:	4a06      	ldr	r2, [pc, #24]	; (ce0 <_oscctrl_init_sources+0x34>)
+     cc6:	7d13      	ldrb	r3, [r2, #20]
+     cc8:	2180      	movs	r1, #128	; 0x80
+     cca:	4249      	negs	r1, r1
+     ccc:	430b      	orrs	r3, r1
+     cce:	b2db      	uxtb	r3, r3
+     cd0:	7513      	strb	r3, [r2, #20]
+	while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+     cd2:	2338      	movs	r3, #56	; 0x38
+     cd4:	4a02      	ldr	r2, [pc, #8]	; (ce0 <_oscctrl_init_sources+0x34>)
+     cd6:	5cd2      	ldrb	r2, [r2, r3]
+     cd8:	3b2a      	subs	r3, #42	; 0x2a
+     cda:	421a      	tst	r2, r3
+     cdc:	d1f9      	bne.n	cd2 <_oscctrl_init_sources+0x26>
+#if CONF_OSC16M_ONDEMAND == 1
+	hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw);
+#endif
+#endif
+	(void)hw;
+}
+     cde:	4770      	bx	lr
+     ce0:	40001000 	.word	0x40001000
+
+00000ce4 <_oscctrl_init_referenced_generators>:
+#if CONF_DFLL_CONFIG == 1
+	while (hri_gclk_read_SYNCBUSY_reg(GCLK))
+		;
+#endif
+	(void)hw, (void)tmp;
+}
+     ce4:	4770      	bx	lr
+	...
+
+00000ce8 <_set_performance_level>:
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+     ce8:	4b09      	ldr	r3, [pc, #36]	; (d10 <_set_performance_level+0x28>)
+     cea:	789b      	ldrb	r3, [r3, #2]
+	tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
+     cec:	2203      	movs	r2, #3
+     cee:	4013      	ands	r3, r2
+/**
+ * \brief Set performance level
+ */
+void _set_performance_level(const uint8_t level)
+{
+	if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) {
+     cf0:	4298      	cmp	r0, r3
+     cf2:	d00c      	beq.n	d0e <_set_performance_level+0x26>
+	((Pm *)hw)->INTFLAG.reg = mask;
+     cf4:	4a06      	ldr	r2, [pc, #24]	; (d10 <_set_performance_level+0x28>)
+     cf6:	23ff      	movs	r3, #255	; 0xff
+     cf8:	7193      	strb	r3, [r2, #6]
+
+static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PLCFG.reg;
+     cfa:	7893      	ldrb	r3, [r2, #2]
+	tmp &= ~PM_PLCFG_PLSEL_Msk;
+     cfc:	2103      	movs	r1, #3
+     cfe:	438b      	bics	r3, r1
+	tmp |= PM_PLCFG_PLSEL(data);
+     d00:	4008      	ands	r0, r1
+     d02:	4318      	orrs	r0, r3
+	((Pm *)hw)->PLCFG.reg = tmp;
+     d04:	7090      	strb	r0, [r2, #2]
+	return ((Pm *)hw)->INTFLAG.reg;
+     d06:	4b02      	ldr	r3, [pc, #8]	; (d10 <_set_performance_level+0x28>)
+     d08:	799b      	ldrb	r3, [r3, #6]
+		hri_pm_clear_INTFLAG_reg(PM, 0xFF);
+		hri_pm_write_PLCFG_PLSEL_bf(PM, level);
+		while (!hri_pm_read_INTFLAG_reg(PM))
+     d0a:	2b00      	cmp	r3, #0
+     d0c:	d0fb      	beq.n	d06 <_set_performance_level+0x1e>
+			;
+	}
+}
+     d0e:	4770      	bx	lr
+     d10:	40000400 	.word	0x40000400
+
+00000d14 <_rtc_interrupt_handler>:
+ * \brief RTC interrupt handler
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+static void _rtc_interrupt_handler(struct calendar_dev *dev)
+{
+     d14:	b510      	push	{r4, lr}
+     d16:	0004      	movs	r4, r0
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status  = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
+     d18:	6802      	ldr	r2, [r0, #0]
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+     d1a:	8991      	ldrh	r1, [r2, #12]
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+     d1c:	8953      	ldrh	r3, [r2, #10]
+	uint16_t interrupt_enabled = hri_rtcmode0_read_INTEN_reg(dev->hw);
+
+	if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
+     d1e:	400b      	ands	r3, r1
+     d20:	05da      	lsls	r2, r3, #23
+     d22:	d402      	bmi.n	d2a <_rtc_interrupt_handler+0x16>
+		dev->callback(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+	} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
+     d24:	045b      	lsls	r3, r3, #17
+     d26:	d407      	bmi.n	d38 <_rtc_interrupt_handler+0x24>
+		dev->callback_tamper(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+	}
+}
+     d28:	bd10      	pop	{r4, pc}
+		dev->callback(dev);
+     d2a:	6843      	ldr	r3, [r0, #4]
+     d2c:	4798      	blx	r3
+		hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+     d2e:	6823      	ldr	r3, [r4, #0]
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+     d30:	2280      	movs	r2, #128	; 0x80
+     d32:	0052      	lsls	r2, r2, #1
+     d34:	819a      	strh	r2, [r3, #12]
+     d36:	e7f7      	b.n	d28 <_rtc_interrupt_handler+0x14>
+		dev->callback_tamper(dev);
+     d38:	6883      	ldr	r3, [r0, #8]
+     d3a:	4798      	blx	r3
+		hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+     d3c:	6823      	ldr	r3, [r4, #0]
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+     d3e:	2280      	movs	r2, #128	; 0x80
+     d40:	01d2      	lsls	r2, r2, #7
+     d42:	819a      	strh	r2, [r3, #12]
+}
+     d44:	e7f0      	b.n	d28 <_rtc_interrupt_handler+0x14>
+	...
+
+00000d48 <_calendar_init>:
+{
+     d48:	b510      	push	{r4, lr}
+     d4a:	1e04      	subs	r4, r0, #0
+	ASSERT(dev && dev->hw);
+     d4c:	d037      	beq.n	dbe <_calendar_init+0x76>
+     d4e:	6803      	ldr	r3, [r0, #0]
+     d50:	2b00      	cmp	r3, #0
+     d52:	d032      	beq.n	dba <_calendar_init+0x72>
+     d54:	2001      	movs	r0, #1
+     d56:	222f      	movs	r2, #47	; 0x2f
+     d58:	491a      	ldr	r1, [pc, #104]	; (dc4 <_calendar_init+0x7c>)
+     d5a:	4b1b      	ldr	r3, [pc, #108]	; (dc8 <_calendar_init+0x80>)
+     d5c:	4798      	blx	r3
+	_rtc_dev = dev;
+     d5e:	4b1b      	ldr	r3, [pc, #108]	; (dcc <_calendar_init+0x84>)
+     d60:	601c      	str	r4, [r3, #0]
+	if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
+     d62:	6821      	ldr	r1, [r4, #0]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     d64:	690a      	ldr	r2, [r1, #16]
+     d66:	4b1a      	ldr	r3, [pc, #104]	; (dd0 <_calendar_init+0x88>)
+     d68:	421a      	tst	r2, r3
+     d6a:	d1fb      	bne.n	d64 <_calendar_init+0x1c>
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+     d6c:	880b      	ldrh	r3, [r1, #0]
+     d6e:	079b      	lsls	r3, r3, #30
+     d70:	d50b      	bpl.n	d8a <_calendar_init+0x42>
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+     d72:	880b      	ldrh	r3, [r1, #0]
+     d74:	2202      	movs	r2, #2
+     d76:	4393      	bics	r3, r2
+     d78:	800b      	strh	r3, [r1, #0]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     d7a:	690a      	ldr	r2, [r1, #16]
+     d7c:	4b14      	ldr	r3, [pc, #80]	; (dd0 <_calendar_init+0x88>)
+     d7e:	421a      	tst	r2, r3
+     d80:	d1fb      	bne.n	d7a <_calendar_init+0x32>
+		hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
+     d82:	6822      	ldr	r2, [r4, #0]
+     d84:	6913      	ldr	r3, [r2, #16]
+     d86:	079b      	lsls	r3, r3, #30
+     d88:	d4fc      	bmi.n	d84 <_calendar_init+0x3c>
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+     d8a:	6822      	ldr	r2, [r4, #0]
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+     d8c:	8813      	ldrh	r3, [r2, #0]
+     d8e:	2101      	movs	r1, #1
+     d90:	430b      	orrs	r3, r1
+     d92:	b29b      	uxth	r3, r3
+     d94:	8013      	strh	r3, [r2, #0]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     d96:	6913      	ldr	r3, [r2, #16]
+     d98:	07db      	lsls	r3, r3, #31
+     d9a:	d4fc      	bmi.n	d96 <_calendar_init+0x4e>
+	hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
+     d9c:	6823      	ldr	r3, [r4, #0]
+     d9e:	691a      	ldr	r2, [r3, #16]
+     da0:	07d2      	lsls	r2, r2, #31
+     da2:	d4fc      	bmi.n	d9e <_calendar_init+0x56>
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+     da4:	4a0b      	ldr	r2, [pc, #44]	; (dd4 <_calendar_init+0x8c>)
+     da6:	801a      	strh	r2, [r3, #0]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     da8:	6919      	ldr	r1, [r3, #16]
+     daa:	4a09      	ldr	r2, [pc, #36]	; (dd0 <_calendar_init+0x88>)
+     dac:	4211      	tst	r1, r2
+     dae:	d1fb      	bne.n	da8 <_calendar_init+0x60>
+	    dev->hw,
+     db0:	6823      	ldr	r3, [r4, #0]
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+     db2:	2200      	movs	r2, #0
+     db4:	661a      	str	r2, [r3, #96]	; 0x60
+}
+     db6:	2000      	movs	r0, #0
+     db8:	bd10      	pop	{r4, pc}
+	ASSERT(dev && dev->hw);
+     dba:	2000      	movs	r0, #0
+     dbc:	e7cb      	b.n	d56 <_calendar_init+0xe>
+     dbe:	2000      	movs	r0, #0
+     dc0:	e7c9      	b.n	d56 <_calendar_init+0xe>
+     dc2:	46c0      	nop			; (mov r8, r8)
+     dc4:	00002064 	.word	0x00002064
+     dc8:	00000a69 	.word	0x00000a69
+     dcc:	20000064 	.word	0x20000064
+     dd0:	00008003 	.word	0x00008003
+     dd4:	ffff8b00 	.word	0xffff8b00
+
+00000dd8 <_calendar_enable>:
+{
+     dd8:	b510      	push	{r4, lr}
+     dda:	1e04      	subs	r4, r0, #0
+	ASSERT(dev && dev->hw);
+     ddc:	d015      	beq.n	e0a <_calendar_enable+0x32>
+     dde:	6803      	ldr	r3, [r0, #0]
+     de0:	2b00      	cmp	r3, #0
+     de2:	d010      	beq.n	e06 <_calendar_enable+0x2e>
+     de4:	2001      	movs	r0, #1
+     de6:	2273      	movs	r2, #115	; 0x73
+     de8:	4909      	ldr	r1, [pc, #36]	; (e10 <_calendar_enable+0x38>)
+     dea:	4b0a      	ldr	r3, [pc, #40]	; (e14 <_calendar_enable+0x3c>)
+     dec:	4798      	blx	r3
+	hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw);
+     dee:	6821      	ldr	r1, [r4, #0]
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+     df0:	880b      	ldrh	r3, [r1, #0]
+     df2:	2202      	movs	r2, #2
+     df4:	4313      	orrs	r3, r2
+     df6:	b29b      	uxth	r3, r3
+     df8:	800b      	strh	r3, [r1, #0]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     dfa:	690a      	ldr	r2, [r1, #16]
+     dfc:	4b06      	ldr	r3, [pc, #24]	; (e18 <_calendar_enable+0x40>)
+     dfe:	421a      	tst	r2, r3
+     e00:	d1fb      	bne.n	dfa <_calendar_enable+0x22>
+}
+     e02:	2000      	movs	r0, #0
+     e04:	bd10      	pop	{r4, pc}
+	ASSERT(dev && dev->hw);
+     e06:	2000      	movs	r0, #0
+     e08:	e7ed      	b.n	de6 <_calendar_enable+0xe>
+     e0a:	2000      	movs	r0, #0
+     e0c:	e7eb      	b.n	de6 <_calendar_enable+0xe>
+     e0e:	46c0      	nop			; (mov r8, r8)
+     e10:	00002064 	.word	0x00002064
+     e14:	00000a69 	.word	0x00000a69
+     e18:	00008003 	.word	0x00008003
+
+00000e1c <_calendar_set_counter>:
+{
+     e1c:	b570      	push	{r4, r5, r6, lr}
+     e1e:	0004      	movs	r4, r0
+     e20:	000d      	movs	r5, r1
+	ASSERT(dev && dev->hw);
+     e22:	2800      	cmp	r0, #0
+     e24:	d010      	beq.n	e48 <_calendar_set_counter+0x2c>
+     e26:	6803      	ldr	r3, [r0, #0]
+     e28:	2b00      	cmp	r3, #0
+     e2a:	d00b      	beq.n	e44 <_calendar_set_counter+0x28>
+     e2c:	2001      	movs	r0, #1
+     e2e:	228b      	movs	r2, #139	; 0x8b
+     e30:	4906      	ldr	r1, [pc, #24]	; (e4c <_calendar_set_counter+0x30>)
+     e32:	4b07      	ldr	r3, [pc, #28]	; (e50 <_calendar_set_counter+0x34>)
+     e34:	4798      	blx	r3
+	hri_rtcmode0_write_COUNT_reg(dev->hw, counter);
+     e36:	6822      	ldr	r2, [r4, #0]
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+     e38:	6195      	str	r5, [r2, #24]
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+     e3a:	6913      	ldr	r3, [r2, #16]
+     e3c:	071b      	lsls	r3, r3, #28
+     e3e:	d4fc      	bmi.n	e3a <_calendar_set_counter+0x1e>
+}
+     e40:	2000      	movs	r0, #0
+     e42:	bd70      	pop	{r4, r5, r6, pc}
+	ASSERT(dev && dev->hw);
+     e44:	2000      	movs	r0, #0
+     e46:	e7f2      	b.n	e2e <_calendar_set_counter+0x12>
+     e48:	2000      	movs	r0, #0
+     e4a:	e7f0      	b.n	e2e <_calendar_set_counter+0x12>
+     e4c:	00002064 	.word	0x00002064
+     e50:	00000a69 	.word	0x00000a69
+
+00000e54 <_calendar_get_counter>:
+{
+     e54:	b510      	push	{r4, lr}
+     e56:	1e04      	subs	r4, r0, #0
+	ASSERT(dev && dev->hw);
+     e58:	d00f      	beq.n	e7a <_calendar_get_counter+0x26>
+     e5a:	6803      	ldr	r3, [r0, #0]
+     e5c:	2b00      	cmp	r3, #0
+     e5e:	d00a      	beq.n	e76 <_calendar_get_counter+0x22>
+     e60:	2001      	movs	r0, #1
+     e62:	2297      	movs	r2, #151	; 0x97
+     e64:	4906      	ldr	r1, [pc, #24]	; (e80 <_calendar_get_counter+0x2c>)
+     e66:	4b07      	ldr	r3, [pc, #28]	; (e84 <_calendar_get_counter+0x30>)
+     e68:	4798      	blx	r3
+	return hri_rtcmode0_read_COUNT_reg(dev->hw);
+     e6a:	6822      	ldr	r2, [r4, #0]
+     e6c:	6913      	ldr	r3, [r2, #16]
+     e6e:	071b      	lsls	r3, r3, #28
+     e70:	d4fc      	bmi.n	e6c <_calendar_get_counter+0x18>
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+     e72:	6990      	ldr	r0, [r2, #24]
+}
+     e74:	bd10      	pop	{r4, pc}
+	ASSERT(dev && dev->hw);
+     e76:	2000      	movs	r0, #0
+     e78:	e7f3      	b.n	e62 <_calendar_get_counter+0xe>
+     e7a:	2000      	movs	r0, #0
+     e7c:	e7f1      	b.n	e62 <_calendar_get_counter+0xe>
+     e7e:	46c0      	nop			; (mov r8, r8)
+     e80:	00002064 	.word	0x00002064
+     e84:	00000a69 	.word	0x00000a69
+
+00000e88 <RTC_Handler>:
+
+/**
+ * \brief Rtc interrupt handler
+ */
+void RTC_Handler(void)
+{
+     e88:	b510      	push	{r4, lr}
+	_rtc_interrupt_handler(_rtc_dev);
+     e8a:	4b02      	ldr	r3, [pc, #8]	; (e94 <RTC_Handler+0xc>)
+     e8c:	6818      	ldr	r0, [r3, #0]
+     e8e:	4b02      	ldr	r3, [pc, #8]	; (e98 <RTC_Handler+0x10>)
+     e90:	4798      	blx	r3
+}
+     e92:	bd10      	pop	{r4, pc}
+     e94:	20000064 	.word	0x20000064
+     e98:	00000d15 	.word	0x00000d15
+
+00000e9c <_sercom_get_hardware_index>:
+{
+#ifdef _UNIT_TEST_
+	return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom);
+#endif
+
+	return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
+     e9c:	4b02      	ldr	r3, [pc, #8]	; (ea8 <_sercom_get_hardware_index+0xc>)
+     e9e:	469c      	mov	ip, r3
+     ea0:	4460      	add	r0, ip
+     ea2:	0a80      	lsrs	r0, r0, #10
+     ea4:	b2c0      	uxtb	r0, r0
+}
+     ea6:	4770      	bx	lr
+     ea8:	bdfffc00 	.word	0xbdfffc00
+
+00000eac <_get_i2cm_index>:
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2cm_index(const void *const hw)
+{
+     eac:	b510      	push	{r4, lr}
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+     eae:	4b0d      	ldr	r3, [pc, #52]	; (ee4 <_get_i2cm_index+0x38>)
+     eb0:	4798      	blx	r3
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+     eb2:	2300      	movs	r3, #0
+     eb4:	2b00      	cmp	r3, #0
+     eb6:	d008      	beq.n	eca <_get_i2cm_index+0x1e>
+		if (_i2cms[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+     eb8:	22e6      	movs	r2, #230	; 0xe6
+     eba:	0092      	lsls	r2, r2, #2
+     ebc:	490a      	ldr	r1, [pc, #40]	; (ee8 <_get_i2cm_index+0x3c>)
+     ebe:	2000      	movs	r0, #0
+     ec0:	4b0a      	ldr	r3, [pc, #40]	; (eec <_get_i2cm_index+0x40>)
+     ec2:	4798      	blx	r3
+	return -1;
+     ec4:	2001      	movs	r0, #1
+     ec6:	4240      	negs	r0, r0
+}
+     ec8:	bd10      	pop	{r4, pc}
+		if (_i2cms[i].number == sercom_offset) {
+     eca:	005a      	lsls	r2, r3, #1
+     ecc:	18d2      	adds	r2, r2, r3
+     ece:	00d1      	lsls	r1, r2, #3
+     ed0:	4a07      	ldr	r2, [pc, #28]	; (ef0 <_get_i2cm_index+0x44>)
+     ed2:	1852      	adds	r2, r2, r1
+     ed4:	7d12      	ldrb	r2, [r2, #20]
+     ed6:	4290      	cmp	r0, r2
+     ed8:	d002      	beq.n	ee0 <_get_i2cm_index+0x34>
+	for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+     eda:	3301      	adds	r3, #1
+     edc:	b2db      	uxtb	r3, r3
+     ede:	e7e9      	b.n	eb4 <_get_i2cm_index+0x8>
+			return i;
+     ee0:	b258      	sxtb	r0, r3
+     ee2:	e7f1      	b.n	ec8 <_get_i2cm_index+0x1c>
+     ee4:	00000e9d 	.word	0x00000e9d
+     ee8:	000020cc 	.word	0x000020cc
+     eec:	00000a69 	.word	0x00000a69
+     ef0:	0000207c 	.word	0x0000207c
+
+00000ef4 <_i2c_m_sync_init_impl>:
+	}
+	return ERR_NONE;
+}
+
+static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw)
+{
+     ef4:	b570      	push	{r4, r5, r6, lr}
+     ef6:	0005      	movs	r5, r0
+     ef8:	000c      	movs	r4, r1
+	uint8_t i = _get_i2cm_index(hw);
+     efa:	0008      	movs	r0, r1
+     efc:	4b2d      	ldr	r3, [pc, #180]	; (fb4 <_i2c_m_sync_init_impl+0xc0>)
+     efe:	4798      	blx	r3
+     f00:	b2c0      	uxtb	r0, r0
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+     f02:	69e3      	ldr	r3, [r4, #28]
+
+	if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) {
+     f04:	07db      	lsls	r3, r3, #31
+     f06:	d41d      	bmi.n	f44 <_i2c_m_sync_init_impl+0x50>
+		uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk;
+     f08:	0043      	lsls	r3, r0, #1
+     f0a:	181b      	adds	r3, r3, r0
+     f0c:	00da      	lsls	r2, r3, #3
+     f0e:	4b2a      	ldr	r3, [pc, #168]	; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+     f10:	189b      	adds	r3, r3, r2
+     f12:	699a      	ldr	r2, [r3, #24]
+     f14:	231c      	movs	r3, #28
+     f16:	401a      	ands	r2, r3
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f18:	69e3      	ldr	r3, [r4, #28]
+     f1a:	079b      	lsls	r3, r3, #30
+     f1c:	d1fc      	bne.n	f18 <_i2c_m_sync_init_impl+0x24>
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+     f1e:	6823      	ldr	r3, [r4, #0]
+		if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) {
+     f20:	079b      	lsls	r3, r3, #30
+     f22:	d509      	bpl.n	f38 <_i2c_m_sync_init_impl+0x44>
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+     f24:	6823      	ldr	r3, [r4, #0]
+     f26:	2102      	movs	r1, #2
+     f28:	438b      	bics	r3, r1
+     f2a:	6023      	str	r3, [r4, #0]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f2c:	69e3      	ldr	r3, [r4, #28]
+     f2e:	079b      	lsls	r3, r3, #30
+     f30:	d1fc      	bne.n	f2c <_i2c_m_sync_init_impl+0x38>
+     f32:	69e3      	ldr	r3, [r4, #28]
+     f34:	079b      	lsls	r3, r3, #30
+     f36:	d4fc      	bmi.n	f32 <_i2c_m_sync_init_impl+0x3e>
+			hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE);
+		}
+		hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode);
+     f38:	2301      	movs	r3, #1
+     f3a:	4313      	orrs	r3, r2
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+     f3c:	6023      	str	r3, [r4, #0]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f3e:	69e3      	ldr	r3, [r4, #28]
+     f40:	079b      	lsls	r3, r3, #30
+     f42:	d1fc      	bne.n	f3e <_i2c_m_sync_init_impl+0x4a>
+     f44:	69e3      	ldr	r3, [r4, #28]
+     f46:	07db      	lsls	r3, r3, #31
+     f48:	d4fc      	bmi.n	f44 <_i2c_m_sync_init_impl+0x50>
+	}
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+
+	hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a);
+     f4a:	0043      	lsls	r3, r0, #1
+     f4c:	181b      	adds	r3, r3, r0
+     f4e:	00da      	lsls	r2, r3, #3
+     f50:	4b19      	ldr	r3, [pc, #100]	; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+     f52:	189b      	adds	r3, r3, r2
+     f54:	699b      	ldr	r3, [r3, #24]
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+     f56:	6023      	str	r3, [r4, #0]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f58:	69e3      	ldr	r3, [r4, #28]
+     f5a:	079b      	lsls	r3, r3, #30
+     f5c:	d1fc      	bne.n	f58 <_i2c_m_sync_init_impl+0x64>
+	hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b);
+     f5e:	0043      	lsls	r3, r0, #1
+     f60:	181b      	adds	r3, r3, r0
+     f62:	00da      	lsls	r2, r3, #3
+     f64:	4b14      	ldr	r3, [pc, #80]	; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+     f66:	189b      	adds	r3, r3, r2
+     f68:	69db      	ldr	r3, [r3, #28]
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+     f6a:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f6c:	69e3      	ldr	r3, [r4, #28]
+     f6e:	075b      	lsls	r3, r3, #29
+     f70:	d4fc      	bmi.n	f6c <_i2c_m_sync_init_impl+0x78>
+	hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud);
+     f72:	0042      	lsls	r2, r0, #1
+     f74:	1812      	adds	r2, r2, r0
+     f76:	00d1      	lsls	r1, r2, #3
+     f78:	4b0f      	ldr	r3, [pc, #60]	; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+     f7a:	185b      	adds	r3, r3, r1
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+     f7c:	6a1a      	ldr	r2, [r3, #32]
+     f7e:	60e2      	str	r2, [r4, #12]
+
+	service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+     f80:	7eda      	ldrb	r2, [r3, #27]
+     f82:	2303      	movs	r3, #3
+     f84:	401a      	ands	r2, r3
+     f86:	81aa      	strh	r2, [r5, #12]
+	hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1);
+     f88:	3b02      	subs	r3, #2
+     f8a:	4293      	cmp	r3, r2
+     f8c:	419b      	sbcs	r3, r3
+     f8e:	425b      	negs	r3, r3
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+     f90:	6a62      	ldr	r2, [r4, #36]	; 0x24
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+     f92:	490a      	ldr	r1, [pc, #40]	; (fbc <_i2c_m_sync_init_impl+0xc8>)
+     f94:	400a      	ands	r2, r1
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+     f96:	039b      	lsls	r3, r3, #14
+     f98:	4313      	orrs	r3, r2
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+     f9a:	6263      	str	r3, [r4, #36]	; 0x24
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     f9c:	69e3      	ldr	r3, [r4, #28]
+     f9e:	075b      	lsls	r3, r3, #29
+     fa0:	d4fc      	bmi.n	f9c <_i2c_m_sync_init_impl+0xa8>
+
+	service->trise = _i2cms[i].trise;
+     fa2:	0043      	lsls	r3, r0, #1
+     fa4:	1818      	adds	r0, r3, r0
+     fa6:	00c2      	lsls	r2, r0, #3
+     fa8:	4b03      	ldr	r3, [pc, #12]	; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+     faa:	189b      	adds	r3, r3, r2
+     fac:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
+     fae:	81eb      	strh	r3, [r5, #14]
+
+	return ERR_NONE;
+}
+     fb0:	2000      	movs	r0, #0
+     fb2:	bd70      	pop	{r4, r5, r6, pc}
+     fb4:	00000ead 	.word	0x00000ead
+     fb8:	0000207c 	.word	0x0000207c
+     fbc:	ffffbfff 	.word	0xffffbfff
+
+00000fc0 <_sercom_i2c_sync_send_address>:
+{
+     fc0:	b570      	push	{r4, r5, r6, lr}
+     fc2:	0005      	movs	r5, r0
+	void *             hw    = i2c_dev->hw;
+     fc4:	6904      	ldr	r4, [r0, #16]
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+     fc6:	6823      	ldr	r3, [r4, #0]
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+     fc8:	0edb      	lsrs	r3, r3, #27
+     fca:	2601      	movs	r6, #1
+     fcc:	401e      	ands	r6, r3
+	ASSERT(i2c_dev);
+     fce:	1e43      	subs	r3, r0, #1
+     fd0:	4198      	sbcs	r0, r3
+     fd2:	b2c0      	uxtb	r0, r0
+     fd4:	4a8e      	ldr	r2, [pc, #568]	; (1210 <_sercom_i2c_sync_send_address+0x250>)
+     fd6:	498f      	ldr	r1, [pc, #572]	; (1214 <_sercom_i2c_sync_send_address+0x254>)
+     fd8:	4b8f      	ldr	r3, [pc, #572]	; (1218 <_sercom_i2c_sync_send_address+0x258>)
+     fda:	4798      	blx	r3
+	if (msg->len == 1 && sclsm) {
+     fdc:	686b      	ldr	r3, [r5, #4]
+     fde:	2b01      	cmp	r3, #1
+     fe0:	d04d      	beq.n	107e <_sercom_i2c_sync_send_address+0xbe>
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+     fe2:	6863      	ldr	r3, [r4, #4]
+     fe4:	4a8d      	ldr	r2, [pc, #564]	; (121c <_sercom_i2c_sync_send_address+0x25c>)
+     fe6:	4013      	ands	r3, r2
+     fe8:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+     fea:	69e3      	ldr	r3, [r4, #28]
+     fec:	075b      	lsls	r3, r3, #29
+     fee:	d4fc      	bmi.n	fea <_sercom_i2c_sync_send_address+0x2a>
+	if (msg->addr & I2C_M_TEN) {
+     ff0:	882b      	ldrh	r3, [r5, #0]
+     ff2:	055a      	lsls	r2, r3, #21
+     ff4:	d54e      	bpl.n	1094 <_sercom_i2c_sync_send_address+0xd4>
+		if (msg->flags & I2C_M_RD) {
+     ff6:	886a      	ldrh	r2, [r5, #2]
+     ff8:	07d2      	lsls	r2, r2, #31
+     ffa:	d504      	bpl.n	1006 <_sercom_i2c_sync_send_address+0x46>
+			msg->flags |= I2C_M_TEN;
+     ffc:	886a      	ldrh	r2, [r5, #2]
+     ffe:	2180      	movs	r1, #128	; 0x80
+    1000:	00c9      	lsls	r1, r1, #3
+    1002:	430a      	orrs	r2, r1
+    1004:	806a      	strh	r2, [r5, #2]
+		                              ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+    1006:	005b      	lsls	r3, r3, #1
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+    1008:	4a85      	ldr	r2, [pc, #532]	; (1220 <_sercom_i2c_sync_send_address+0x260>)
+    100a:	401a      	ands	r2, r3
+    100c:	69e3      	ldr	r3, [r4, #28]
+    100e:	075b      	lsls	r3, r3, #29
+    1010:	d4fc      	bmi.n	100c <_sercom_i2c_sync_send_address+0x4c>
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+    1012:	6a63      	ldr	r3, [r4, #36]	; 0x24
+    1014:	2180      	movs	r1, #128	; 0x80
+    1016:	01c9      	lsls	r1, r1, #7
+    1018:	400b      	ands	r3, r1
+    101a:	4313      	orrs	r3, r2
+		hri_sercomi2cm_write_ADDR_reg(hw,
+    101c:	2280      	movs	r2, #128	; 0x80
+    101e:	0212      	lsls	r2, r2, #8
+    1020:	4313      	orrs	r3, r2
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+    1022:	6263      	str	r3, [r4, #36]	; 0x24
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1024:	69e3      	ldr	r3, [r4, #28]
+    1026:	075b      	lsls	r3, r3, #29
+    1028:	d4fc      	bmi.n	1024 <_sercom_i2c_sync_send_address+0x64>
+	void *   hw      = i2c_dev->hw;
+    102a:	692e      	ldr	r6, [r5, #16]
+	uint32_t timeout = 65535;
+    102c:	4a7d      	ldr	r2, [pc, #500]	; (1224 <_sercom_i2c_sync_send_address+0x264>)
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+    102e:	7e33      	ldrb	r3, [r6, #24]
+    1030:	b2db      	uxtb	r3, r3
+		*flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+    1032:	0018      	movs	r0, r3
+		if (timeout-- == 0) {
+    1034:	1e51      	subs	r1, r2, #1
+    1036:	2a00      	cmp	r2, #0
+    1038:	d002      	beq.n	1040 <_sercom_i2c_sync_send_address+0x80>
+    103a:	000a      	movs	r2, r1
+	} while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+    103c:	079b      	lsls	r3, r3, #30
+    103e:	d0f6      	beq.n	102e <_sercom_i2c_sync_send_address+0x6e>
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+    1040:	6823      	ldr	r3, [r4, #0]
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+    1042:	0edb      	lsrs	r3, r3, #27
+    1044:	2201      	movs	r2, #1
+    1046:	401a      	ands	r2, r3
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1048:	69e3      	ldr	r3, [r4, #28]
+    104a:	075b      	lsls	r3, r3, #29
+    104c:	d4fc      	bmi.n	1048 <_sercom_i2c_sync_send_address+0x88>
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+    104e:	8b63      	ldrh	r3, [r4, #26]
+    1050:	b29b      	uxth	r3, r3
+	if (flags & MB_FLAG) {
+    1052:	07c1      	lsls	r1, r0, #31
+    1054:	d400      	bmi.n	1058 <_sercom_i2c_sync_send_address+0x98>
+    1056:	e08f      	b.n	1178 <_sercom_i2c_sync_send_address+0x1b8>
+		if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+    1058:	079a      	lsls	r2, r3, #30
+    105a:	d52f      	bpl.n	10bc <_sercom_i2c_sync_send_address+0xfc>
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+    105c:	2201      	movs	r2, #1
+    105e:	7622      	strb	r2, [r4, #24]
+			msg->flags |= I2C_M_FAIL;
+    1060:	886a      	ldrh	r2, [r5, #2]
+    1062:	2180      	movs	r1, #128	; 0x80
+    1064:	0149      	lsls	r1, r1, #5
+    1066:	430a      	orrs	r2, r1
+    1068:	806a      	strh	r2, [r5, #2]
+			msg->flags &= ~I2C_M_BUSY;
+    106a:	886a      	ldrh	r2, [r5, #2]
+    106c:	496e      	ldr	r1, [pc, #440]	; (1228 <_sercom_i2c_sync_send_address+0x268>)
+    106e:	400a      	ands	r2, r1
+    1070:	806a      	strh	r2, [r5, #2]
+			if (status & SERCOM_I2CM_STATUS_BUSERR) {
+    1072:	07db      	lsls	r3, r3, #31
+    1074:	d400      	bmi.n	1078 <_sercom_i2c_sync_send_address+0xb8>
+    1076:	e0c6      	b.n	1206 <_sercom_i2c_sync_send_address+0x246>
+				return I2C_ERR_BUS;
+    1078:	2005      	movs	r0, #5
+    107a:	4240      	negs	r0, r0
+    107c:	e0a2      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+	if (msg->len == 1 && sclsm) {
+    107e:	2e00      	cmp	r6, #0
+    1080:	d0af      	beq.n	fe2 <_sercom_i2c_sync_send_address+0x22>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    1082:	6862      	ldr	r2, [r4, #4]
+    1084:	2380      	movs	r3, #128	; 0x80
+    1086:	02db      	lsls	r3, r3, #11
+    1088:	4313      	orrs	r3, r2
+    108a:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    108c:	69e3      	ldr	r3, [r4, #28]
+    108e:	075b      	lsls	r3, r3, #29
+    1090:	d4fc      	bmi.n	108c <_sercom_i2c_sync_send_address+0xcc>
+    1092:	e7ad      	b.n	ff0 <_sercom_i2c_sync_send_address+0x30>
+		                              ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+    1094:	005b      	lsls	r3, r3, #1
+    1096:	22ff      	movs	r2, #255	; 0xff
+    1098:	4013      	ands	r3, r2
+    109a:	886a      	ldrh	r2, [r5, #2]
+    109c:	2101      	movs	r1, #1
+    109e:	400a      	ands	r2, r1
+    10a0:	431a      	orrs	r2, r3
+    10a2:	69e3      	ldr	r3, [r4, #28]
+    10a4:	075b      	lsls	r3, r3, #29
+    10a6:	d4fc      	bmi.n	10a2 <_sercom_i2c_sync_send_address+0xe2>
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+    10a8:	6a63      	ldr	r3, [r4, #36]	; 0x24
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+    10aa:	2180      	movs	r1, #128	; 0x80
+    10ac:	01c9      	lsls	r1, r1, #7
+    10ae:	400b      	ands	r3, r1
+		hri_sercomi2cm_write_ADDR_reg(hw,
+    10b0:	4313      	orrs	r3, r2
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+    10b2:	6263      	str	r3, [r4, #36]	; 0x24
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    10b4:	69e3      	ldr	r3, [r4, #28]
+    10b6:	075b      	lsls	r3, r3, #29
+    10b8:	d4fc      	bmi.n	10b4 <_sercom_i2c_sync_send_address+0xf4>
+    10ba:	e7b6      	b.n	102a <_sercom_i2c_sync_send_address+0x6a>
+			if (status & SERCOM_I2CM_STATUS_RXNACK) {
+    10bc:	075b      	lsls	r3, r3, #29
+    10be:	d41b      	bmi.n	10f8 <_sercom_i2c_sync_send_address+0x138>
+			if (msg->flags & I2C_M_TEN) {
+    10c0:	886b      	ldrh	r3, [r5, #2]
+    10c2:	055b      	lsls	r3, r3, #21
+    10c4:	d534      	bpl.n	1130 <_sercom_i2c_sync_send_address+0x170>
+				                              ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+    10c6:	882a      	ldrh	r2, [r5, #0]
+    10c8:	1212      	asrs	r2, r2, #8
+    10ca:	0052      	lsls	r2, r2, #1
+				                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+    10cc:	2306      	movs	r3, #6
+    10ce:	401a      	ands	r2, r3
+    10d0:	69e3      	ldr	r3, [r4, #28]
+    10d2:	075b      	lsls	r3, r3, #29
+    10d4:	d4fc      	bmi.n	10d0 <_sercom_i2c_sync_send_address+0x110>
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+    10d6:	6a63      	ldr	r3, [r4, #36]	; 0x24
+    10d8:	2180      	movs	r1, #128	; 0x80
+    10da:	01c9      	lsls	r1, r1, #7
+    10dc:	400b      	ands	r3, r1
+    10de:	4313      	orrs	r3, r2
+				hri_sercomi2cm_write_ADDR_reg(hw,
+    10e0:	22f1      	movs	r2, #241	; 0xf1
+    10e2:	4313      	orrs	r3, r2
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+    10e4:	6263      	str	r3, [r4, #36]	; 0x24
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    10e6:	69e3      	ldr	r3, [r4, #28]
+    10e8:	075b      	lsls	r3, r3, #29
+    10ea:	d4fc      	bmi.n	10e6 <_sercom_i2c_sync_send_address+0x126>
+				msg->flags &= ~I2C_M_TEN;
+    10ec:	886b      	ldrh	r3, [r5, #2]
+    10ee:	4a4f      	ldr	r2, [pc, #316]	; (122c <_sercom_i2c_sync_send_address+0x26c>)
+    10f0:	4013      	ands	r3, r2
+    10f2:	806b      	strh	r3, [r5, #2]
+				return I2C_OK;
+    10f4:	2000      	movs	r0, #0
+    10f6:	e065      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+				if (msg->len > 0) {
+    10f8:	686b      	ldr	r3, [r5, #4]
+    10fa:	2b00      	cmp	r3, #0
+    10fc:	dd04      	ble.n	1108 <_sercom_i2c_sync_send_address+0x148>
+					msg->flags |= I2C_M_FAIL;
+    10fe:	886b      	ldrh	r3, [r5, #2]
+    1100:	2280      	movs	r2, #128	; 0x80
+    1102:	0152      	lsls	r2, r2, #5
+    1104:	4313      	orrs	r3, r2
+    1106:	806b      	strh	r3, [r5, #2]
+				if (msg->flags & I2C_M_STOP) {
+    1108:	886b      	ldrh	r3, [r5, #2]
+    110a:	b21b      	sxth	r3, r3
+    110c:	2b00      	cmp	r3, #0
+    110e:	db06      	blt.n	111e <_sercom_i2c_sync_send_address+0x15e>
+				msg->flags &= ~I2C_M_BUSY;
+    1110:	886b      	ldrh	r3, [r5, #2]
+    1112:	4a45      	ldr	r2, [pc, #276]	; (1228 <_sercom_i2c_sync_send_address+0x268>)
+    1114:	4013      	ands	r3, r2
+    1116:	806b      	strh	r3, [r5, #2]
+				return I2C_NACK;
+    1118:	2002      	movs	r0, #2
+    111a:	4240      	negs	r0, r0
+    111c:	e052      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    111e:	6862      	ldr	r2, [r4, #4]
+    1120:	23c0      	movs	r3, #192	; 0xc0
+    1122:	029b      	lsls	r3, r3, #10
+    1124:	4313      	orrs	r3, r2
+    1126:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1128:	69e3      	ldr	r3, [r4, #28]
+    112a:	075b      	lsls	r3, r3, #29
+    112c:	d4fc      	bmi.n	1128 <_sercom_i2c_sync_send_address+0x168>
+    112e:	e7ef      	b.n	1110 <_sercom_i2c_sync_send_address+0x150>
+			if (msg->len == 0) {
+    1130:	6868      	ldr	r0, [r5, #4]
+    1132:	2800      	cmp	r0, #0
+    1134:	d111      	bne.n	115a <_sercom_i2c_sync_send_address+0x19a>
+				if (msg->flags & I2C_M_STOP) {
+    1136:	886b      	ldrh	r3, [r5, #2]
+    1138:	b21b      	sxth	r3, r3
+    113a:	2b00      	cmp	r3, #0
+    113c:	db04      	blt.n	1148 <_sercom_i2c_sync_send_address+0x188>
+				msg->flags &= ~I2C_M_BUSY;
+    113e:	886b      	ldrh	r3, [r5, #2]
+    1140:	4a39      	ldr	r2, [pc, #228]	; (1228 <_sercom_i2c_sync_send_address+0x268>)
+    1142:	4013      	ands	r3, r2
+    1144:	806b      	strh	r3, [r5, #2]
+    1146:	e03d      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    1148:	6862      	ldr	r2, [r4, #4]
+    114a:	23c0      	movs	r3, #192	; 0xc0
+    114c:	029b      	lsls	r3, r3, #10
+    114e:	4313      	orrs	r3, r2
+    1150:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1152:	69e3      	ldr	r3, [r4, #28]
+    1154:	075b      	lsls	r3, r3, #29
+    1156:	d4fc      	bmi.n	1152 <_sercom_i2c_sync_send_address+0x192>
+    1158:	e7f1      	b.n	113e <_sercom_i2c_sync_send_address+0x17e>
+				hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+    115a:	68ab      	ldr	r3, [r5, #8]
+    115c:	781a      	ldrb	r2, [r3, #0]
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+    115e:	2328      	movs	r3, #40	; 0x28
+    1160:	54e2      	strb	r2, [r4, r3]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1162:	69e3      	ldr	r3, [r4, #28]
+    1164:	075b      	lsls	r3, r3, #29
+    1166:	d4fc      	bmi.n	1162 <_sercom_i2c_sync_send_address+0x1a2>
+				msg->buffer++;
+    1168:	68ab      	ldr	r3, [r5, #8]
+    116a:	3301      	adds	r3, #1
+    116c:	60ab      	str	r3, [r5, #8]
+				msg->len--;
+    116e:	686b      	ldr	r3, [r5, #4]
+    1170:	3b01      	subs	r3, #1
+    1172:	606b      	str	r3, [r5, #4]
+			return I2C_OK;
+    1174:	2000      	movs	r0, #0
+    1176:	e025      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+	} else if (flags & SB_FLAG) {
+    1178:	0781      	lsls	r1, r0, #30
+    117a:	d547      	bpl.n	120c <_sercom_i2c_sync_send_address+0x24c>
+		if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+    117c:	6869      	ldr	r1, [r5, #4]
+    117e:	2900      	cmp	r1, #0
+    1180:	d03c      	beq.n	11fc <_sercom_i2c_sync_send_address+0x23c>
+    1182:	075b      	lsls	r3, r3, #29
+    1184:	d43a      	bmi.n	11fc <_sercom_i2c_sync_send_address+0x23c>
+			msg->len--;
+    1186:	3901      	subs	r1, #1
+    1188:	6069      	str	r1, [r5, #4]
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+    118a:	2900      	cmp	r1, #0
+    118c:	d101      	bne.n	1192 <_sercom_i2c_sync_send_address+0x1d2>
+    118e:	2a00      	cmp	r2, #0
+    1190:	d01b      	beq.n	11ca <_sercom_i2c_sync_send_address+0x20a>
+    1192:	2901      	cmp	r1, #1
+    1194:	d017      	beq.n	11c6 <_sercom_i2c_sync_send_address+0x206>
+			if (msg->len == 0) {
+    1196:	686b      	ldr	r3, [r5, #4]
+    1198:	2b00      	cmp	r3, #0
+    119a:	d107      	bne.n	11ac <_sercom_i2c_sync_send_address+0x1ec>
+				if (msg->flags & I2C_M_STOP) {
+    119c:	886b      	ldrh	r3, [r5, #2]
+    119e:	b21b      	sxth	r3, r3
+    11a0:	2b00      	cmp	r3, #0
+    11a2:	db1b      	blt.n	11dc <_sercom_i2c_sync_send_address+0x21c>
+				msg->flags &= ~I2C_M_BUSY;
+    11a4:	886b      	ldrh	r3, [r5, #2]
+    11a6:	4a20      	ldr	r2, [pc, #128]	; (1228 <_sercom_i2c_sync_send_address+0x268>)
+    11a8:	4013      	ands	r3, r2
+    11aa:	806b      	strh	r3, [r5, #2]
+			*msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+    11ac:	68aa      	ldr	r2, [r5, #8]
+    11ae:	1c53      	adds	r3, r2, #1
+    11b0:	60ab      	str	r3, [r5, #8]
+    11b2:	69e3      	ldr	r3, [r4, #28]
+    11b4:	075b      	lsls	r3, r3, #29
+    11b6:	d4fc      	bmi.n	11b2 <_sercom_i2c_sync_send_address+0x1f2>
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+    11b8:	2328      	movs	r3, #40	; 0x28
+    11ba:	5ce3      	ldrb	r3, [r4, r3]
+    11bc:	7013      	strb	r3, [r2, #0]
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+    11be:	2302      	movs	r3, #2
+    11c0:	7623      	strb	r3, [r4, #24]
+	return I2C_OK;
+    11c2:	2000      	movs	r0, #0
+}
+    11c4:	bd70      	pop	{r4, r5, r6, pc}
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+    11c6:	2a00      	cmp	r2, #0
+    11c8:	d0e5      	beq.n	1196 <_sercom_i2c_sync_send_address+0x1d6>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    11ca:	6862      	ldr	r2, [r4, #4]
+    11cc:	2380      	movs	r3, #128	; 0x80
+    11ce:	02db      	lsls	r3, r3, #11
+    11d0:	4313      	orrs	r3, r2
+    11d2:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    11d4:	69e3      	ldr	r3, [r4, #28]
+    11d6:	075b      	lsls	r3, r3, #29
+    11d8:	d4fc      	bmi.n	11d4 <_sercom_i2c_sync_send_address+0x214>
+    11da:	e7dc      	b.n	1196 <_sercom_i2c_sync_send_address+0x1d6>
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+    11dc:	6863      	ldr	r3, [r4, #4]
+    11de:	4a12      	ldr	r2, [pc, #72]	; (1228 <_sercom_i2c_sync_send_address+0x268>)
+    11e0:	4013      	ands	r3, r2
+    11e2:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    11e4:	69e3      	ldr	r3, [r4, #28]
+    11e6:	075b      	lsls	r3, r3, #29
+    11e8:	d4fc      	bmi.n	11e4 <_sercom_i2c_sync_send_address+0x224>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    11ea:	6862      	ldr	r2, [r4, #4]
+    11ec:	23c0      	movs	r3, #192	; 0xc0
+    11ee:	029b      	lsls	r3, r3, #10
+    11f0:	4313      	orrs	r3, r2
+    11f2:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    11f4:	69e3      	ldr	r3, [r4, #28]
+    11f6:	075b      	lsls	r3, r3, #29
+    11f8:	d4fc      	bmi.n	11f4 <_sercom_i2c_sync_send_address+0x234>
+    11fa:	e7d3      	b.n	11a4 <_sercom_i2c_sync_send_address+0x1e4>
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+    11fc:	2302      	movs	r3, #2
+    11fe:	7623      	strb	r3, [r4, #24]
+			return I2C_NACK;
+    1200:	2002      	movs	r0, #2
+    1202:	4240      	negs	r0, r0
+    1204:	e7de      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+			return I2C_ERR_BAD_ADDRESS;
+    1206:	2004      	movs	r0, #4
+    1208:	4240      	negs	r0, r0
+    120a:	e7db      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+	return I2C_OK;
+    120c:	2000      	movs	r0, #0
+	return _sercom_i2c_sync_analyse_flags(hw, flags, msg);
+    120e:	e7d9      	b.n	11c4 <_sercom_i2c_sync_send_address+0x204>
+    1210:	00000594 	.word	0x00000594
+    1214:	000020cc 	.word	0x000020cc
+    1218:	00000a69 	.word	0x00000a69
+    121c:	fffbffff 	.word	0xfffbffff
+    1220:	000007fe 	.word	0x000007fe
+    1224:	0000ffff 	.word	0x0000ffff
+    1228:	fffffeff 	.word	0xfffffeff
+    122c:	fffffbff 	.word	0xfffffbff
+
+00001230 <_i2c_m_sync_init>:
+{
+    1230:	b570      	push	{r4, r5, r6, lr}
+    1232:	0004      	movs	r4, r0
+    1234:	000d      	movs	r5, r1
+	ASSERT(i2c_dev);
+    1236:	1e43      	subs	r3, r0, #1
+    1238:	4198      	sbcs	r0, r3
+    123a:	b2c0      	uxtb	r0, r0
+    123c:	4a04      	ldr	r2, [pc, #16]	; (1250 <_i2c_m_sync_init+0x20>)
+    123e:	4905      	ldr	r1, [pc, #20]	; (1254 <_i2c_m_sync_init+0x24>)
+    1240:	4b05      	ldr	r3, [pc, #20]	; (1258 <_i2c_m_sync_init+0x28>)
+    1242:	4798      	blx	r3
+	i2c_dev->hw = hw;
+    1244:	6125      	str	r5, [r4, #16]
+	return _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+    1246:	0029      	movs	r1, r5
+    1248:	0020      	movs	r0, r4
+    124a:	4b04      	ldr	r3, [pc, #16]	; (125c <_i2c_m_sync_init+0x2c>)
+    124c:	4798      	blx	r3
+}
+    124e:	bd70      	pop	{r4, r5, r6, pc}
+    1250:	00000507 	.word	0x00000507
+    1254:	000020cc 	.word	0x000020cc
+    1258:	00000a69 	.word	0x00000a69
+    125c:	00000ef5 	.word	0x00000ef5
+
+00001260 <_i2c_m_sync_enable>:
+{
+    1260:	b570      	push	{r4, r5, r6, lr}
+    1262:	0004      	movs	r4, r0
+	ASSERT(i2c_dev);
+    1264:	4d19      	ldr	r5, [pc, #100]	; (12cc <_i2c_m_sync_enable+0x6c>)
+    1266:	1e43      	subs	r3, r0, #1
+    1268:	4198      	sbcs	r0, r3
+    126a:	b2c0      	uxtb	r0, r0
+    126c:	4a18      	ldr	r2, [pc, #96]	; (12d0 <_i2c_m_sync_enable+0x70>)
+    126e:	0029      	movs	r1, r5
+    1270:	4e18      	ldr	r6, [pc, #96]	; (12d4 <_i2c_m_sync_enable+0x74>)
+    1272:	47b0      	blx	r6
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+    1274:	6924      	ldr	r4, [r4, #16]
+	ASSERT(hw);
+    1276:	0020      	movs	r0, r4
+    1278:	1e43      	subs	r3, r0, #1
+    127a:	4198      	sbcs	r0, r3
+    127c:	b2c0      	uxtb	r0, r0
+    127e:	4a16      	ldr	r2, [pc, #88]	; (12d8 <_i2c_m_sync_enable+0x78>)
+    1280:	0029      	movs	r1, r5
+    1282:	47b0      	blx	r6
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+    1284:	6823      	ldr	r3, [r4, #0]
+    1286:	2202      	movs	r2, #2
+    1288:	4313      	orrs	r3, r2
+    128a:	6023      	str	r3, [r4, #0]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    128c:	69e3      	ldr	r3, [r4, #28]
+    128e:	079b      	lsls	r3, r3, #30
+    1290:	d1fc      	bne.n	128c <_i2c_m_sync_enable+0x2c>
+    1292:	2004      	movs	r0, #4
+    1294:	4911      	ldr	r1, [pc, #68]	; (12dc <_i2c_m_sync_enable+0x7c>)
+    1296:	69e3      	ldr	r3, [r4, #28]
+    1298:	075b      	lsls	r3, r3, #29
+    129a:	d4fc      	bmi.n	1296 <_i2c_m_sync_enable+0x36>
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+    129c:	8b62      	ldrh	r2, [r4, #26]
+    129e:	0912      	lsrs	r2, r2, #4
+    12a0:	2303      	movs	r3, #3
+    12a2:	4013      	ands	r3, r2
+	while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) {
+    12a4:	2b01      	cmp	r3, #1
+    12a6:	d00b      	beq.n	12c0 <_i2c_m_sync_enable+0x60>
+		timeout--;
+    12a8:	3901      	subs	r1, #1
+		if (timeout <= 0) {
+    12aa:	2900      	cmp	r1, #0
+    12ac:	dcf3      	bgt.n	1296 <_i2c_m_sync_enable+0x36>
+			if (--timeout_attempt)
+    12ae:	3801      	subs	r0, #1
+    12b0:	2800      	cmp	r0, #0
+    12b2:	d007      	beq.n	12c4 <_i2c_m_sync_enable+0x64>
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+    12b4:	2310      	movs	r3, #16
+    12b6:	8363      	strh	r3, [r4, #26]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    12b8:	69e3      	ldr	r3, [r4, #28]
+    12ba:	075b      	lsls	r3, r3, #29
+    12bc:	d4fc      	bmi.n	12b8 <_i2c_m_sync_enable+0x58>
+    12be:	e7e9      	b.n	1294 <_i2c_m_sync_enable+0x34>
+	return ERR_NONE;
+    12c0:	2000      	movs	r0, #0
+}
+    12c2:	bd70      	pop	{r4, r5, r6, pc}
+				return I2C_ERR_BUSY;
+    12c4:	2006      	movs	r0, #6
+    12c6:	4240      	negs	r0, r0
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+    12c8:	e7fb      	b.n	12c2 <_i2c_m_sync_enable+0x62>
+    12ca:	46c0      	nop			; (mov r8, r8)
+    12cc:	000020cc 	.word	0x000020cc
+    12d0:	00000524 	.word	0x00000524
+    12d4:	00000a69 	.word	0x00000a69
+    12d8:	000005f4 	.word	0x000005f4
+    12dc:	0000ffff 	.word	0x0000ffff
+
+000012e0 <_i2c_m_sync_transfer>:
+{
+    12e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    12e2:	0005      	movs	r5, r0
+    12e4:	000e      	movs	r6, r1
+	void *   hw = i2c_dev->hw;
+    12e6:	6904      	ldr	r4, [r0, #16]
+	ASSERT(i2c_dev);
+    12e8:	1e43      	subs	r3, r0, #1
+    12ea:	4198      	sbcs	r0, r3
+    12ec:	b2c0      	uxtb	r0, r0
+    12ee:	4a93      	ldr	r2, [pc, #588]	; (153c <_i2c_m_sync_transfer+0x25c>)
+    12f0:	4993      	ldr	r1, [pc, #588]	; (1540 <_i2c_m_sync_transfer+0x260>)
+    12f2:	4f94      	ldr	r7, [pc, #592]	; (1544 <_i2c_m_sync_transfer+0x264>)
+    12f4:	47b8      	blx	r7
+	ASSERT(i2c_dev->hw);
+    12f6:	6928      	ldr	r0, [r5, #16]
+    12f8:	1e43      	subs	r3, r0, #1
+    12fa:	4198      	sbcs	r0, r3
+    12fc:	b2c0      	uxtb	r0, r0
+    12fe:	22b8      	movs	r2, #184	; 0xb8
+    1300:	00d2      	lsls	r2, r2, #3
+    1302:	498f      	ldr	r1, [pc, #572]	; (1540 <_i2c_m_sync_transfer+0x260>)
+    1304:	47b8      	blx	r7
+	ASSERT(msg);
+    1306:	0030      	movs	r0, r6
+    1308:	1e43      	subs	r3, r0, #1
+    130a:	4198      	sbcs	r0, r3
+    130c:	b2c0      	uxtb	r0, r0
+    130e:	4a8e      	ldr	r2, [pc, #568]	; (1548 <_i2c_m_sync_transfer+0x268>)
+    1310:	498b      	ldr	r1, [pc, #556]	; (1540 <_i2c_m_sync_transfer+0x260>)
+    1312:	47b8      	blx	r7
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+    1314:	886b      	ldrh	r3, [r5, #2]
+    1316:	05db      	lsls	r3, r3, #23
+    1318:	d500      	bpl.n	131c <_i2c_m_sync_transfer+0x3c>
+    131a:	e10b      	b.n	1534 <_i2c_m_sync_transfer+0x254>
+	msg->flags |= I2C_M_BUSY;
+    131c:	8872      	ldrh	r2, [r6, #2]
+    131e:	2380      	movs	r3, #128	; 0x80
+    1320:	005b      	lsls	r3, r3, #1
+    1322:	469c      	mov	ip, r3
+    1324:	431a      	orrs	r2, r3
+    1326:	8072      	strh	r2, [r6, #2]
+	i2c_dev->service.msg = *msg;
+    1328:	002a      	movs	r2, r5
+    132a:	0031      	movs	r1, r6
+    132c:	c989      	ldmia	r1!, {r0, r3, r7}
+    132e:	c289      	stmia	r2!, {r0, r3, r7}
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+    1330:	6862      	ldr	r2, [r4, #4]
+    1332:	4663      	mov	r3, ip
+    1334:	4313      	orrs	r3, r2
+    1336:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1338:	69e3      	ldr	r3, [r4, #28]
+    133a:	075b      	lsls	r3, r3, #29
+    133c:	d4fc      	bmi.n	1338 <_i2c_m_sync_transfer+0x58>
+	ret = _sercom_i2c_sync_send_address(i2c_dev);
+    133e:	0028      	movs	r0, r5
+    1340:	4b82      	ldr	r3, [pc, #520]	; (154c <_i2c_m_sync_transfer+0x26c>)
+    1342:	4798      	blx	r3
+	if (ret) {
+    1344:	2800      	cmp	r0, #0
+    1346:	d100      	bne.n	134a <_i2c_m_sync_transfer+0x6a>
+    1348:	e09d      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+		i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+    134a:	886b      	ldrh	r3, [r5, #2]
+    134c:	4a80      	ldr	r2, [pc, #512]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    134e:	4013      	ands	r3, r2
+    1350:	806b      	strh	r3, [r5, #2]
+}
+    1352:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+			return I2C_ERR_BUS;
+    1354:	2005      	movs	r0, #5
+    1356:	4240      	negs	r0, r0
+    1358:	e0a6      	b.n	14a8 <_i2c_m_sync_transfer+0x1c8>
+			if (msg->flags & I2C_M_STOP) {
+    135a:	8873      	ldrh	r3, [r6, #2]
+    135c:	b21b      	sxth	r3, r3
+    135e:	2b00      	cmp	r3, #0
+    1360:	db04      	blt.n	136c <_i2c_m_sync_transfer+0x8c>
+			i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+    1362:	886b      	ldrh	r3, [r5, #2]
+    1364:	4a7a      	ldr	r2, [pc, #488]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    1366:	4013      	ands	r3, r2
+    1368:	806b      	strh	r3, [r5, #2]
+			return ret;
+    136a:	e7f2      	b.n	1352 <_i2c_m_sync_transfer+0x72>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    136c:	6862      	ldr	r2, [r4, #4]
+    136e:	23c0      	movs	r3, #192	; 0xc0
+    1370:	029b      	lsls	r3, r3, #10
+    1372:	4313      	orrs	r3, r2
+    1374:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1376:	69e3      	ldr	r3, [r4, #28]
+    1378:	075b      	lsls	r3, r3, #29
+    137a:	d4fc      	bmi.n	1376 <_i2c_m_sync_transfer+0x96>
+    137c:	e7f1      	b.n	1362 <_i2c_m_sync_transfer+0x82>
+			if (status & SERCOM_I2CM_STATUS_RXNACK) {
+    137e:	0753      	lsls	r3, r2, #29
+    1380:	d41b      	bmi.n	13ba <_i2c_m_sync_transfer+0xda>
+			if (msg->flags & I2C_M_TEN) {
+    1382:	886b      	ldrh	r3, [r5, #2]
+    1384:	055b      	lsls	r3, r3, #21
+    1386:	d534      	bpl.n	13f2 <_i2c_m_sync_transfer+0x112>
+				                              ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+    1388:	882a      	ldrh	r2, [r5, #0]
+    138a:	1212      	asrs	r2, r2, #8
+    138c:	0052      	lsls	r2, r2, #1
+				                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+    138e:	2306      	movs	r3, #6
+    1390:	401a      	ands	r2, r3
+    1392:	69e3      	ldr	r3, [r4, #28]
+    1394:	075b      	lsls	r3, r3, #29
+    1396:	d4fc      	bmi.n	1392 <_i2c_m_sync_transfer+0xb2>
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+    1398:	6a63      	ldr	r3, [r4, #36]	; 0x24
+    139a:	2180      	movs	r1, #128	; 0x80
+    139c:	01c9      	lsls	r1, r1, #7
+    139e:	400b      	ands	r3, r1
+    13a0:	4313      	orrs	r3, r2
+				hri_sercomi2cm_write_ADDR_reg(hw,
+    13a2:	22f1      	movs	r2, #241	; 0xf1
+    13a4:	4313      	orrs	r3, r2
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+    13a6:	6263      	str	r3, [r4, #36]	; 0x24
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    13a8:	69e3      	ldr	r3, [r4, #28]
+    13aa:	075b      	lsls	r3, r3, #29
+    13ac:	d4fc      	bmi.n	13a8 <_i2c_m_sync_transfer+0xc8>
+				msg->flags &= ~I2C_M_TEN;
+    13ae:	886b      	ldrh	r3, [r5, #2]
+    13b0:	4a68      	ldr	r2, [pc, #416]	; (1554 <_i2c_m_sync_transfer+0x274>)
+    13b2:	4013      	ands	r3, r2
+    13b4:	806b      	strh	r3, [r5, #2]
+				return I2C_OK;
+    13b6:	2000      	movs	r0, #0
+    13b8:	e065      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+				if (msg->len > 0) {
+    13ba:	686b      	ldr	r3, [r5, #4]
+    13bc:	2b00      	cmp	r3, #0
+    13be:	dd04      	ble.n	13ca <_i2c_m_sync_transfer+0xea>
+					msg->flags |= I2C_M_FAIL;
+    13c0:	886b      	ldrh	r3, [r5, #2]
+    13c2:	2280      	movs	r2, #128	; 0x80
+    13c4:	0152      	lsls	r2, r2, #5
+    13c6:	4313      	orrs	r3, r2
+    13c8:	806b      	strh	r3, [r5, #2]
+				if (msg->flags & I2C_M_STOP) {
+    13ca:	886b      	ldrh	r3, [r5, #2]
+    13cc:	b21b      	sxth	r3, r3
+    13ce:	2b00      	cmp	r3, #0
+    13d0:	db06      	blt.n	13e0 <_i2c_m_sync_transfer+0x100>
+				msg->flags &= ~I2C_M_BUSY;
+    13d2:	886b      	ldrh	r3, [r5, #2]
+    13d4:	4a5e      	ldr	r2, [pc, #376]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    13d6:	4013      	ands	r3, r2
+    13d8:	806b      	strh	r3, [r5, #2]
+				return I2C_NACK;
+    13da:	2002      	movs	r0, #2
+    13dc:	4240      	negs	r0, r0
+    13de:	e052      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    13e0:	6862      	ldr	r2, [r4, #4]
+    13e2:	23c0      	movs	r3, #192	; 0xc0
+    13e4:	029b      	lsls	r3, r3, #10
+    13e6:	4313      	orrs	r3, r2
+    13e8:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    13ea:	69e3      	ldr	r3, [r4, #28]
+    13ec:	075b      	lsls	r3, r3, #29
+    13ee:	d4fc      	bmi.n	13ea <_i2c_m_sync_transfer+0x10a>
+    13f0:	e7ef      	b.n	13d2 <_i2c_m_sync_transfer+0xf2>
+			if (msg->len == 0) {
+    13f2:	6868      	ldr	r0, [r5, #4]
+    13f4:	2800      	cmp	r0, #0
+    13f6:	d111      	bne.n	141c <_i2c_m_sync_transfer+0x13c>
+				if (msg->flags & I2C_M_STOP) {
+    13f8:	886b      	ldrh	r3, [r5, #2]
+    13fa:	b21b      	sxth	r3, r3
+    13fc:	2b00      	cmp	r3, #0
+    13fe:	db04      	blt.n	140a <_i2c_m_sync_transfer+0x12a>
+				msg->flags &= ~I2C_M_BUSY;
+    1400:	886b      	ldrh	r3, [r5, #2]
+    1402:	4a53      	ldr	r2, [pc, #332]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    1404:	4013      	ands	r3, r2
+    1406:	806b      	strh	r3, [r5, #2]
+    1408:	e03d      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    140a:	6862      	ldr	r2, [r4, #4]
+    140c:	23c0      	movs	r3, #192	; 0xc0
+    140e:	029b      	lsls	r3, r3, #10
+    1410:	4313      	orrs	r3, r2
+    1412:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1414:	69e3      	ldr	r3, [r4, #28]
+    1416:	075b      	lsls	r3, r3, #29
+    1418:	d4fc      	bmi.n	1414 <_i2c_m_sync_transfer+0x134>
+    141a:	e7f1      	b.n	1400 <_i2c_m_sync_transfer+0x120>
+				hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+    141c:	68ab      	ldr	r3, [r5, #8]
+    141e:	781a      	ldrb	r2, [r3, #0]
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+    1420:	2328      	movs	r3, #40	; 0x28
+    1422:	54e2      	strb	r2, [r4, r3]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1424:	69e3      	ldr	r3, [r4, #28]
+    1426:	075b      	lsls	r3, r3, #29
+    1428:	d4fc      	bmi.n	1424 <_i2c_m_sync_transfer+0x144>
+				msg->buffer++;
+    142a:	68ab      	ldr	r3, [r5, #8]
+    142c:	3301      	adds	r3, #1
+    142e:	60ab      	str	r3, [r5, #8]
+				msg->len--;
+    1430:	686b      	ldr	r3, [r5, #4]
+    1432:	3b01      	subs	r3, #1
+    1434:	606b      	str	r3, [r5, #4]
+			return I2C_OK;
+    1436:	2000      	movs	r0, #0
+    1438:	e025      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+	} else if (flags & SB_FLAG) {
+    143a:	07bb      	lsls	r3, r7, #30
+    143c:	d578      	bpl.n	1530 <_i2c_m_sync_transfer+0x250>
+		if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+    143e:	686b      	ldr	r3, [r5, #4]
+    1440:	2b00      	cmp	r3, #0
+    1442:	d06d      	beq.n	1520 <_i2c_m_sync_transfer+0x240>
+    1444:	0752      	lsls	r2, r2, #29
+    1446:	d46b      	bmi.n	1520 <_i2c_m_sync_transfer+0x240>
+			msg->len--;
+    1448:	3b01      	subs	r3, #1
+    144a:	606b      	str	r3, [r5, #4]
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+    144c:	2b00      	cmp	r3, #0
+    144e:	d101      	bne.n	1454 <_i2c_m_sync_transfer+0x174>
+    1450:	2900      	cmp	r1, #0
+    1452:	d04c      	beq.n	14ee <_i2c_m_sync_transfer+0x20e>
+    1454:	2b01      	cmp	r3, #1
+    1456:	d048      	beq.n	14ea <_i2c_m_sync_transfer+0x20a>
+			if (msg->len == 0) {
+    1458:	686b      	ldr	r3, [r5, #4]
+    145a:	2b00      	cmp	r3, #0
+    145c:	d107      	bne.n	146e <_i2c_m_sync_transfer+0x18e>
+				if (msg->flags & I2C_M_STOP) {
+    145e:	886b      	ldrh	r3, [r5, #2]
+    1460:	b21b      	sxth	r3, r3
+    1462:	2b00      	cmp	r3, #0
+    1464:	db4c      	blt.n	1500 <_i2c_m_sync_transfer+0x220>
+				msg->flags &= ~I2C_M_BUSY;
+    1466:	886b      	ldrh	r3, [r5, #2]
+    1468:	4a39      	ldr	r2, [pc, #228]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    146a:	4013      	ands	r3, r2
+    146c:	806b      	strh	r3, [r5, #2]
+			*msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+    146e:	68aa      	ldr	r2, [r5, #8]
+    1470:	1c53      	adds	r3, r2, #1
+    1472:	60ab      	str	r3, [r5, #8]
+    1474:	69e3      	ldr	r3, [r4, #28]
+    1476:	075b      	lsls	r3, r3, #29
+    1478:	d4fc      	bmi.n	1474 <_i2c_m_sync_transfer+0x194>
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+    147a:	2328      	movs	r3, #40	; 0x28
+    147c:	5ce3      	ldrb	r3, [r4, r3]
+    147e:	7013      	strb	r3, [r2, #0]
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+    1480:	2302      	movs	r3, #2
+    1482:	7623      	strb	r3, [r4, #24]
+	return I2C_OK;
+    1484:	2000      	movs	r0, #0
+	while (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+    1486:	886b      	ldrh	r3, [r5, #2]
+    1488:	05db      	lsls	r3, r3, #23
+    148a:	d400      	bmi.n	148e <_i2c_m_sync_transfer+0x1ae>
+    148c:	e761      	b.n	1352 <_i2c_m_sync_transfer+0x72>
+	void *   hw      = i2c_dev->hw;
+    148e:	6928      	ldr	r0, [r5, #16]
+	uint32_t timeout = 65535;
+    1490:	4a31      	ldr	r2, [pc, #196]	; (1558 <_i2c_m_sync_transfer+0x278>)
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+    1492:	7e03      	ldrb	r3, [r0, #24]
+    1494:	b2db      	uxtb	r3, r3
+		*flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+    1496:	001f      	movs	r7, r3
+		if (timeout-- == 0) {
+    1498:	1e51      	subs	r1, r2, #1
+    149a:	2a00      	cmp	r2, #0
+    149c:	d100      	bne.n	14a0 <_i2c_m_sync_transfer+0x1c0>
+    149e:	e759      	b.n	1354 <_i2c_m_sync_transfer+0x74>
+    14a0:	000a      	movs	r2, r1
+	} while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+    14a2:	079b      	lsls	r3, r3, #30
+    14a4:	d0f5      	beq.n	1492 <_i2c_m_sync_transfer+0x1b2>
+	return I2C_OK;
+    14a6:	2000      	movs	r0, #0
+		if (ret) {
+    14a8:	2800      	cmp	r0, #0
+    14aa:	d000      	beq.n	14ae <_i2c_m_sync_transfer+0x1ce>
+    14ac:	e755      	b.n	135a <_i2c_m_sync_transfer+0x7a>
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+    14ae:	6823      	ldr	r3, [r4, #0]
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+    14b0:	0edb      	lsrs	r3, r3, #27
+    14b2:	2101      	movs	r1, #1
+    14b4:	4019      	ands	r1, r3
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    14b6:	69e3      	ldr	r3, [r4, #28]
+    14b8:	075b      	lsls	r3, r3, #29
+    14ba:	d4fc      	bmi.n	14b6 <_i2c_m_sync_transfer+0x1d6>
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+    14bc:	8b62      	ldrh	r2, [r4, #26]
+    14be:	b292      	uxth	r2, r2
+	if (flags & MB_FLAG) {
+    14c0:	07fb      	lsls	r3, r7, #31
+    14c2:	d5ba      	bpl.n	143a <_i2c_m_sync_transfer+0x15a>
+		if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+    14c4:	0793      	lsls	r3, r2, #30
+    14c6:	d400      	bmi.n	14ca <_i2c_m_sync_transfer+0x1ea>
+    14c8:	e759      	b.n	137e <_i2c_m_sync_transfer+0x9e>
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+    14ca:	2301      	movs	r3, #1
+    14cc:	7623      	strb	r3, [r4, #24]
+			msg->flags |= I2C_M_FAIL;
+    14ce:	886b      	ldrh	r3, [r5, #2]
+    14d0:	2180      	movs	r1, #128	; 0x80
+    14d2:	0149      	lsls	r1, r1, #5
+    14d4:	430b      	orrs	r3, r1
+    14d6:	806b      	strh	r3, [r5, #2]
+			msg->flags &= ~I2C_M_BUSY;
+    14d8:	886b      	ldrh	r3, [r5, #2]
+    14da:	491d      	ldr	r1, [pc, #116]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    14dc:	400b      	ands	r3, r1
+    14de:	806b      	strh	r3, [r5, #2]
+			if (status & SERCOM_I2CM_STATUS_BUSERR) {
+    14e0:	07d3      	lsls	r3, r2, #31
+    14e2:	d522      	bpl.n	152a <_i2c_m_sync_transfer+0x24a>
+				return I2C_ERR_BUS;
+    14e4:	2005      	movs	r0, #5
+    14e6:	4240      	negs	r0, r0
+    14e8:	e7cd      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+    14ea:	2900      	cmp	r1, #0
+    14ec:	d0b4      	beq.n	1458 <_i2c_m_sync_transfer+0x178>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    14ee:	6862      	ldr	r2, [r4, #4]
+    14f0:	2380      	movs	r3, #128	; 0x80
+    14f2:	02db      	lsls	r3, r3, #11
+    14f4:	4313      	orrs	r3, r2
+    14f6:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    14f8:	69e3      	ldr	r3, [r4, #28]
+    14fa:	075b      	lsls	r3, r3, #29
+    14fc:	d4fc      	bmi.n	14f8 <_i2c_m_sync_transfer+0x218>
+    14fe:	e7ab      	b.n	1458 <_i2c_m_sync_transfer+0x178>
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+    1500:	6863      	ldr	r3, [r4, #4]
+    1502:	4a13      	ldr	r2, [pc, #76]	; (1550 <_i2c_m_sync_transfer+0x270>)
+    1504:	4013      	ands	r3, r2
+    1506:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1508:	69e3      	ldr	r3, [r4, #28]
+    150a:	075b      	lsls	r3, r3, #29
+    150c:	d4fc      	bmi.n	1508 <_i2c_m_sync_transfer+0x228>
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+    150e:	6862      	ldr	r2, [r4, #4]
+    1510:	23c0      	movs	r3, #192	; 0xc0
+    1512:	029b      	lsls	r3, r3, #10
+    1514:	4313      	orrs	r3, r2
+    1516:	6063      	str	r3, [r4, #4]
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+    1518:	69e3      	ldr	r3, [r4, #28]
+    151a:	075b      	lsls	r3, r3, #29
+    151c:	d4fc      	bmi.n	1518 <_i2c_m_sync_transfer+0x238>
+    151e:	e7a2      	b.n	1466 <_i2c_m_sync_transfer+0x186>
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+    1520:	2302      	movs	r3, #2
+    1522:	7623      	strb	r3, [r4, #24]
+			return I2C_NACK;
+    1524:	2002      	movs	r0, #2
+    1526:	4240      	negs	r0, r0
+    1528:	e7ad      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+			return I2C_ERR_BAD_ADDRESS;
+    152a:	2004      	movs	r0, #4
+    152c:	4240      	negs	r0, r0
+    152e:	e7aa      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+	return I2C_OK;
+    1530:	2000      	movs	r0, #0
+    1532:	e7a8      	b.n	1486 <_i2c_m_sync_transfer+0x1a6>
+		return I2C_ERR_BUSY;
+    1534:	2006      	movs	r0, #6
+    1536:	4240      	negs	r0, r0
+    1538:	e70b      	b.n	1352 <_i2c_m_sync_transfer+0x72>
+    153a:	46c0      	nop			; (mov r8, r8)
+    153c:	000005bf 	.word	0x000005bf
+    1540:	000020cc 	.word	0x000020cc
+    1544:	00000a69 	.word	0x00000a69
+    1548:	000005c1 	.word	0x000005c1
+    154c:	00000fc1 	.word	0x00000fc1
+    1550:	fffffeff 	.word	0xfffffeff
+    1554:	fffffbff 	.word	0xfffffbff
+    1558:	0000ffff 	.word	0x0000ffff
+
+0000155c <_system_time_init>:
+ * \brief Initialize system time module
+ */
+void _system_time_init(void *const hw)
+{
+	(void)hw;
+	SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos);
+    155c:	4b02      	ldr	r3, [pc, #8]	; (1568 <_system_time_init+0xc>)
+    155e:	4a03      	ldr	r2, [pc, #12]	; (156c <_system_time_init+0x10>)
+    1560:	605a      	str	r2, [r3, #4]
+	SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos)
+    1562:	2205      	movs	r2, #5
+    1564:	601a      	str	r2, [r3, #0]
+	                | (1 << SysTick_CTRL_CLKSOURCE_Pos);
+}
+    1566:	4770      	bx	lr
+    1568:	e000e010 	.word	0xe000e010
+    156c:	00ffffff 	.word	0x00ffffff
+
+00001570 <_delay_init>:
+/**
+ * \brief Initialize delay functionality
+ */
+void _delay_init(void *const hw)
+{
+    1570:	b510      	push	{r4, lr}
+	_system_time_init(hw);
+    1572:	4b01      	ldr	r3, [pc, #4]	; (1578 <_delay_init+0x8>)
+    1574:	4798      	blx	r3
+}
+    1576:	bd10      	pop	{r4, pc}
+    1578:	0000155d 	.word	0x0000155d
+
+0000157c <tcc_pwm_interrupt_handler>:
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+    157c:	b570      	push	{r4, r5, r6, lr}
+    157e:	0005      	movs	r5, r0
+	void *const hw = device->hw;
+    1580:	6904      	ldr	r4, [r0, #16]
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+    1582:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+
+	if (hri_tcc_get_interrupt_OVF_bit(hw)) {
+    1584:	07db      	lsls	r3, r3, #31
+    1586:	d505      	bpl.n	1594 <tcc_pwm_interrupt_handler+0x18>
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+    1588:	2301      	movs	r3, #1
+    158a:	62e3      	str	r3, [r4, #44]	; 0x2c
+		hri_tcc_clear_interrupt_OVF_bit(hw);
+		if (NULL != device->callback.pwm_period_cb) {
+    158c:	6803      	ldr	r3, [r0, #0]
+    158e:	2b00      	cmp	r3, #0
+    1590:	d000      	beq.n	1594 <tcc_pwm_interrupt_handler+0x18>
+			device->callback.pwm_period_cb(device);
+    1592:	4798      	blx	r3
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+    1594:	6aa3      	ldr	r3, [r4, #40]	; 0x28
+		}
+	}
+	if (hri_tcc_get_INTEN_ERR_bit(hw)) {
+    1596:	071b      	lsls	r3, r3, #28
+    1598:	d506      	bpl.n	15a8 <tcc_pwm_interrupt_handler+0x2c>
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+    159a:	2308      	movs	r3, #8
+    159c:	62e3      	str	r3, [r4, #44]	; 0x2c
+		hri_tcc_clear_interrupt_ERR_bit(hw);
+		if (NULL != device->callback.pwm_error_cb) {
+    159e:	686b      	ldr	r3, [r5, #4]
+    15a0:	2b00      	cmp	r3, #0
+    15a2:	d001      	beq.n	15a8 <tcc_pwm_interrupt_handler+0x2c>
+			device->callback.pwm_error_cb(device);
+    15a4:	0028      	movs	r0, r5
+    15a6:	4798      	blx	r3
+		}
+	}
+}
+    15a8:	bd70      	pop	{r4, r5, r6, pc}
+	...
+
+000015ac <TCC0_Handler>:
+
+/**
+ * \brief TCC interrupt handler
+ */
+void TCC0_Handler(void)
+{
+    15ac:	b510      	push	{r4, lr}
+	tcc_pwm_interrupt_handler(_tcc0_dev);
+    15ae:	4b02      	ldr	r3, [pc, #8]	; (15b8 <TCC0_Handler+0xc>)
+    15b0:	6818      	ldr	r0, [r3, #0]
+    15b2:	4b02      	ldr	r3, [pc, #8]	; (15bc <TCC0_Handler+0x10>)
+    15b4:	4798      	blx	r3
+}
+    15b6:	bd10      	pop	{r4, pc}
+    15b8:	20000068 	.word	0x20000068
+    15bc:	0000157d 	.word	0x0000157d
+
+000015c0 <_tc_start_pwm>:
+/**
+ * \brief Start PWM
+ */
+void _tc_start_pwm(struct _pwm_device *const device)
+{
+	hri_tc_set_CTRLA_ENABLE_bit(device->hw);
+    15c0:	6902      	ldr	r2, [r0, #16]
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+    15c2:	6813      	ldr	r3, [r2, #0]
+    15c4:	2102      	movs	r1, #2
+    15c6:	430b      	orrs	r3, r1
+    15c8:	6013      	str	r3, [r2, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    15ca:	6913      	ldr	r3, [r2, #16]
+    15cc:	079b      	lsls	r3, r3, #30
+    15ce:	d1fc      	bne.n	15ca <_tc_start_pwm+0xa>
+}
+    15d0:	4770      	bx	lr
+
+000015d2 <_tc_stop_pwm>:
+/**
+ * \brief Stop PWM
+ */
+void _tc_stop_pwm(struct _pwm_device *const device)
+{
+	hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
+    15d2:	6902      	ldr	r2, [r0, #16]
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+    15d4:	6813      	ldr	r3, [r2, #0]
+    15d6:	2102      	movs	r1, #2
+    15d8:	438b      	bics	r3, r1
+    15da:	6013      	str	r3, [r2, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    15dc:	6913      	ldr	r3, [r2, #16]
+    15de:	079b      	lsls	r3, r3, #30
+    15e0:	d1fc      	bne.n	15dc <_tc_stop_pwm+0xa>
+}
+    15e2:	4770      	bx	lr
+
+000015e4 <_tc_is_pwm_enabled>:
+/**
+ * \brief Check if PWM is running
+ */
+bool _tc_is_pwm_enabled(const struct _pwm_device *const device)
+{
+	return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
+    15e4:	6902      	ldr	r2, [r0, #16]
+    15e6:	6913      	ldr	r3, [r2, #16]
+    15e8:	079b      	lsls	r3, r3, #30
+    15ea:	d1fc      	bne.n	15e6 <_tc_is_pwm_enabled+0x2>
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+    15ec:	6813      	ldr	r3, [r2, #0]
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+    15ee:	085b      	lsrs	r3, r3, #1
+	return (bool)tmp;
+    15f0:	2001      	movs	r0, #1
+    15f2:	4018      	ands	r0, r3
+}
+    15f4:	4770      	bx	lr
+
+000015f6 <tc_pwm_interrupt_handler>:
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+    15f6:	b570      	push	{r4, r5, r6, lr}
+    15f8:	0005      	movs	r5, r0
+	void *const hw = device->hw;
+    15fa:	6904      	ldr	r4, [r0, #16]
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+    15fc:	7aa3      	ldrb	r3, [r4, #10]
+
+	if (hri_tc_get_interrupt_OVF_bit(hw)) {
+    15fe:	07db      	lsls	r3, r3, #31
+    1600:	d505      	bpl.n	160e <tc_pwm_interrupt_handler+0x18>
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+    1602:	2301      	movs	r3, #1
+    1604:	72a3      	strb	r3, [r4, #10]
+		hri_tc_clear_interrupt_OVF_bit(hw);
+		if (NULL != device->callback.pwm_period_cb) {
+    1606:	6803      	ldr	r3, [r0, #0]
+    1608:	2b00      	cmp	r3, #0
+    160a:	d000      	beq.n	160e <tc_pwm_interrupt_handler+0x18>
+			device->callback.pwm_period_cb(device);
+    160c:	4798      	blx	r3
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+    160e:	7a63      	ldrb	r3, [r4, #9]
+		}
+	}
+	if (hri_tc_get_INTEN_ERR_bit(hw)) {
+    1610:	079b      	lsls	r3, r3, #30
+    1612:	d506      	bpl.n	1622 <tc_pwm_interrupt_handler+0x2c>
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+    1614:	2302      	movs	r3, #2
+    1616:	72a3      	strb	r3, [r4, #10]
+		hri_tc_clear_interrupt_ERR_bit(hw);
+		if (NULL != device->callback.pwm_error_cb) {
+    1618:	686b      	ldr	r3, [r5, #4]
+    161a:	2b00      	cmp	r3, #0
+    161c:	d001      	beq.n	1622 <tc_pwm_interrupt_handler+0x2c>
+			device->callback.pwm_error_cb(device);
+    161e:	0028      	movs	r0, r5
+    1620:	4798      	blx	r3
+		}
+	}
+}
+    1622:	bd70      	pop	{r4, r5, r6, pc}
+
+00001624 <_tc_init_irq_param>:
+/**
+ * \brief Init irq param with the given tc hardware instance
+ */
+static void _tc_init_irq_param(const void *const hw, void *dev)
+{
+	if (hw == TC3) {
+    1624:	4b03      	ldr	r3, [pc, #12]	; (1634 <_tc_init_irq_param+0x10>)
+    1626:	4298      	cmp	r0, r3
+    1628:	d000      	beq.n	162c <_tc_init_irq_param+0x8>
+		_tc3_dev = (struct _pwm_device *)dev;
+	}
+}
+    162a:	4770      	bx	lr
+		_tc3_dev = (struct _pwm_device *)dev;
+    162c:	4b02      	ldr	r3, [pc, #8]	; (1638 <_tc_init_irq_param+0x14>)
+    162e:	6019      	str	r1, [r3, #0]
+}
+    1630:	e7fb      	b.n	162a <_tc_init_irq_param+0x6>
+    1632:	46c0      	nop			; (mov r8, r8)
+    1634:	42002c00 	.word	0x42002c00
+    1638:	2000006c 	.word	0x2000006c
+
+0000163c <get_tc_index>:
+{
+    163c:	b510      	push	{r4, lr}
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline uint8_t _get_hardware_offset(const void *const hw)
+{
+	return (((uint32_t)hw - (uint32_t)TC0) >> 10);
+    163e:	4b0e      	ldr	r3, [pc, #56]	; (1678 <get_tc_index+0x3c>)
+    1640:	469c      	mov	ip, r3
+    1642:	4460      	add	r0, ip
+    1644:	0a80      	lsrs	r0, r0, #10
+    1646:	b2c3      	uxtb	r3, r0
+	for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+    1648:	2000      	movs	r0, #0
+    164a:	2800      	cmp	r0, #0
+    164c:	d008      	beq.n	1660 <get_tc_index+0x24>
+	ASSERT(false);
+    164e:	22b0      	movs	r2, #176	; 0xb0
+    1650:	0052      	lsls	r2, r2, #1
+    1652:	490a      	ldr	r1, [pc, #40]	; (167c <get_tc_index+0x40>)
+    1654:	2000      	movs	r0, #0
+    1656:	4b0a      	ldr	r3, [pc, #40]	; (1680 <get_tc_index+0x44>)
+    1658:	4798      	blx	r3
+	return -1;
+    165a:	2001      	movs	r0, #1
+    165c:	4240      	negs	r0, r0
+}
+    165e:	bd10      	pop	{r4, pc}
+		if (_tcs[i].number == index) {
+    1660:	0082      	lsls	r2, r0, #2
+    1662:	1812      	adds	r2, r2, r0
+    1664:	0091      	lsls	r1, r2, #2
+    1666:	4a07      	ldr	r2, [pc, #28]	; (1684 <get_tc_index+0x48>)
+    1668:	5c8a      	ldrb	r2, [r1, r2]
+    166a:	429a      	cmp	r2, r3
+    166c:	d002      	beq.n	1674 <get_tc_index+0x38>
+	for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+    166e:	3001      	adds	r0, #1
+    1670:	b2c0      	uxtb	r0, r0
+    1672:	e7ea      	b.n	164a <get_tc_index+0xe>
+			return i;
+    1674:	b240      	sxtb	r0, r0
+    1676:	e7f2      	b.n	165e <get_tc_index+0x22>
+    1678:	bdffe000 	.word	0xbdffe000
+    167c:	000020e8 	.word	0x000020e8
+    1680:	00000a69 	.word	0x00000a69
+    1684:	20000000 	.word	0x20000000
+
+00001688 <_tc_pwm_init>:
+{
+    1688:	b570      	push	{r4, r5, r6, lr}
+    168a:	0006      	movs	r6, r0
+    168c:	000c      	movs	r4, r1
+	int8_t i   = get_tc_index(hw);
+    168e:	0008      	movs	r0, r1
+    1690:	4b53      	ldr	r3, [pc, #332]	; (17e0 <_tc_pwm_init+0x158>)
+    1692:	4798      	blx	r3
+    1694:	0005      	movs	r5, r0
+	device->hw = hw;
+    1696:	6134      	str	r4, [r6, #16]
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+    1698:	6923      	ldr	r3, [r4, #16]
+	if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
+    169a:	07db      	lsls	r3, r3, #31
+    169c:	d414      	bmi.n	16c8 <_tc_pwm_init+0x40>
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    169e:	6923      	ldr	r3, [r4, #16]
+    16a0:	079b      	lsls	r3, r3, #30
+    16a2:	d1fc      	bne.n	169e <_tc_pwm_init+0x16>
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+    16a4:	6823      	ldr	r3, [r4, #0]
+		if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
+    16a6:	079b      	lsls	r3, r3, #30
+    16a8:	d509      	bpl.n	16be <_tc_pwm_init+0x36>
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+    16aa:	6823      	ldr	r3, [r4, #0]
+    16ac:	2202      	movs	r2, #2
+    16ae:	4393      	bics	r3, r2
+    16b0:	6023      	str	r3, [r4, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    16b2:	6923      	ldr	r3, [r4, #16]
+    16b4:	079b      	lsls	r3, r3, #30
+    16b6:	d1fc      	bne.n	16b2 <_tc_pwm_init+0x2a>
+    16b8:	6923      	ldr	r3, [r4, #16]
+    16ba:	079b      	lsls	r3, r3, #30
+    16bc:	d4fc      	bmi.n	16b8 <_tc_pwm_init+0x30>
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+    16be:	2301      	movs	r3, #1
+    16c0:	6023      	str	r3, [r4, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    16c2:	6923      	ldr	r3, [r4, #16]
+    16c4:	079b      	lsls	r3, r3, #30
+    16c6:	d1fc      	bne.n	16c2 <_tc_pwm_init+0x3a>
+    16c8:	6923      	ldr	r3, [r4, #16]
+    16ca:	07db      	lsls	r3, r3, #31
+    16cc:	d4fc      	bmi.n	16c8 <_tc_pwm_init+0x40>
+	hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
+    16ce:	00ab      	lsls	r3, r5, #2
+    16d0:	195b      	adds	r3, r3, r5
+    16d2:	009a      	lsls	r2, r3, #2
+    16d4:	4b43      	ldr	r3, [pc, #268]	; (17e4 <_tc_pwm_init+0x15c>)
+    16d6:	189b      	adds	r3, r3, r2
+    16d8:	685b      	ldr	r3, [r3, #4]
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+    16da:	6023      	str	r3, [r4, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    16dc:	6923      	ldr	r3, [r4, #16]
+    16de:	079b      	lsls	r3, r3, #30
+    16e0:	d1fc      	bne.n	16dc <_tc_pwm_init+0x54>
+	hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
+    16e2:	00aa      	lsls	r2, r5, #2
+    16e4:	1952      	adds	r2, r2, r5
+    16e6:	0091      	lsls	r1, r2, #2
+    16e8:	4b3e      	ldr	r3, [pc, #248]	; (17e4 <_tc_pwm_init+0x15c>)
+    16ea:	185b      	adds	r3, r3, r1
+    16ec:	7a9a      	ldrb	r2, [r3, #10]
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+    16ee:	73e2      	strb	r2, [r4, #15]
+	hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
+    16f0:	891a      	ldrh	r2, [r3, #8]
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+    16f2:	80e2      	strh	r2, [r4, #6]
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+    16f4:	2203      	movs	r2, #3
+    16f6:	7322      	strb	r2, [r4, #12]
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+    16f8:	685a      	ldr	r2, [r3, #4]
+    16fa:	230c      	movs	r3, #12
+    16fc:	4013      	ands	r3, r2
+    16fe:	2b08      	cmp	r3, #8
+    1700:	d054      	beq.n	17ac <_tc_pwm_init+0x124>
+	} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
+    1702:	2b00      	cmp	r3, #0
+    1704:	d166      	bne.n	17d4 <_tc_pwm_init+0x14c>
+		hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
+    1706:	00ab      	lsls	r3, r5, #2
+    1708:	195b      	adds	r3, r3, r5
+    170a:	009a      	lsls	r2, r3, #2
+    170c:	4b35      	ldr	r3, [pc, #212]	; (17e4 <_tc_pwm_init+0x15c>)
+    170e:	189b      	adds	r3, r3, r2
+    1710:	899b      	ldrh	r3, [r3, #12]
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+    1712:	83a3      	strh	r3, [r4, #28]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    1714:	6923      	ldr	r3, [r4, #16]
+    1716:	22c0      	movs	r2, #192	; 0xc0
+    1718:	421a      	tst	r2, r3
+    171a:	d1fb      	bne.n	1714 <_tc_pwm_init+0x8c>
+		hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
+    171c:	00ab      	lsls	r3, r5, #2
+    171e:	195b      	adds	r3, r3, r5
+    1720:	009a      	lsls	r2, r3, #2
+    1722:	4b30      	ldr	r3, [pc, #192]	; (17e4 <_tc_pwm_init+0x15c>)
+    1724:	189b      	adds	r3, r3, r2
+    1726:	8a1b      	ldrh	r3, [r3, #16]
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+    1728:	83e3      	strh	r3, [r4, #30]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    172a:	6923      	ldr	r3, [r4, #16]
+    172c:	22c0      	movs	r2, #192	; 0xc0
+    172e:	421a      	tst	r2, r3
+    1730:	d1fb      	bne.n	172a <_tc_pwm_init+0xa2>
+	_tc_init_irq_param(hw, (void *)device);
+    1732:	0031      	movs	r1, r6
+    1734:	0020      	movs	r0, r4
+    1736:	4b2c      	ldr	r3, [pc, #176]	; (17e8 <_tc_pwm_init+0x160>)
+    1738:	4798      	blx	r3
+	NVIC_DisableIRQ(_tcs[i].irq);
+    173a:	00ab      	lsls	r3, r5, #2
+    173c:	195b      	adds	r3, r3, r5
+    173e:	009a      	lsls	r2, r3, #2
+    1740:	4b28      	ldr	r3, [pc, #160]	; (17e4 <_tc_pwm_init+0x15c>)
+    1742:	189b      	adds	r3, r3, r2
+    1744:	785b      	ldrb	r3, [r3, #1]
+    1746:	b25b      	sxtb	r3, r3
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+    1748:	2b00      	cmp	r3, #0
+    174a:	db0b      	blt.n	1764 <_tc_pwm_init+0xdc>
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    174c:	221f      	movs	r2, #31
+    174e:	4013      	ands	r3, r2
+    1750:	3a1e      	subs	r2, #30
+    1752:	409a      	lsls	r2, r3
+    1754:	0013      	movs	r3, r2
+    1756:	2280      	movs	r2, #128	; 0x80
+    1758:	4924      	ldr	r1, [pc, #144]	; (17ec <_tc_pwm_init+0x164>)
+    175a:	508b      	str	r3, [r1, r2]
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+    175c:	f3bf 8f4f 	dsb	sy
+  __ASM volatile ("isb 0xF":::"memory");
+    1760:	f3bf 8f6f 	isb	sy
+	NVIC_ClearPendingIRQ(_tcs[i].irq);
+    1764:	00ab      	lsls	r3, r5, #2
+    1766:	195b      	adds	r3, r3, r5
+    1768:	009a      	lsls	r2, r3, #2
+    176a:	4b1e      	ldr	r3, [pc, #120]	; (17e4 <_tc_pwm_init+0x15c>)
+    176c:	189b      	adds	r3, r3, r2
+    176e:	785b      	ldrb	r3, [r3, #1]
+    1770:	b25b      	sxtb	r3, r3
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+    1772:	2b00      	cmp	r3, #0
+    1774:	db08      	blt.n	1788 <_tc_pwm_init+0x100>
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    1776:	221f      	movs	r2, #31
+    1778:	4013      	ands	r3, r2
+    177a:	3a1e      	subs	r2, #30
+    177c:	409a      	lsls	r2, r3
+    177e:	0013      	movs	r3, r2
+    1780:	22c0      	movs	r2, #192	; 0xc0
+    1782:	0052      	lsls	r2, r2, #1
+    1784:	4919      	ldr	r1, [pc, #100]	; (17ec <_tc_pwm_init+0x164>)
+    1786:	508b      	str	r3, [r1, r2]
+	NVIC_EnableIRQ(_tcs[i].irq);
+    1788:	00ab      	lsls	r3, r5, #2
+    178a:	195d      	adds	r5, r3, r5
+    178c:	00aa      	lsls	r2, r5, #2
+    178e:	4b15      	ldr	r3, [pc, #84]	; (17e4 <_tc_pwm_init+0x15c>)
+    1790:	189b      	adds	r3, r3, r2
+    1792:	785b      	ldrb	r3, [r3, #1]
+    1794:	b25b      	sxtb	r3, r3
+  if ((int32_t)(IRQn) >= 0)
+    1796:	2b00      	cmp	r3, #0
+    1798:	db1f      	blt.n	17da <_tc_pwm_init+0x152>
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    179a:	221f      	movs	r2, #31
+    179c:	4013      	ands	r3, r2
+    179e:	3a1e      	subs	r2, #30
+    17a0:	409a      	lsls	r2, r3
+    17a2:	0013      	movs	r3, r2
+    17a4:	4a11      	ldr	r2, [pc, #68]	; (17ec <_tc_pwm_init+0x164>)
+    17a6:	6013      	str	r3, [r2, #0]
+	return 0;
+    17a8:	2000      	movs	r0, #0
+}
+    17aa:	bd70      	pop	{r4, r5, r6, pc}
+		hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
+    17ac:	4b0d      	ldr	r3, [pc, #52]	; (17e4 <_tc_pwm_init+0x15c>)
+    17ae:	185b      	adds	r3, r3, r1
+    17b0:	68db      	ldr	r3, [r3, #12]
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+    17b2:	61e3      	str	r3, [r4, #28]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    17b4:	6923      	ldr	r3, [r4, #16]
+    17b6:	22c0      	movs	r2, #192	; 0xc0
+    17b8:	421a      	tst	r2, r3
+    17ba:	d1fb      	bne.n	17b4 <_tc_pwm_init+0x12c>
+		hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+    17bc:	00ab      	lsls	r3, r5, #2
+    17be:	195b      	adds	r3, r3, r5
+    17c0:	009a      	lsls	r2, r3, #2
+    17c2:	4b08      	ldr	r3, [pc, #32]	; (17e4 <_tc_pwm_init+0x15c>)
+    17c4:	189b      	adds	r3, r3, r2
+    17c6:	691b      	ldr	r3, [r3, #16]
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+    17c8:	6223      	str	r3, [r4, #32]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    17ca:	6923      	ldr	r3, [r4, #16]
+    17cc:	22c0      	movs	r2, #192	; 0xc0
+    17ce:	421a      	tst	r2, r3
+    17d0:	d1fb      	bne.n	17ca <_tc_pwm_init+0x142>
+    17d2:	e7ae      	b.n	1732 <_tc_pwm_init+0xaa>
+		return -1;
+    17d4:	2001      	movs	r0, #1
+    17d6:	4240      	negs	r0, r0
+    17d8:	e7e7      	b.n	17aa <_tc_pwm_init+0x122>
+	return 0;
+    17da:	2000      	movs	r0, #0
+    17dc:	e7e5      	b.n	17aa <_tc_pwm_init+0x122>
+    17de:	46c0      	nop			; (mov r8, r8)
+    17e0:	0000163d 	.word	0x0000163d
+    17e4:	20000000 	.word	0x20000000
+    17e8:	00001625 	.word	0x00001625
+    17ec:	e000e100 	.word	0xe000e100
+
+000017f0 <_tc_set_pwm_param>:
+{
+    17f0:	b570      	push	{r4, r5, r6, lr}
+    17f2:	000e      	movs	r6, r1
+    17f4:	0015      	movs	r5, r2
+	void *const hw = device->hw;
+    17f6:	6904      	ldr	r4, [r0, #16]
+	int8_t      i  = get_tc_index(hw);
+    17f8:	0020      	movs	r0, r4
+    17fa:	4b1b      	ldr	r3, [pc, #108]	; (1868 <_tc_set_pwm_param+0x78>)
+    17fc:	4798      	blx	r3
+	_tcs[i].cc0 = period;
+    17fe:	0082      	lsls	r2, r0, #2
+    1800:	1812      	adds	r2, r2, r0
+    1802:	0091      	lsls	r1, r2, #2
+    1804:	4b19      	ldr	r3, [pc, #100]	; (186c <_tc_set_pwm_param+0x7c>)
+    1806:	185b      	adds	r3, r3, r1
+    1808:	60de      	str	r6, [r3, #12]
+	_tcs[i].cc1 = duty_cycle;
+    180a:	611d      	str	r5, [r3, #16]
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+    180c:	685a      	ldr	r2, [r3, #4]
+    180e:	230c      	movs	r3, #12
+    1810:	4013      	ands	r3, r2
+    1812:	2b08      	cmp	r3, #8
+    1814:	d016      	beq.n	1844 <_tc_set_pwm_param+0x54>
+		hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0);
+    1816:	0083      	lsls	r3, r0, #2
+    1818:	181b      	adds	r3, r3, r0
+    181a:	009a      	lsls	r2, r3, #2
+    181c:	4b13      	ldr	r3, [pc, #76]	; (186c <_tc_set_pwm_param+0x7c>)
+    181e:	189b      	adds	r3, r3, r2
+    1820:	899b      	ldrh	r3, [r3, #12]
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+    1822:	83a3      	strh	r3, [r4, #28]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    1824:	6923      	ldr	r3, [r4, #16]
+    1826:	22c0      	movs	r2, #192	; 0xc0
+    1828:	421a      	tst	r2, r3
+    182a:	d1fb      	bne.n	1824 <_tc_set_pwm_param+0x34>
+		hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1);
+    182c:	0083      	lsls	r3, r0, #2
+    182e:	1818      	adds	r0, r3, r0
+    1830:	0082      	lsls	r2, r0, #2
+    1832:	4b0e      	ldr	r3, [pc, #56]	; (186c <_tc_set_pwm_param+0x7c>)
+    1834:	189b      	adds	r3, r3, r2
+    1836:	8a1b      	ldrh	r3, [r3, #16]
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+    1838:	83e3      	strh	r3, [r4, #30]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    183a:	6923      	ldr	r3, [r4, #16]
+    183c:	22c0      	movs	r2, #192	; 0xc0
+    183e:	421a      	tst	r2, r3
+    1840:	d1fb      	bne.n	183a <_tc_set_pwm_param+0x4a>
+}
+    1842:	bd70      	pop	{r4, r5, r6, pc}
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+    1844:	61e6      	str	r6, [r4, #28]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    1846:	6923      	ldr	r3, [r4, #16]
+    1848:	22c0      	movs	r2, #192	; 0xc0
+    184a:	421a      	tst	r2, r3
+    184c:	d1fb      	bne.n	1846 <_tc_set_pwm_param+0x56>
+		hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+    184e:	0083      	lsls	r3, r0, #2
+    1850:	1818      	adds	r0, r3, r0
+    1852:	0082      	lsls	r2, r0, #2
+    1854:	4b05      	ldr	r3, [pc, #20]	; (186c <_tc_set_pwm_param+0x7c>)
+    1856:	189b      	adds	r3, r3, r2
+    1858:	691b      	ldr	r3, [r3, #16]
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+    185a:	6223      	str	r3, [r4, #32]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    185c:	6923      	ldr	r3, [r4, #16]
+    185e:	22c0      	movs	r2, #192	; 0xc0
+    1860:	421a      	tst	r2, r3
+    1862:	d1fb      	bne.n	185c <_tc_set_pwm_param+0x6c>
+    1864:	e7ed      	b.n	1842 <_tc_set_pwm_param+0x52>
+    1866:	46c0      	nop			; (mov r8, r8)
+    1868:	0000163d 	.word	0x0000163d
+    186c:	20000000 	.word	0x20000000
+
+00001870 <_tc_pwm_get_period>:
+{
+    1870:	b510      	push	{r4, lr}
+	void *const hw = device->hw;
+    1872:	6904      	ldr	r4, [r0, #16]
+	int8_t      i  = get_tc_index(hw);
+    1874:	0020      	movs	r0, r4
+    1876:	4b0c      	ldr	r3, [pc, #48]	; (18a8 <_tc_pwm_get_period+0x38>)
+    1878:	4798      	blx	r3
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+    187a:	0083      	lsls	r3, r0, #2
+    187c:	1818      	adds	r0, r3, r0
+    187e:	0082      	lsls	r2, r0, #2
+    1880:	4b0a      	ldr	r3, [pc, #40]	; (18ac <_tc_pwm_get_period+0x3c>)
+    1882:	189b      	adds	r3, r3, r2
+    1884:	685a      	ldr	r2, [r3, #4]
+    1886:	230c      	movs	r3, #12
+    1888:	4013      	ands	r3, r2
+    188a:	2b08      	cmp	r3, #8
+    188c:	d006      	beq.n	189c <_tc_pwm_get_period+0x2c>
+    188e:	6923      	ldr	r3, [r4, #16]
+    1890:	22c0      	movs	r2, #192	; 0xc0
+    1892:	421a      	tst	r2, r3
+    1894:	d1fb      	bne.n	188e <_tc_pwm_get_period+0x1e>
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+    1896:	8ba0      	ldrh	r0, [r4, #28]
+    1898:	b280      	uxth	r0, r0
+}
+    189a:	bd10      	pop	{r4, pc}
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    189c:	6923      	ldr	r3, [r4, #16]
+    189e:	22c0      	movs	r2, #192	; 0xc0
+    18a0:	421a      	tst	r2, r3
+    18a2:	d1fb      	bne.n	189c <_tc_pwm_get_period+0x2c>
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+    18a4:	69e0      	ldr	r0, [r4, #28]
+		return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0));
+    18a6:	e7f8      	b.n	189a <_tc_pwm_get_period+0x2a>
+    18a8:	0000163d 	.word	0x0000163d
+    18ac:	20000000 	.word	0x20000000
+
+000018b0 <_tc_pwm_get_duty>:
+{
+    18b0:	b510      	push	{r4, lr}
+	void *const hw = device->hw;
+    18b2:	6904      	ldr	r4, [r0, #16]
+	int8_t      i  = get_tc_index(hw);
+    18b4:	0020      	movs	r0, r4
+    18b6:	4b14      	ldr	r3, [pc, #80]	; (1908 <_tc_pwm_get_duty+0x58>)
+    18b8:	4798      	blx	r3
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+    18ba:	0083      	lsls	r3, r0, #2
+    18bc:	1818      	adds	r0, r3, r0
+    18be:	0082      	lsls	r2, r0, #2
+    18c0:	4b12      	ldr	r3, [pc, #72]	; (190c <_tc_pwm_get_duty+0x5c>)
+    18c2:	189b      	adds	r3, r3, r2
+    18c4:	685a      	ldr	r2, [r3, #4]
+    18c6:	230c      	movs	r3, #12
+    18c8:	4013      	ands	r3, r2
+    18ca:	2b08      	cmp	r3, #8
+    18cc:	d011      	beq.n	18f2 <_tc_pwm_get_duty+0x42>
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    18ce:	6923      	ldr	r3, [r4, #16]
+    18d0:	22c0      	movs	r2, #192	; 0xc0
+    18d2:	421a      	tst	r2, r3
+    18d4:	d1fb      	bne.n	18ce <_tc_pwm_get_duty+0x1e>
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+    18d6:	8ba1      	ldrh	r1, [r4, #28]
+    18d8:	b289      	uxth	r1, r1
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    18da:	6923      	ldr	r3, [r4, #16]
+    18dc:	22c0      	movs	r2, #192	; 0xc0
+    18de:	421a      	tst	r2, r3
+    18e0:	d1fb      	bne.n	18da <_tc_pwm_get_duty+0x2a>
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+    18e2:	8be3      	ldrh	r3, [r4, #30]
+    18e4:	b29b      	uxth	r3, r3
+	return ((duty_cycle * 1000) / per);
+    18e6:	20fa      	movs	r0, #250	; 0xfa
+    18e8:	0080      	lsls	r0, r0, #2
+    18ea:	4358      	muls	r0, r3
+    18ec:	4b08      	ldr	r3, [pc, #32]	; (1910 <_tc_pwm_get_duty+0x60>)
+    18ee:	4798      	blx	r3
+}
+    18f0:	bd10      	pop	{r4, pc}
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    18f2:	6923      	ldr	r3, [r4, #16]
+    18f4:	22c0      	movs	r2, #192	; 0xc0
+    18f6:	421a      	tst	r2, r3
+    18f8:	d1fb      	bne.n	18f2 <_tc_pwm_get_duty+0x42>
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+    18fa:	69e1      	ldr	r1, [r4, #28]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    18fc:	6923      	ldr	r3, [r4, #16]
+    18fe:	22c0      	movs	r2, #192	; 0xc0
+    1900:	421a      	tst	r2, r3
+    1902:	d1fb      	bne.n	18fc <_tc_pwm_get_duty+0x4c>
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+    1904:	6a23      	ldr	r3, [r4, #32]
+    1906:	e7ee      	b.n	18e6 <_tc_pwm_get_duty+0x36>
+    1908:	0000163d 	.word	0x0000163d
+    190c:	20000000 	.word	0x20000000
+    1910:	00001d45 	.word	0x00001d45
+
+00001914 <_tc_pwm_deinit>:
+{
+    1914:	b570      	push	{r4, r5, r6, lr}
+	void *const hw = device->hw;
+    1916:	6904      	ldr	r4, [r0, #16]
+	int8_t      i  = get_tc_index(hw);
+    1918:	0020      	movs	r0, r4
+    191a:	4b16      	ldr	r3, [pc, #88]	; (1974 <_tc_pwm_deinit+0x60>)
+    191c:	4798      	blx	r3
+    191e:	0005      	movs	r5, r0
+	ASSERT(ARRAY_SIZE(_tcs));
+    1920:	22c2      	movs	r2, #194	; 0xc2
+    1922:	4915      	ldr	r1, [pc, #84]	; (1978 <_tc_pwm_deinit+0x64>)
+    1924:	2001      	movs	r0, #1
+    1926:	4b15      	ldr	r3, [pc, #84]	; (197c <_tc_pwm_deinit+0x68>)
+    1928:	4798      	blx	r3
+	NVIC_DisableIRQ(_tcs[i].irq);
+    192a:	00a8      	lsls	r0, r5, #2
+    192c:	1940      	adds	r0, r0, r5
+    192e:	0082      	lsls	r2, r0, #2
+    1930:	4b13      	ldr	r3, [pc, #76]	; (1980 <_tc_pwm_deinit+0x6c>)
+    1932:	189b      	adds	r3, r3, r2
+    1934:	785b      	ldrb	r3, [r3, #1]
+    1936:	b25b      	sxtb	r3, r3
+  if ((int32_t)(IRQn) >= 0)
+    1938:	2b00      	cmp	r3, #0
+    193a:	db0b      	blt.n	1954 <_tc_pwm_deinit+0x40>
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    193c:	221f      	movs	r2, #31
+    193e:	4013      	ands	r3, r2
+    1940:	3a1e      	subs	r2, #30
+    1942:	409a      	lsls	r2, r3
+    1944:	0013      	movs	r3, r2
+    1946:	2280      	movs	r2, #128	; 0x80
+    1948:	490e      	ldr	r1, [pc, #56]	; (1984 <_tc_pwm_deinit+0x70>)
+    194a:	508b      	str	r3, [r1, r2]
+  __ASM volatile ("dsb 0xF":::"memory");
+    194c:	f3bf 8f4f 	dsb	sy
+  __ASM volatile ("isb 0xF":::"memory");
+    1950:	f3bf 8f6f 	isb	sy
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+    1954:	6823      	ldr	r3, [r4, #0]
+    1956:	2202      	movs	r2, #2
+    1958:	4393      	bics	r3, r2
+    195a:	6023      	str	r3, [r4, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    195c:	6923      	ldr	r3, [r4, #16]
+    195e:	079b      	lsls	r3, r3, #30
+    1960:	d1fc      	bne.n	195c <_tc_pwm_deinit+0x48>
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+    1962:	6823      	ldr	r3, [r4, #0]
+    1964:	2201      	movs	r2, #1
+    1966:	4313      	orrs	r3, r2
+    1968:	6023      	str	r3, [r4, #0]
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+    196a:	6923      	ldr	r3, [r4, #16]
+    196c:	07db      	lsls	r3, r3, #31
+    196e:	d4fc      	bmi.n	196a <_tc_pwm_deinit+0x56>
+}
+    1970:	bd70      	pop	{r4, r5, r6, pc}
+    1972:	46c0      	nop			; (mov r8, r8)
+    1974:	0000163d 	.word	0x0000163d
+    1978:	000020e8 	.word	0x000020e8
+    197c:	00000a69 	.word	0x00000a69
+    1980:	20000000 	.word	0x20000000
+    1984:	e000e100 	.word	0xe000e100
+
+00001988 <_tc_pwm_set_irq_state>:
+{
+    1988:	b570      	push	{r4, r5, r6, lr}
+    198a:	0004      	movs	r4, r0
+    198c:	000e      	movs	r6, r1
+    198e:	0015      	movs	r5, r2
+	ASSERT(device);
+    1990:	1e43      	subs	r3, r0, #1
+    1992:	4198      	sbcs	r0, r3
+    1994:	b2c0      	uxtb	r0, r0
+    1996:	2218      	movs	r2, #24
+    1998:	32ff      	adds	r2, #255	; 0xff
+    199a:	490d      	ldr	r1, [pc, #52]	; (19d0 <_tc_pwm_set_irq_state+0x48>)
+    199c:	4b0d      	ldr	r3, [pc, #52]	; (19d4 <_tc_pwm_set_irq_state+0x4c>)
+    199e:	4798      	blx	r3
+	if (PWM_DEVICE_PERIOD_CB == type) {
+    19a0:	2e00      	cmp	r6, #0
+    19a2:	d108      	bne.n	19b6 <_tc_pwm_set_irq_state+0x2e>
+		hri_tc_write_INTEN_OVF_bit(device->hw, disable);
+    19a4:	6923      	ldr	r3, [r4, #16]
+	if (value == 0x0) {
+    19a6:	2d00      	cmp	r5, #0
+    19a8:	d102      	bne.n	19b0 <_tc_pwm_set_irq_state+0x28>
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+    19aa:	2201      	movs	r2, #1
+    19ac:	721a      	strb	r2, [r3, #8]
+    19ae:	e004      	b.n	19ba <_tc_pwm_set_irq_state+0x32>
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+    19b0:	2201      	movs	r2, #1
+    19b2:	725a      	strb	r2, [r3, #9]
+    19b4:	e001      	b.n	19ba <_tc_pwm_set_irq_state+0x32>
+	} else if (PWM_DEVICE_ERROR_CB == type) {
+    19b6:	2e01      	cmp	r6, #1
+    19b8:	d000      	beq.n	19bc <_tc_pwm_set_irq_state+0x34>
+}
+    19ba:	bd70      	pop	{r4, r5, r6, pc}
+		hri_tc_write_INTEN_ERR_bit(device->hw, disable);
+    19bc:	6923      	ldr	r3, [r4, #16]
+	if (value == 0x0) {
+    19be:	2d00      	cmp	r5, #0
+    19c0:	d002      	beq.n	19c8 <_tc_pwm_set_irq_state+0x40>
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+    19c2:	2202      	movs	r2, #2
+    19c4:	725a      	strb	r2, [r3, #9]
+}
+    19c6:	e7f8      	b.n	19ba <_tc_pwm_set_irq_state+0x32>
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+    19c8:	2202      	movs	r2, #2
+    19ca:	721a      	strb	r2, [r3, #8]
+    19cc:	e7f5      	b.n	19ba <_tc_pwm_set_irq_state+0x32>
+    19ce:	46c0      	nop			; (mov r8, r8)
+    19d0:	000020e8 	.word	0x000020e8
+    19d4:	00000a69 	.word	0x00000a69
+
+000019d8 <_tc_get_pwm>:
+	return &_tc_pwm_functions;
+    19d8:	4801      	ldr	r0, [pc, #4]	; (19e0 <_tc_get_pwm+0x8>)
+}
+    19da:	3014      	adds	r0, #20
+    19dc:	4770      	bx	lr
+    19de:	46c0      	nop			; (mov r8, r8)
+    19e0:	20000000 	.word	0x20000000
+
+000019e4 <TC3_Handler>:
+{
+    19e4:	b510      	push	{r4, lr}
+	tc_pwm_interrupt_handler(_tc3_dev);
+    19e6:	4b02      	ldr	r3, [pc, #8]	; (19f0 <TC3_Handler+0xc>)
+    19e8:	6818      	ldr	r0, [r3, #0]
+    19ea:	4b02      	ldr	r3, [pc, #8]	; (19f4 <TC3_Handler+0x10>)
+    19ec:	4798      	blx	r3
+}
+    19ee:	bd10      	pop	{r4, pc}
+    19f0:	2000006c 	.word	0x2000006c
+    19f4:	000015f7 	.word	0x000015f7
+
+000019f8 <main>:
+#include <atmel_start.h>
+#include "watch-library/watch.h"
+
+int main(void)
+{
+    19f8:	b530      	push	{r4, r5, lr}
+    19fa:	b08b      	sub	sp, #44	; 0x2c
+	atmel_start_init();
+    19fc:	4b23      	ldr	r3, [pc, #140]	; (1a8c <main+0x94>)
+    19fe:	4798      	blx	r3
+	
+	Watch watch;
+	struct calendar_date_time date_time;
+	date_time.date.year = 2021;
+    1a00:	ac02      	add	r4, sp, #8
+    1a02:	4b23      	ldr	r3, [pc, #140]	; (1a90 <main+0x98>)
+    1a04:	80e3      	strh	r3, [r4, #6]
+	date_time.date.month = 4;
+    1a06:	2304      	movs	r3, #4
+    1a08:	7163      	strb	r3, [r4, #5]
+	date_time.date.day = 25;
+    1a0a:	2219      	movs	r2, #25
+    1a0c:	7122      	strb	r2, [r4, #4]
+	date_time.time.hour = 4;
+    1a0e:	70a3      	strb	r3, [r4, #2]
+	date_time.time.min = 0;
+    1a10:	2500      	movs	r5, #0
+    1a12:	7065      	strb	r5, [r4, #1]
+	date_time.time.sec = 0;
+    1a14:	7025      	strb	r5, [r4, #0]
+
+	watch_init(&watch);
+    1a16:	a804      	add	r0, sp, #16
+    1a18:	4b1e      	ldr	r3, [pc, #120]	; (1a94 <main+0x9c>)
+    1a1a:	4798      	blx	r3
+	watch_enable_led();
+    1a1c:	4b1e      	ldr	r3, [pc, #120]	; (1a98 <main+0xa0>)
+    1a1e:	4798      	blx	r3
+	watch_enable_date_time();
+    1a20:	4b1e      	ldr	r3, [pc, #120]	; (1a9c <main+0xa4>)
+    1a22:	4798      	blx	r3
+	watch_set_date_time(date_time);
+    1a24:	9802      	ldr	r0, [sp, #8]
+    1a26:	6861      	ldr	r1, [r4, #4]
+    1a28:	4b1d      	ldr	r3, [pc, #116]	; (1aa0 <main+0xa8>)
+    1a2a:	4798      	blx	r3
+	watch_enable_digital_output(A0);
+    1a2c:	2024      	movs	r0, #36	; 0x24
+    1a2e:	4b1d      	ldr	r3, [pc, #116]	; (1aa4 <main+0xac>)
+    1a30:	4798      	blx	r3
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+    1a32:	2110      	movs	r1, #16
+    1a34:	2398      	movs	r3, #152	; 0x98
+    1a36:	22c0      	movs	r2, #192	; 0xc0
+    1a38:	05d2      	lsls	r2, r2, #23
+    1a3a:	50d1      	str	r1, [r2, r3]
+	gpio_set_pin_level(A0, true);
+	watch_enable_i2c();
+    1a3c:	4b1a      	ldr	r3, [pc, #104]	; (1aa8 <main+0xb0>)
+    1a3e:	4798      	blx	r3
+	
+	uint8_t chipID = 0;
+    1a40:	466b      	mov	r3, sp
+    1a42:	1ddc      	adds	r4, r3, #7
+    1a44:	71dd      	strb	r5, [r3, #7]
+	uint8_t ChipIdRegister = 0xD0;
+    1a46:	1d99      	adds	r1, r3, #6
+    1a48:	23d0      	movs	r3, #208	; 0xd0
+    1a4a:	700b      	strb	r3, [r1, #0]
+	watch_i2c_send(0x77, &ChipIdRegister, 1);
+    1a4c:	2201      	movs	r2, #1
+    1a4e:	2077      	movs	r0, #119	; 0x77
+    1a50:	4b16      	ldr	r3, [pc, #88]	; (1aac <main+0xb4>)
+    1a52:	4798      	blx	r3
+	watch_i2c_receive(0x77, &chipID, 1);
+    1a54:	2201      	movs	r2, #1
+    1a56:	0021      	movs	r1, r4
+    1a58:	2077      	movs	r0, #119	; 0x77
+    1a5a:	4b15      	ldr	r3, [pc, #84]	; (1ab0 <main+0xb8>)
+    1a5c:	4798      	blx	r3
+	if (chipID == 0x60) {
+    1a5e:	7823      	ldrb	r3, [r4, #0]
+    1a60:	2b60      	cmp	r3, #96	; 0x60
+    1a62:	d101      	bne.n	1a68 <main+0x70>
+		watch_set_led_green();
+    1a64:	4b13      	ldr	r3, [pc, #76]	; (1ab4 <main+0xbc>)
+    1a66:	4798      	blx	r3
+	}
+
+	uint8_t last = date_time.time.sec;
+    1a68:	ab02      	add	r3, sp, #8
+    1a6a:	781c      	ldrb	r4, [r3, #0]
+    1a6c:	e001      	b.n	1a72 <main+0x7a>
+		if (date_time.time.sec != last) {
+			last = date_time.time.sec;
+			if (last % 2 == 0) {
+				watch_set_led_red();
+			} else {
+				watch_set_led_green();
+    1a6e:	4b11      	ldr	r3, [pc, #68]	; (1ab4 <main+0xbc>)
+    1a70:	4798      	blx	r3
+{
+    1a72:	0025      	movs	r5, r4
+		watch_get_date_time(&date_time);
+    1a74:	ac02      	add	r4, sp, #8
+    1a76:	0020      	movs	r0, r4
+    1a78:	4b0f      	ldr	r3, [pc, #60]	; (1ab8 <main+0xc0>)
+    1a7a:	4798      	blx	r3
+		if (date_time.time.sec != last) {
+    1a7c:	7824      	ldrb	r4, [r4, #0]
+    1a7e:	42a5      	cmp	r5, r4
+    1a80:	d0f8      	beq.n	1a74 <main+0x7c>
+			if (last % 2 == 0) {
+    1a82:	07e3      	lsls	r3, r4, #31
+    1a84:	d4f3      	bmi.n	1a6e <main+0x76>
+				watch_set_led_red();
+    1a86:	4b0d      	ldr	r3, [pc, #52]	; (1abc <main+0xc4>)
+    1a88:	4798      	blx	r3
+    1a8a:	e7f2      	b.n	1a72 <main+0x7a>
+    1a8c:	00000109 	.word	0x00000109
+    1a90:	000007e5 	.word	0x000007e5
+    1a94:	00001bb1 	.word	0x00001bb1
+    1a98:	00001bb5 	.word	0x00001bb5
+    1a9c:	00001c19 	.word	0x00001c19
+    1aa0:	00001c35 	.word	0x00001c35
+    1aa4:	00001c75 	.word	0x00001c75
+    1aa8:	00001cb9 	.word	0x00001cb9
+    1aac:	00001ce5 	.word	0x00001ce5
+    1ab0:	00001d15 	.word	0x00001d15
+    1ab4:	00001c05 	.word	0x00001c05
+    1ab8:	00001c61 	.word	0x00001c61
+    1abc:	00001bf1 	.word	0x00001bf1
+
+00001ac0 <sleepmgr_event_callback>:
+ *
+ * \param[in] id The event ID to process
+ * \param[in] data Not used
+ */
+static void sleepmgr_event_callback(event_id_t id, event_data_t data)
+{
+    1ac0:	b570      	push	{r4, r5, r6, lr}
+    1ac2:	b082      	sub	sp, #8
+    1ac4:	000e      	movs	r6, r1
+	if (EVENT_IS_READY_TO_SLEEP_ID == id) {
+    1ac6:	2800      	cmp	r0, #0
+    1ac8:	d113      	bne.n	1af2 <sleepmgr_event_callback+0x32>
+ * \return A pointer to the head of the given list or NULL if the list is
+ * empty
+ */
+static inline void *list_get_head(const struct list_descriptor *const list)
+{
+	return (void *)list->head;
+    1aca:	4b16      	ldr	r3, [pc, #88]	; (1b24 <sleepmgr_event_callback+0x64>)
+    1acc:	681d      	ldr	r5, [r3, #0]
+		struct sleepmgr_ready_to_sleep_cb *cur;
+		struct sleepmgr_ready_to_sleep *   ret_val = (struct sleepmgr_ready_to_sleep *)data;
+		struct sleepmgr_ready_to_sleep     ready;
+
+		for (cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_head(&ready_to_sleep_cbs); cur;
+    1ace:	e00c      	b.n	1aea <sleepmgr_event_callback+0x2a>
+		     cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_next_element(cur)) {
+			ready.mode  = ret_val->mode;
+    1ad0:	7873      	ldrb	r3, [r6, #1]
+    1ad2:	ac01      	add	r4, sp, #4
+    1ad4:	7063      	strb	r3, [r4, #1]
+			ready.ready = true;
+    1ad6:	2301      	movs	r3, #1
+    1ad8:	7023      	strb	r3, [r4, #0]
+			cur->cb(&ready);
+    1ada:	0020      	movs	r0, r4
+    1adc:	686b      	ldr	r3, [r5, #4]
+    1ade:	4798      	blx	r3
+			ret_val->ready &= ready.ready;
+    1ae0:	7832      	ldrb	r2, [r6, #0]
+    1ae2:	7823      	ldrb	r3, [r4, #0]
+    1ae4:	4013      	ands	r3, r2
+    1ae6:	7033      	strb	r3, [r6, #0]
+ * \return A pointer to the next list element or NULL if there is not next
+ * element
+ */
+static inline void *list_get_next_element(const void *const element)
+{
+	return element ? ((struct list_element *)element)->next : NULL;
+    1ae8:	682d      	ldr	r5, [r5, #0]
+		for (cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_head(&ready_to_sleep_cbs); cur;
+    1aea:	2d00      	cmp	r5, #0
+    1aec:	d1f0      	bne.n	1ad0 <sleepmgr_event_callback+0x10>
+		for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+		     cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_next_element(cur)) {
+			cur->cb(data);
+		}
+	}
+}
+    1aee:	b002      	add	sp, #8
+    1af0:	bd70      	pop	{r4, r5, r6, pc}
+	} else if (EVENT_WOKEN_UP_ID == id) {
+    1af2:	2802      	cmp	r0, #2
+    1af4:	d004      	beq.n	1b00 <sleepmgr_event_callback+0x40>
+	} else if (EVENT_PREPARE_TO_SLEEP_ID == id) {
+    1af6:	2801      	cmp	r0, #1
+    1af8:	d1f9      	bne.n	1aee <sleepmgr_event_callback+0x2e>
+	return (void *)list->head;
+    1afa:	4b0a      	ldr	r3, [pc, #40]	; (1b24 <sleepmgr_event_callback+0x64>)
+    1afc:	689c      	ldr	r4, [r3, #8]
+		for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+    1afe:	e00d      	b.n	1b1c <sleepmgr_event_callback+0x5c>
+    1b00:	4b08      	ldr	r3, [pc, #32]	; (1b24 <sleepmgr_event_callback+0x64>)
+    1b02:	685c      	ldr	r4, [r3, #4]
+		for (cur = (struct sleepmgr_wake_up_cb *)list_get_head(&wake_up_cbs); cur;
+    1b04:	e003      	b.n	1b0e <sleepmgr_event_callback+0x4e>
+			cur->cb((const enum sleepmgr_wakeup_source)data);
+    1b06:	b2f0      	uxtb	r0, r6
+    1b08:	6863      	ldr	r3, [r4, #4]
+    1b0a:	4798      	blx	r3
+	return element ? ((struct list_element *)element)->next : NULL;
+    1b0c:	6824      	ldr	r4, [r4, #0]
+		for (cur = (struct sleepmgr_wake_up_cb *)list_get_head(&wake_up_cbs); cur;
+    1b0e:	2c00      	cmp	r4, #0
+    1b10:	d1f9      	bne.n	1b06 <sleepmgr_event_callback+0x46>
+    1b12:	e7ec      	b.n	1aee <sleepmgr_event_callback+0x2e>
+			cur->cb(data);
+    1b14:	b2f0      	uxtb	r0, r6
+    1b16:	6863      	ldr	r3, [r4, #4]
+    1b18:	4798      	blx	r3
+    1b1a:	6824      	ldr	r4, [r4, #0]
+		for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+    1b1c:	2c00      	cmp	r4, #0
+    1b1e:	d1f9      	bne.n	1b14 <sleepmgr_event_callback+0x54>
+    1b20:	e7e5      	b.n	1aee <sleepmgr_event_callback+0x2e>
+    1b22:	46c0      	nop			; (mov r8, r8)
+    1b24:	20000070 	.word	0x20000070
+
+00001b28 <sleepmgr_init>:
+{
+    1b28:	b570      	push	{r4, r5, r6, lr}
+	event_subscribe(&sleepmgr_event, EVENT_PREPARE_TO_SLEEP_ID, sleepmgr_event_callback);
+    1b2a:	4e08      	ldr	r6, [pc, #32]	; (1b4c <sleepmgr_init+0x24>)
+    1b2c:	4c08      	ldr	r4, [pc, #32]	; (1b50 <sleepmgr_init+0x28>)
+    1b2e:	340c      	adds	r4, #12
+    1b30:	0032      	movs	r2, r6
+    1b32:	2101      	movs	r1, #1
+    1b34:	0020      	movs	r0, r4
+    1b36:	4d07      	ldr	r5, [pc, #28]	; (1b54 <sleepmgr_init+0x2c>)
+    1b38:	47a8      	blx	r5
+	event_subscribe(&sleepmgr_event, EVENT_IS_READY_TO_SLEEP_ID, sleepmgr_event_callback);
+    1b3a:	0032      	movs	r2, r6
+    1b3c:	2100      	movs	r1, #0
+    1b3e:	0020      	movs	r0, r4
+    1b40:	47a8      	blx	r5
+	event_subscribe(&sleepmgr_event, EVENT_WOKEN_UP_ID, sleepmgr_event_callback);
+    1b42:	0032      	movs	r2, r6
+    1b44:	2102      	movs	r1, #2
+    1b46:	0020      	movs	r0, r4
+    1b48:	47a8      	blx	r5
+}
+    1b4a:	bd70      	pop	{r4, r5, r6, pc}
+    1b4c:	00001ac1 	.word	0x00001ac1
+    1b50:	20000070 	.word	0x20000070
+    1b54:	00000a71 	.word	0x00000a71
+
+00001b58 <sleepmgr_register_ready_to_sleep_callback>:
+{
+    1b58:	b510      	push	{r4, lr}
+    1b5a:	0004      	movs	r4, r0
+	ASSERT(cb);
+    1b5c:	1e43      	subs	r3, r0, #1
+    1b5e:	4198      	sbcs	r0, r3
+    1b60:	b2c0      	uxtb	r0, r0
+    1b62:	2240      	movs	r2, #64	; 0x40
+    1b64:	4903      	ldr	r1, [pc, #12]	; (1b74 <sleepmgr_register_ready_to_sleep_callback+0x1c>)
+    1b66:	4b04      	ldr	r3, [pc, #16]	; (1b78 <sleepmgr_register_ready_to_sleep_callback+0x20>)
+    1b68:	4798      	blx	r3
+	list_insert_as_head(&ready_to_sleep_cbs, cb);
+    1b6a:	0021      	movs	r1, r4
+    1b6c:	4803      	ldr	r0, [pc, #12]	; (1b7c <sleepmgr_register_ready_to_sleep_callback+0x24>)
+    1b6e:	4b04      	ldr	r3, [pc, #16]	; (1b80 <sleepmgr_register_ready_to_sleep_callback+0x28>)
+    1b70:	4798      	blx	r3
+}
+    1b72:	bd10      	pop	{r4, pc}
+    1b74:	000020fc 	.word	0x000020fc
+    1b78:	00000a69 	.word	0x00000a69
+    1b7c:	20000070 	.word	0x20000070
+    1b80:	00000b11 	.word	0x00000b11
+
+00001b84 <sleep_cb>:
+
+static struct sleepmgr_ready_to_sleep_cb sleepmgr_cb;
+
+static void sleep_cb(struct sleepmgr_ready_to_sleep *const ready)
+{
+	ready->ready = false;
+    1b84:	2300      	movs	r3, #0
+    1b86:	7003      	strb	r3, [r0, #0]
+}
+    1b88:	4770      	bx	lr
+	...
+
+00001b8c <sleep_manager_init>:
+
+void sleep_manager_init(void)
+{
+    1b8c:	b510      	push	{r4, lr}
+	sleepmgr_init();
+    1b8e:	4b04      	ldr	r3, [pc, #16]	; (1ba0 <sleep_manager_init+0x14>)
+    1b90:	4798      	blx	r3
+
+	sleepmgr_cb.cb = sleep_cb;
+    1b92:	4804      	ldr	r0, [pc, #16]	; (1ba4 <sleep_manager_init+0x18>)
+    1b94:	4b04      	ldr	r3, [pc, #16]	; (1ba8 <sleep_manager_init+0x1c>)
+    1b96:	6043      	str	r3, [r0, #4]
+	sleepmgr_register_ready_to_sleep_callback(&sleepmgr_cb);
+    1b98:	4b04      	ldr	r3, [pc, #16]	; (1bac <sleep_manager_init+0x20>)
+    1b9a:	4798      	blx	r3
+}
+    1b9c:	bd10      	pop	{r4, pc}
+    1b9e:	46c0      	nop			; (mov r8, r8)
+    1ba0:	00001b29 	.word	0x00001b29
+    1ba4:	20000088 	.word	0x20000088
+    1ba8:	00001b85 	.word	0x00001b85
+    1bac:	00001b59 	.word	0x00001b59
+
+00001bb0 <watch_init>:
+
+#include "watch.h"
+#include "driver_init.h"
+
+void watch_init(Watch *watch) {
+}
+    1bb0:	4770      	bx	lr
+	...
+
+00001bb4 <watch_enable_led>:
+
+void watch_enable_led() {
+    1bb4:	b510      	push	{r4, lr}
+	PWM_0_init();
+    1bb6:	4b06      	ldr	r3, [pc, #24]	; (1bd0 <watch_enable_led+0x1c>)
+    1bb8:	4798      	blx	r3
+	pwm_set_parameters(&PWM_0, 10000, 0);
+    1bba:	4c06      	ldr	r4, [pc, #24]	; (1bd4 <watch_enable_led+0x20>)
+    1bbc:	2200      	movs	r2, #0
+    1bbe:	4906      	ldr	r1, [pc, #24]	; (1bd8 <watch_enable_led+0x24>)
+    1bc0:	0020      	movs	r0, r4
+    1bc2:	4b06      	ldr	r3, [pc, #24]	; (1bdc <watch_enable_led+0x28>)
+    1bc4:	4798      	blx	r3
+	pwm_enable(&PWM_0);
+    1bc6:	0020      	movs	r0, r4
+    1bc8:	4b05      	ldr	r3, [pc, #20]	; (1be0 <watch_enable_led+0x2c>)
+    1bca:	4798      	blx	r3
+}
+    1bcc:	bd10      	pop	{r4, pc}
+    1bce:	46c0      	nop			; (mov r8, r8)
+    1bd0:	000002d5 	.word	0x000002d5
+    1bd4:	20000090 	.word	0x20000090
+    1bd8:	00002710 	.word	0x00002710
+    1bdc:	00000a2d 	.word	0x00000a2d
+    1be0:	000009e9 	.word	0x000009e9
+
+00001be4 <watch_set_led_color>:
+
+	pwm_disable(&PWM_0);
+}
+
+void watch_set_led_color(uint16_t red, uint16_t green) {
+	TC3->COUNT16.CC[0].reg = red;
+    1be4:	4b01      	ldr	r3, [pc, #4]	; (1bec <watch_set_led_color+0x8>)
+    1be6:	8398      	strh	r0, [r3, #28]
+	TC3->COUNT16.CC[1].reg = green;
+    1be8:	83d9      	strh	r1, [r3, #30]
+}
+    1bea:	4770      	bx	lr
+    1bec:	42002c00 	.word	0x42002c00
+
+00001bf0 <watch_set_led_red>:
+
+void watch_set_led_red() {
+    1bf0:	b510      	push	{r4, lr}
+	watch_set_led_color(65535, 0);
+    1bf2:	2100      	movs	r1, #0
+    1bf4:	4801      	ldr	r0, [pc, #4]	; (1bfc <watch_set_led_red+0xc>)
+    1bf6:	4b02      	ldr	r3, [pc, #8]	; (1c00 <watch_set_led_red+0x10>)
+    1bf8:	4798      	blx	r3
+}
+    1bfa:	bd10      	pop	{r4, pc}
+    1bfc:	0000ffff 	.word	0x0000ffff
+    1c00:	00001be5 	.word	0x00001be5
+
+00001c04 <watch_set_led_green>:
+
+void watch_set_led_green() {
+    1c04:	b510      	push	{r4, lr}
+	watch_set_led_color(0, 65535);
+    1c06:	4902      	ldr	r1, [pc, #8]	; (1c10 <watch_set_led_green+0xc>)
+    1c08:	2000      	movs	r0, #0
+    1c0a:	4b02      	ldr	r3, [pc, #8]	; (1c14 <watch_set_led_green+0x10>)
+    1c0c:	4798      	blx	r3
+}
+    1c0e:	bd10      	pop	{r4, pc}
+    1c10:	0000ffff 	.word	0x0000ffff
+    1c14:	00001be5 	.word	0x00001be5
+
+00001c18 <watch_enable_date_time>:
+
+void watch_enable_date_time() {
+    1c18:	b510      	push	{r4, lr}
+	CALENDAR_0_init();
+    1c1a:	4b03      	ldr	r3, [pc, #12]	; (1c28 <watch_enable_date_time+0x10>)
+    1c1c:	4798      	blx	r3
+	calendar_enable(&CALENDAR_0);
+    1c1e:	4803      	ldr	r0, [pc, #12]	; (1c2c <watch_enable_date_time+0x14>)
+    1c20:	4b03      	ldr	r3, [pc, #12]	; (1c30 <watch_enable_date_time+0x18>)
+    1c22:	4798      	blx	r3
+}
+    1c24:	bd10      	pop	{r4, pc}
+    1c26:	46c0      	nop			; (mov r8, r8)
+    1c28:	0000019d 	.word	0x0000019d
+    1c2c:	200000b4 	.word	0x200000b4
+    1c30:	000006fd 	.word	0x000006fd
+
+00001c34 <watch_set_date_time>:
+
+void watch_set_date_time(struct calendar_date_time date_time) {
+    1c34:	b510      	push	{r4, lr}
+    1c36:	b082      	sub	sp, #8
+    1c38:	9000      	str	r0, [sp, #0]
+    1c3a:	9101      	str	r1, [sp, #4]
+	calendar_set_date(&CALENDAR_0, &date_time.date);
+    1c3c:	4c05      	ldr	r4, [pc, #20]	; (1c54 <watch_set_date_time+0x20>)
+    1c3e:	a901      	add	r1, sp, #4
+    1c40:	0020      	movs	r0, r4
+    1c42:	4b05      	ldr	r3, [pc, #20]	; (1c58 <watch_set_date_time+0x24>)
+    1c44:	4798      	blx	r3
+	calendar_set_time(&CALENDAR_0, &date_time.time);
+    1c46:	4669      	mov	r1, sp
+    1c48:	0020      	movs	r0, r4
+    1c4a:	4b04      	ldr	r3, [pc, #16]	; (1c5c <watch_set_date_time+0x28>)
+    1c4c:	4798      	blx	r3
+}
+    1c4e:	b002      	add	sp, #8
+    1c50:	bd10      	pop	{r4, pc}
+    1c52:	46c0      	nop			; (mov r8, r8)
+    1c54:	200000b4 	.word	0x200000b4
+    1c58:	0000078d 	.word	0x0000078d
+    1c5c:	00000729 	.word	0x00000729
+
+00001c60 <watch_get_date_time>:
+
+void watch_get_date_time(struct calendar_date_time *date_time) {
+    1c60:	b510      	push	{r4, lr}
+    1c62:	0001      	movs	r1, r0
+	calendar_get_date_time(&CALENDAR_0, date_time);
+    1c64:	4801      	ldr	r0, [pc, #4]	; (1c6c <watch_get_date_time+0xc>)
+    1c66:	4b02      	ldr	r3, [pc, #8]	; (1c70 <watch_get_date_time+0x10>)
+    1c68:	4798      	blx	r3
+}
+    1c6a:	bd10      	pop	{r4, pc}
+    1c6c:	200000b4 	.word	0x200000b4
+    1c70:	000007f1 	.word	0x000007f1
+
+00001c74 <watch_enable_digital_output>:
+void watch_enable_digital_input(const uint8_t pin) {
+	gpio_set_pin_direction(pin, GPIO_DIRECTION_IN);
+	gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+
+void watch_enable_digital_output(const uint8_t pin) {
+    1c74:	b570      	push	{r4, r5, r6, lr}
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
+{
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+    1c76:	0943      	lsrs	r3, r0, #5
+    1c78:	241f      	movs	r4, #31
+    1c7a:	4004      	ands	r4, r0
+    1c7c:	2501      	movs	r5, #1
+    1c7e:	0029      	movs	r1, r5
+    1c80:	40a1      	lsls	r1, r4
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+    1c82:	01da      	lsls	r2, r3, #7
+    1c84:	20c0      	movs	r0, #192	; 0xc0
+    1c86:	05c0      	lsls	r0, r0, #23
+    1c88:	1810      	adds	r0, r2, r0
+    1c8a:	6081      	str	r1, [r0, #8]
+		                                | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_OUT:
+		hri_port_set_DIR_reg(PORT_IOBUS, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+    1c8c:	040e      	lsls	r6, r1, #16
+    1c8e:	0c36      	lsrs	r6, r6, #16
+    1c90:	2080      	movs	r0, #128	; 0x80
+    1c92:	05c0      	lsls	r0, r0, #23
+    1c94:	4330      	orrs	r0, r6
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+    1c96:	4e07      	ldr	r6, [pc, #28]	; (1cb4 <watch_enable_digital_output+0x40>)
+    1c98:	46b4      	mov	ip, r6
+    1c9a:	4462      	add	r2, ip
+    1c9c:	6290      	str	r0, [r2, #40]	; 0x28
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+    1c9e:	0c09      	lsrs	r1, r1, #16
+		hri_port_write_WRCONFIG_reg(
+    1ca0:	20c0      	movs	r0, #192	; 0xc0
+    1ca2:	0600      	lsls	r0, r0, #24
+    1ca4:	4301      	orrs	r1, r0
+    1ca6:	6291      	str	r1, [r2, #40]	; 0x28
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+    1ca8:	1910      	adds	r0, r2, r4
+    1caa:	3040      	adds	r0, #64	; 0x40
+    1cac:	7803      	ldrb	r3, [r0, #0]
+	tmp &= ~PORT_PINCFG_PMUXEN;
+    1cae:	43ab      	bics	r3, r5
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+    1cb0:	7003      	strb	r3, [r0, #0]
+	gpio_set_pin_direction(pin, GPIO_DIRECTION_OUT);
+	gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+    1cb2:	bd70      	pop	{r4, r5, r6, pc}
+    1cb4:	41006000 	.word	0x41006000
+
+00001cb8 <watch_enable_i2c>:
+
+struct io_descriptor *I2C_0_io;
+
+void watch_enable_i2c() {
+    1cb8:	b510      	push	{r4, lr}
+	I2C_0_init();
+    1cba:	4b05      	ldr	r3, [pc, #20]	; (1cd0 <watch_enable_i2c+0x18>)
+    1cbc:	4798      	blx	r3
+	i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+    1cbe:	4c05      	ldr	r4, [pc, #20]	; (1cd4 <watch_enable_i2c+0x1c>)
+    1cc0:	4905      	ldr	r1, [pc, #20]	; (1cd8 <watch_enable_i2c+0x20>)
+    1cc2:	0020      	movs	r0, r4
+    1cc4:	4b05      	ldr	r3, [pc, #20]	; (1cdc <watch_enable_i2c+0x24>)
+    1cc6:	4798      	blx	r3
+	i2c_m_sync_enable(&I2C_0);
+    1cc8:	0020      	movs	r0, r4
+    1cca:	4b05      	ldr	r3, [pc, #20]	; (1ce0 <watch_enable_i2c+0x28>)
+    1ccc:	4798      	blx	r3
+}
+    1cce:	bd10      	pop	{r4, pc}
+    1cd0:	00000235 	.word	0x00000235
+    1cd4:	200000f8 	.word	0x200000f8
+    1cd8:	20000118 	.word	0x20000118
+    1cdc:	00000907 	.word	0x00000907
+    1ce0:	000008e9 	.word	0x000008e9
+
+00001ce4 <watch_i2c_send>:
+
+void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) {
+    1ce4:	b570      	push	{r4, r5, r6, lr}
+    1ce6:	000c      	movs	r4, r1
+    1ce8:	0015      	movs	r5, r2
+	i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+    1cea:	2280      	movs	r2, #128	; 0x80
+    1cec:	0112      	lsls	r2, r2, #4
+    1cee:	0001      	movs	r1, r0
+    1cf0:	4804      	ldr	r0, [pc, #16]	; (1d04 <watch_i2c_send+0x20>)
+    1cf2:	4b05      	ldr	r3, [pc, #20]	; (1d08 <watch_i2c_send+0x24>)
+    1cf4:	4798      	blx	r3
+	io_write(I2C_0_io, buf, length);
+    1cf6:	4b05      	ldr	r3, [pc, #20]	; (1d0c <watch_i2c_send+0x28>)
+    1cf8:	6818      	ldr	r0, [r3, #0]
+    1cfa:	002a      	movs	r2, r5
+    1cfc:	0021      	movs	r1, r4
+    1cfe:	4b04      	ldr	r3, [pc, #16]	; (1d10 <watch_i2c_send+0x2c>)
+    1d00:	4798      	blx	r3
+}
+    1d02:	bd70      	pop	{r4, r5, r6, pc}
+    1d04:	200000f8 	.word	0x200000f8
+    1d08:	000008f5 	.word	0x000008f5
+    1d0c:	20000118 	.word	0x20000118
+    1d10:	00000911 	.word	0x00000911
+
+00001d14 <watch_i2c_receive>:
+
+void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) {
+    1d14:	b570      	push	{r4, r5, r6, lr}
+    1d16:	000c      	movs	r4, r1
+    1d18:	0015      	movs	r5, r2
+	i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+    1d1a:	2280      	movs	r2, #128	; 0x80
+    1d1c:	0112      	lsls	r2, r2, #4
+    1d1e:	0001      	movs	r1, r0
+    1d20:	4804      	ldr	r0, [pc, #16]	; (1d34 <watch_i2c_receive+0x20>)
+    1d22:	4b05      	ldr	r3, [pc, #20]	; (1d38 <watch_i2c_receive+0x24>)
+    1d24:	4798      	blx	r3
+	io_read(I2C_0_io, buf, length);
+    1d26:	4b05      	ldr	r3, [pc, #20]	; (1d3c <watch_i2c_receive+0x28>)
+    1d28:	6818      	ldr	r0, [r3, #0]
+    1d2a:	002a      	movs	r2, r5
+    1d2c:	0021      	movs	r1, r4
+    1d2e:	4b04      	ldr	r3, [pc, #16]	; (1d40 <watch_i2c_receive+0x2c>)
+    1d30:	4798      	blx	r3
+}
+    1d32:	bd70      	pop	{r4, r5, r6, pc}
+    1d34:	200000f8 	.word	0x200000f8
+    1d38:	000008f5 	.word	0x000008f5
+    1d3c:	20000118 	.word	0x20000118
+    1d40:	00000949 	.word	0x00000949
+
+00001d44 <__udivsi3>:
+    1d44:	2200      	movs	r2, #0
+    1d46:	0843      	lsrs	r3, r0, #1
+    1d48:	428b      	cmp	r3, r1
+    1d4a:	d374      	bcc.n	1e36 <__udivsi3+0xf2>
+    1d4c:	0903      	lsrs	r3, r0, #4
+    1d4e:	428b      	cmp	r3, r1
+    1d50:	d35f      	bcc.n	1e12 <__udivsi3+0xce>
+    1d52:	0a03      	lsrs	r3, r0, #8
+    1d54:	428b      	cmp	r3, r1
+    1d56:	d344      	bcc.n	1de2 <__udivsi3+0x9e>
+    1d58:	0b03      	lsrs	r3, r0, #12
+    1d5a:	428b      	cmp	r3, r1
+    1d5c:	d328      	bcc.n	1db0 <__udivsi3+0x6c>
+    1d5e:	0c03      	lsrs	r3, r0, #16
+    1d60:	428b      	cmp	r3, r1
+    1d62:	d30d      	bcc.n	1d80 <__udivsi3+0x3c>
+    1d64:	22ff      	movs	r2, #255	; 0xff
+    1d66:	0209      	lsls	r1, r1, #8
+    1d68:	ba12      	rev	r2, r2
+    1d6a:	0c03      	lsrs	r3, r0, #16
+    1d6c:	428b      	cmp	r3, r1
+    1d6e:	d302      	bcc.n	1d76 <__udivsi3+0x32>
+    1d70:	1212      	asrs	r2, r2, #8
+    1d72:	0209      	lsls	r1, r1, #8
+    1d74:	d065      	beq.n	1e42 <__udivsi3+0xfe>
+    1d76:	0b03      	lsrs	r3, r0, #12
+    1d78:	428b      	cmp	r3, r1
+    1d7a:	d319      	bcc.n	1db0 <__udivsi3+0x6c>
+    1d7c:	e000      	b.n	1d80 <__udivsi3+0x3c>
+    1d7e:	0a09      	lsrs	r1, r1, #8
+    1d80:	0bc3      	lsrs	r3, r0, #15
+    1d82:	428b      	cmp	r3, r1
+    1d84:	d301      	bcc.n	1d8a <__udivsi3+0x46>
+    1d86:	03cb      	lsls	r3, r1, #15
+    1d88:	1ac0      	subs	r0, r0, r3
+    1d8a:	4152      	adcs	r2, r2
+    1d8c:	0b83      	lsrs	r3, r0, #14
+    1d8e:	428b      	cmp	r3, r1
+    1d90:	d301      	bcc.n	1d96 <__udivsi3+0x52>
+    1d92:	038b      	lsls	r3, r1, #14
+    1d94:	1ac0      	subs	r0, r0, r3
+    1d96:	4152      	adcs	r2, r2
+    1d98:	0b43      	lsrs	r3, r0, #13
+    1d9a:	428b      	cmp	r3, r1
+    1d9c:	d301      	bcc.n	1da2 <__udivsi3+0x5e>
+    1d9e:	034b      	lsls	r3, r1, #13
+    1da0:	1ac0      	subs	r0, r0, r3
+    1da2:	4152      	adcs	r2, r2
+    1da4:	0b03      	lsrs	r3, r0, #12
+    1da6:	428b      	cmp	r3, r1
+    1da8:	d301      	bcc.n	1dae <__udivsi3+0x6a>
+    1daa:	030b      	lsls	r3, r1, #12
+    1dac:	1ac0      	subs	r0, r0, r3
+    1dae:	4152      	adcs	r2, r2
+    1db0:	0ac3      	lsrs	r3, r0, #11
+    1db2:	428b      	cmp	r3, r1
+    1db4:	d301      	bcc.n	1dba <__udivsi3+0x76>
+    1db6:	02cb      	lsls	r3, r1, #11
+    1db8:	1ac0      	subs	r0, r0, r3
+    1dba:	4152      	adcs	r2, r2
+    1dbc:	0a83      	lsrs	r3, r0, #10
+    1dbe:	428b      	cmp	r3, r1
+    1dc0:	d301      	bcc.n	1dc6 <__udivsi3+0x82>
+    1dc2:	028b      	lsls	r3, r1, #10
+    1dc4:	1ac0      	subs	r0, r0, r3
+    1dc6:	4152      	adcs	r2, r2
+    1dc8:	0a43      	lsrs	r3, r0, #9
+    1dca:	428b      	cmp	r3, r1
+    1dcc:	d301      	bcc.n	1dd2 <__udivsi3+0x8e>
+    1dce:	024b      	lsls	r3, r1, #9
+    1dd0:	1ac0      	subs	r0, r0, r3
+    1dd2:	4152      	adcs	r2, r2
+    1dd4:	0a03      	lsrs	r3, r0, #8
+    1dd6:	428b      	cmp	r3, r1
+    1dd8:	d301      	bcc.n	1dde <__udivsi3+0x9a>
+    1dda:	020b      	lsls	r3, r1, #8
+    1ddc:	1ac0      	subs	r0, r0, r3
+    1dde:	4152      	adcs	r2, r2
+    1de0:	d2cd      	bcs.n	1d7e <__udivsi3+0x3a>
+    1de2:	09c3      	lsrs	r3, r0, #7
+    1de4:	428b      	cmp	r3, r1
+    1de6:	d301      	bcc.n	1dec <__udivsi3+0xa8>
+    1de8:	01cb      	lsls	r3, r1, #7
+    1dea:	1ac0      	subs	r0, r0, r3
+    1dec:	4152      	adcs	r2, r2
+    1dee:	0983      	lsrs	r3, r0, #6
+    1df0:	428b      	cmp	r3, r1
+    1df2:	d301      	bcc.n	1df8 <__udivsi3+0xb4>
+    1df4:	018b      	lsls	r3, r1, #6
+    1df6:	1ac0      	subs	r0, r0, r3
+    1df8:	4152      	adcs	r2, r2
+    1dfa:	0943      	lsrs	r3, r0, #5
+    1dfc:	428b      	cmp	r3, r1
+    1dfe:	d301      	bcc.n	1e04 <__udivsi3+0xc0>
+    1e00:	014b      	lsls	r3, r1, #5
+    1e02:	1ac0      	subs	r0, r0, r3
+    1e04:	4152      	adcs	r2, r2
+    1e06:	0903      	lsrs	r3, r0, #4
+    1e08:	428b      	cmp	r3, r1
+    1e0a:	d301      	bcc.n	1e10 <__udivsi3+0xcc>
+    1e0c:	010b      	lsls	r3, r1, #4
+    1e0e:	1ac0      	subs	r0, r0, r3
+    1e10:	4152      	adcs	r2, r2
+    1e12:	08c3      	lsrs	r3, r0, #3
+    1e14:	428b      	cmp	r3, r1
+    1e16:	d301      	bcc.n	1e1c <__udivsi3+0xd8>
+    1e18:	00cb      	lsls	r3, r1, #3
+    1e1a:	1ac0      	subs	r0, r0, r3
+    1e1c:	4152      	adcs	r2, r2
+    1e1e:	0883      	lsrs	r3, r0, #2
+    1e20:	428b      	cmp	r3, r1
+    1e22:	d301      	bcc.n	1e28 <__udivsi3+0xe4>
+    1e24:	008b      	lsls	r3, r1, #2
+    1e26:	1ac0      	subs	r0, r0, r3
+    1e28:	4152      	adcs	r2, r2
+    1e2a:	0843      	lsrs	r3, r0, #1
+    1e2c:	428b      	cmp	r3, r1
+    1e2e:	d301      	bcc.n	1e34 <__udivsi3+0xf0>
+    1e30:	004b      	lsls	r3, r1, #1
+    1e32:	1ac0      	subs	r0, r0, r3
+    1e34:	4152      	adcs	r2, r2
+    1e36:	1a41      	subs	r1, r0, r1
+    1e38:	d200      	bcs.n	1e3c <__udivsi3+0xf8>
+    1e3a:	4601      	mov	r1, r0
+    1e3c:	4152      	adcs	r2, r2
+    1e3e:	4610      	mov	r0, r2
+    1e40:	4770      	bx	lr
+    1e42:	e7ff      	b.n	1e44 <__udivsi3+0x100>
+    1e44:	b501      	push	{r0, lr}
+    1e46:	2000      	movs	r0, #0
+    1e48:	f000 f806 	bl	1e58 <__aeabi_idiv0>
+    1e4c:	bd02      	pop	{r1, pc}
+    1e4e:	46c0      	nop			; (mov r8, r8)
+
+00001e50 <__aeabi_uidivmod>:
+    1e50:	2900      	cmp	r1, #0
+    1e52:	d0f7      	beq.n	1e44 <__udivsi3+0x100>
+    1e54:	e776      	b.n	1d44 <__udivsi3>
+    1e56:	4770      	bx	lr
+
+00001e58 <__aeabi_idiv0>:
+    1e58:	4770      	bx	lr
+    1e5a:	46c0      	nop			; (mov r8, r8)
+
+00001e5c <__ffssi2>:
+    1e5c:	b510      	push	{r4, lr}
+    1e5e:	2300      	movs	r3, #0
+    1e60:	2800      	cmp	r0, #0
+    1e62:	d002      	beq.n	1e6a <__ffssi2+0xe>
+    1e64:	f000 f804 	bl	1e70 <__ctzsi2>
+    1e68:	1c43      	adds	r3, r0, #1
+    1e6a:	0018      	movs	r0, r3
+    1e6c:	bd10      	pop	{r4, pc}
+    1e6e:	46c0      	nop			; (mov r8, r8)
+
+00001e70 <__ctzsi2>:
+    1e70:	4241      	negs	r1, r0
+    1e72:	4008      	ands	r0, r1
+    1e74:	211c      	movs	r1, #28
+    1e76:	2301      	movs	r3, #1
+    1e78:	041b      	lsls	r3, r3, #16
+    1e7a:	4298      	cmp	r0, r3
+    1e7c:	d301      	bcc.n	1e82 <__ctzsi2+0x12>
+    1e7e:	0c00      	lsrs	r0, r0, #16
+    1e80:	3910      	subs	r1, #16
+    1e82:	0a1b      	lsrs	r3, r3, #8
+    1e84:	4298      	cmp	r0, r3
+    1e86:	d301      	bcc.n	1e8c <__ctzsi2+0x1c>
+    1e88:	0a00      	lsrs	r0, r0, #8
+    1e8a:	3908      	subs	r1, #8
+    1e8c:	091b      	lsrs	r3, r3, #4
+    1e8e:	4298      	cmp	r0, r3
+    1e90:	d301      	bcc.n	1e96 <__ctzsi2+0x26>
+    1e92:	0900      	lsrs	r0, r0, #4
+    1e94:	3904      	subs	r1, #4
+    1e96:	a202      	add	r2, pc, #8	; (adr r2, 1ea0 <__ctzsi2+0x30>)
+    1e98:	5c10      	ldrb	r0, [r2, r0]
+    1e9a:	1a40      	subs	r0, r0, r1
+    1e9c:	4770      	bx	lr
+    1e9e:	46c0      	nop			; (mov r8, r8)
+    1ea0:	1d1d1c1b 	.word	0x1d1d1c1b
+    1ea4:	1e1e1e1e 	.word	0x1e1e1e1e
+    1ea8:	1f1f1f1f 	.word	0x1f1f1f1f
+    1eac:	1f1f1f1f 	.word	0x1f1f1f1f
+
+00001eb0 <__libc_init_array>:
+    1eb0:	b570      	push	{r4, r5, r6, lr}
+    1eb2:	2600      	movs	r6, #0
+    1eb4:	4d0c      	ldr	r5, [pc, #48]	; (1ee8 <__libc_init_array+0x38>)
+    1eb6:	4c0d      	ldr	r4, [pc, #52]	; (1eec <__libc_init_array+0x3c>)
+    1eb8:	1b64      	subs	r4, r4, r5
+    1eba:	10a4      	asrs	r4, r4, #2
+    1ebc:	42a6      	cmp	r6, r4
+    1ebe:	d109      	bne.n	1ed4 <__libc_init_array+0x24>
+    1ec0:	2600      	movs	r6, #0
+    1ec2:	f000 f92d 	bl	2120 <_init>
+    1ec6:	4d0a      	ldr	r5, [pc, #40]	; (1ef0 <__libc_init_array+0x40>)
+    1ec8:	4c0a      	ldr	r4, [pc, #40]	; (1ef4 <__libc_init_array+0x44>)
+    1eca:	1b64      	subs	r4, r4, r5
+    1ecc:	10a4      	asrs	r4, r4, #2
+    1ece:	42a6      	cmp	r6, r4
+    1ed0:	d105      	bne.n	1ede <__libc_init_array+0x2e>
+    1ed2:	bd70      	pop	{r4, r5, r6, pc}
+    1ed4:	00b3      	lsls	r3, r6, #2
+    1ed6:	58eb      	ldr	r3, [r5, r3]
+    1ed8:	4798      	blx	r3
+    1eda:	3601      	adds	r6, #1
+    1edc:	e7ee      	b.n	1ebc <__libc_init_array+0xc>
+    1ede:	00b3      	lsls	r3, r6, #2
+    1ee0:	58eb      	ldr	r3, [r5, r3]
+    1ee2:	4798      	blx	r3
+    1ee4:	3601      	adds	r6, #1
+    1ee6:	e7f2      	b.n	1ece <__libc_init_array+0x1e>
+    1ee8:	0000212c 	.word	0x0000212c
+    1eec:	0000212c 	.word	0x0000212c
+    1ef0:	0000212c 	.word	0x0000212c
+    1ef4:	00002130 	.word	0x00002130
+    1ef8:	000003c2 	.word	0x000003c2
+    1efc:	000003e6 	.word	0x000003e6
+    1f00:	000003c6 	.word	0x000003c6
+    1f04:	000003e6 	.word	0x000003e6
+    1f08:	000003ca 	.word	0x000003ca
+    1f0c:	000003e6 	.word	0x000003e6
+    1f10:	000003ca 	.word	0x000003ca
+    1f14:	000003e6 	.word	0x000003e6
+    1f18:	000003e6 	.word	0x000003e6
+    1f1c:	000003ca 	.word	0x000003ca
+    1f20:	000003e6 	.word	0x000003e6
+    1f24:	000003ca 	.word	0x000003ca
+    1f28:	000003e6 	.word	0x000003e6
+    1f2c:	000003da 	.word	0x000003da
+    1f30:	000003ea 	.word	0x000003ea
+    1f34:	000003de 	.word	0x000003de
+    1f38:	000003ea 	.word	0x000003ea
+    1f3c:	000003e2 	.word	0x000003e2
+    1f40:	000003ea 	.word	0x000003ea
+    1f44:	000003e2 	.word	0x000003e2
+    1f48:	000003ea 	.word	0x000003ea
+    1f4c:	000003ea 	.word	0x000003ea
+    1f50:	000003e2 	.word	0x000003e2
+    1f54:	000003ea 	.word	0x000003ea
+    1f58:	000003e2 	.word	0x000003e2
+    1f5c:	000003ea 	.word	0x000003ea
+    1f60:	0000058c 	.word	0x0000058c
+    1f64:	00000586 	.word	0x00000586
+    1f68:	00000590 	.word	0x00000590
+    1f6c:	0000059e 	.word	0x0000059e
+    1f70:	000005aa 	.word	0x000005aa
+    1f74:	000005ba 	.word	0x000005ba
+    1f78:	00000636 	.word	0x00000636
+    1f7c:	00000618 	.word	0x00000618
+    1f80:	0000065a 	.word	0x0000065a
+    1f84:	00000674 	.word	0x00000674
+    1f88:	00000688 	.word	0x00000688
+    1f8c:	00000696 	.word	0x00000696
+    1f90:	682f2e2e 	.word	0x682f2e2e
+    1f94:	732f6c61 	.word	0x732f6c61
+    1f98:	682f6372 	.word	0x682f6372
+    1f9c:	635f6c61 	.word	0x635f6c61
+    1fa0:	6e656c61 	.word	0x6e656c61
+    1fa4:	2e726164 	.word	0x2e726164
+    1fa8:	00000063 	.word	0x00000063
+    1fac:	682f2e2e 	.word	0x682f2e2e
+    1fb0:	732f6c61 	.word	0x732f6c61
+    1fb4:	682f6372 	.word	0x682f6372
+    1fb8:	695f6c61 	.word	0x695f6c61
+    1fbc:	6d5f6332 	.word	0x6d5f6332
+    1fc0:	6e79735f 	.word	0x6e79735f
+    1fc4:	00632e63 	.word	0x00632e63
+    1fc8:	682f2e2e 	.word	0x682f2e2e
+    1fcc:	732f6c61 	.word	0x732f6c61
+    1fd0:	682f6372 	.word	0x682f6372
+    1fd4:	695f6c61 	.word	0x695f6c61
+    1fd8:	00632e6f 	.word	0x00632e6f
+    1fdc:	682f2e2e 	.word	0x682f2e2e
+    1fe0:	732f6c61 	.word	0x732f6c61
+    1fe4:	682f6372 	.word	0x682f6372
+    1fe8:	705f6c61 	.word	0x705f6c61
+    1fec:	632e6d77 	.word	0x632e6d77
+    1ff0:	00000000 	.word	0x00000000
+    1ff4:	682f2e2e 	.word	0x682f2e2e
+    1ff8:	752f6c61 	.word	0x752f6c61
+    1ffc:	736c6974 	.word	0x736c6974
+    2000:	6372732f 	.word	0x6372732f
+    2004:	6974752f 	.word	0x6974752f
+    2008:	655f736c 	.word	0x655f736c
+    200c:	746e6576 	.word	0x746e6576
+    2010:	0000632e 	.word	0x0000632e
+    2014:	682f2e2e 	.word	0x682f2e2e
+    2018:	752f6c61 	.word	0x752f6c61
+    201c:	736c6974 	.word	0x736c6974
+    2020:	6372732f 	.word	0x6372732f
+    2024:	6974752f 	.word	0x6974752f
+    2028:	6c5f736c 	.word	0x6c5f736c
+    202c:	2e747369 	.word	0x2e747369
+    2030:	00000063 	.word	0x00000063
+
+00002034 <_map>:
+    2034:	00000005 00000025 00000006 00000016     ....%...........
+    2044:	00000007 00000017 682f2e2e 652f6c70     ........../hpl/e
+    2054:	682f6369 655f6c70 632e6369 00000000     ic/hpl_eic.c....
+    2064:	682f2e2e 722f6c70 682f6374 725f6c70     ../hpl/rtc/hpl_r
+    2074:	632e6374 00000000                       tc.c....
+
+0000207c <_usarts>:
+	...
+
+00002090 <_i2cms>:
+    2090:	00000001 00200014 00000100 00000f0e     ...... .........
+    20a0:	00d70000 003d0900                       ......=.
+
+000020a8 <_i2css>:
+	...
+
+000020b8 <sercomspi_regs>:
+	...
+    20cc:	682f2e2e 732f6c70 6f637265 70682f6d     ../hpl/sercom/hp
+    20dc:	65735f6c 6d6f6372 0000632e 682f2e2e     l_sercom.c..../h
+    20ec:	742f6c70 70682f63 63745f6c 0000632e     pl/tc/hpl_tc.c..
+    20fc:	732f2e2e 7065656c 6e616d5f 72656761     ../sleep_manager
+    210c:	656c732f 6d5f7065 67616e61 632e7265     /sleep_manager.c
+    211c:	00000000                                ....
+
+00002120 <_init>:
+    2120:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2122:	46c0      	nop			; (mov r8, r8)
+    2124:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    2126:	bc08      	pop	{r3}
+    2128:	469e      	mov	lr, r3
+    212a:	4770      	bx	lr
+
+0000212c <__init_array_start>:
+    212c:	000000d1 	.word	0x000000d1
+
+00002130 <_fini>:
+    2130:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+    2132:	46c0      	nop			; (mov r8, r8)
+    2134:	bcf8      	pop	{r3, r4, r5, r6, r7}
+    2136:	bc08      	pop	{r3}
+    2138:	469e      	mov	lr, r3
+    213a:	4770      	bx	lr
+
+0000213c <__fini_array_start>:
+    213c:	000000a9 	.word	0x000000a9
diff --git a/Smol Watch Project/My Project/Debug/My Project.map b/Smol Watch Project/My Project/Debug/My Project.map
new file mode 100644
index 0000000..7559d52
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/My Project.map	
@@ -0,0 +1,11740 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+                              hpl/core/hpl_core_m0plus_base.o (__aeabi_uidiv)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+                              hal/src/hal_adc_sync.o (__aeabi_idivmod)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_aeabi_uldivmod.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_uldivmod)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_muldi3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_lmul)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_ffssi2.o)
+                              hpl/eic/hpl_eic.o (__ffssi2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_d2uiz)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivmoddi4.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_ddiv)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_dmul)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_dsub)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o) (__aeabi_d2iz)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_i2d)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+                              hpl/sercom/hpl_sercom.o (__aeabi_ui2d)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o) (__aeabi_dcmpge)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o) (__clzsi2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzdi2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivmoddi4.o) (__clzdi2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_ctzsi2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_ffssi2.o) (__ctzsi2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__eqdf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__gedf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__ledf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (exit)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (__libc_init_array)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (memset)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o)
+                              hal/utils/src/utils_syscalls.o (printf)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (__sinit)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fwalk.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_fwalk)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_malloc_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-printf.o) (_vfprintf_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (_printf_i)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (__sread)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wbuf.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (__swbuf_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-writer.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o) (_write_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wsetup.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (__swsetup_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-closer.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o) (_close_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fflush.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-findfp.o) (_fflush_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (__sfvwrite_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-lseekr.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-stdio.o) (_lseek_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-makebuf.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wsetup.o) (__smakebuf_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf.o) (memchr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+                              c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-fvwrite.o) (memcpy)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
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+ .text._calendar_disable
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+ .text._calendar_get_comp
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+ .text._tamper_clear_tampid_flag
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+ .text._tamper_enable_debounce_asynchronous
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+ .text._tamper_enable_debounce_majority
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+ .text._tamper_disable_debounce_majority
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+ .text._tamper_register_callback
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+ .text._calendar_register_callback
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+ .text._calendar_set_irq
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+ .text._usart_calculate_baud_rate
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+ .text._sercom_get_irq_num
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._spi_deinit
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+ .text._spi_sync_enable
+                0x00000000       0x1e hpl/sercom/hpl_sercom.o
+ .text._spi_async_enable
+                0x00000000       0x30 hpl/sercom/hpl_sercom.o
+ .text._spi_sync_disable
+                0x00000000       0x1e hpl/sercom/hpl_sercom.o
+ .text._spi_async_disable
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_set_mode
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._spi_set_baudrate
+                0x00000000       0x14 hpl/sercom/hpl_sercom.o
+ .text._spi_set_char_size
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_set_data_order
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._get_sercom_index
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+ .text._usart_init
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+ .text._sercom_i2c_send_address
+                0x00000000       0xc0 hpl/sercom/hpl_sercom.o
+ .text._get_i2c_s_index
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+ .text._i2c_s_init
+                0x00000000       0x80 hpl/sercom/hpl_sercom.o
+ .text._usart_set_baud_rate
+                0x00000000       0x58 hpl/sercom/hpl_sercom.o
+ .text._usart_set_data_order
+                0x00000000       0x70 hpl/sercom/hpl_sercom.o
+ .text._usart_set_mode
+                0x00000000       0x70 hpl/sercom/hpl_sercom.o
+ .text._usart_set_parity
+                0x00000000       0x98 hpl/sercom/hpl_sercom.o
+ .text._usart_set_stop_bits
+                0x00000000       0x6c hpl/sercom/hpl_sercom.o
+ .text._usart_set_character_size
+                0x00000000       0x68 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_set_address
+                0x00000000       0x68 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_init
+                0x00000000       0x2c hpl/sercom/hpl_sercom.o
+ .text._usart_async_init
+                0x00000000       0x80 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_deinit
+                0x00000000       0x20 hpl/sercom/hpl_sercom.o
+ .text._usart_async_deinit
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+ .text._usart_sync_calculate_baud_rate
+                0x00000000       0x18 hpl/sercom/hpl_sercom.o
+ .text._usart_async_calculate_baud_rate
+                0x00000000       0x18 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_enable
+                0x00000000       0x12 hpl/sercom/hpl_sercom.o
+ .text._usart_async_enable
+                0x00000000       0x12 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_disable
+                0x00000000       0x12 hpl/sercom/hpl_sercom.o
+ .text._usart_async_disable
+                0x00000000       0x12 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_baud_rate
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_baud_rate
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_data_order
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_data_order
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_mode
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_mode
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_parity
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_parity
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_stop_bits
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_stop_bits
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_character_size
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_character_size
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_get_status
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_async_get_status
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_write_byte
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_async_write_byte
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_read_byte
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_is_ready_to_send
+                0x00000000        0xa hpl/sercom/hpl_sercom.o
+ .text._usart_sync_is_transmit_done
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._usart_async_is_byte_sent
+                0x00000000        0xa hpl/sercom/hpl_sercom.o
+ .text._usart_sync_is_byte_received
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._usart_sync_set_flow_control_state
+                0x00000000        0x2 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_flow_control_state
+                0x00000000        0x2 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_get_flow_control_state
+                0x00000000        0x4 hpl/sercom/hpl_sercom.o
+ .text._usart_async_get_flow_control_state
+                0x00000000        0x4 hpl/sercom/hpl_sercom.o
+ .text._usart_async_enable_byte_sent_irq
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_async_enable_tx_done_irq
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._usart_sync_get_hardware_index
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_get_hardware_index
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._usart_async_set_irq_state
+                0x00000000       0x78 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_enable
+                0x00000000       0x80 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_disable
+                0x00000000       0x70 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_set_baudrate
+                0x00000000      0x168 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_init
+                0x00000000       0x84 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_deinit
+                0x00000000       0x44 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_transfer
+                0x00000000       0x94 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_register_callback
+                0x00000000       0x1c hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_send_stop
+                0x00000000       0x16 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_get_bytes_left
+                0x00000000        0xe hpl/sercom/hpl_sercom.o
+ .text._i2c_m_sync_deinit
+                0x00000000       0x44 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_sync_disable
+                0x00000000       0x48 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_sync_set_baudrate
+                0x00000000      0x168 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_async_set_irq_state
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._i2c_m_sync_send_stop
+                0x00000000       0x16 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_init
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_init
+                0x00000000       0x8c hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_deinit
+                0x00000000       0x22 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_deinit
+                0x00000000       0x50 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_enable
+                0x00000000       0x14 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_enable
+                0x00000000       0x14 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_disable
+                0x00000000       0x14 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_disable
+                0x00000000       0x14 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_is_10bit_addressing_on
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_is_10bit_addressing_on
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_set_address
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_set_address
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_write_byte
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_write_byte
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_read_byte
+                0x00000000        0xa hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_is_byte_sent
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_is_byte_received
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_get_status
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_sync_clear_data_ready_flag
+                0x00000000        0xa hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_get_status
+                0x00000000        0x8 hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_abort_transmission
+                0x00000000        0xa hpl/sercom/hpl_sercom.o
+ .text._i2c_s_async_set_irq_state
+                0x00000000       0x54 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_init
+                0x00000000      0x1fc hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_init
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_init
+                0x00000000       0x60 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_init
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_deinit
+                0x00000000       0x54 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_deinit
+                0x00000000       0x54 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_deinit
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_deinit
+                0x00000000       0x10 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_enable
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_enable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_enable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_enable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_disable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_disable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_disable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_disable
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_set_mode
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_set_mode
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_set_mode
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_set_mode
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_calc_baud_val
+                0x00000000       0x5c hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_set_baudrate
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_set_baudrate
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_set_char_size
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_set_char_size
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_set_char_size
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_set_char_size
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_set_data_order
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_set_data_order
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_set_data_order
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_set_data_order
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_m_sync_trans
+                0x00000000      0x114 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_enable_tx
+                0x00000000       0x40 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_enable_tx
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_enable_rx
+                0x00000000       0x48 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_enable_rx
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_enable_tx_complete
+                0x00000000       0x44 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_enable_ss_detect
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_write_one
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_write_one
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_write_one
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_read_one
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_read_one
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_read_one
+                0x00000000       0x34 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_register_callback
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_register_callback
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_is_tx_ready
+                0x00000000       0x38 hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_is_rx_ready
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_is_ss_deactivated
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_sync_is_error
+                0x00000000       0x44 hpl/sercom/hpl_sercom.o
+ .text._spi_m_async_set_irq_state
+                0x00000000       0x3c hpl/sercom/hpl_sercom.o
+ .text._spi_s_async_set_irq_state
+                0x00000000        0xc hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000      0x89e hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000      0x16d hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x22 hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x87 hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x51 hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0xef hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x6a hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000      0x1df hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x22 hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x3f hpl/sercom/hpl_sercom.o
+ .debug_macro   0x00000000       0x1c hpl/sercom/hpl_sercom.o
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+ .debug_macro   0x00000000      0x4da hpl/sercom/hpl_sercom.o
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+ .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
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+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+rom              0x00000000         0x00040000         xr
+ram              0x20000000         0x00008000         xrw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+LOAD atmel_start.o
+LOAD Device_Startup/startup_saml22.o
+LOAD Device_Startup/system_saml22.o
+LOAD driver_init.o
+LOAD examples/driver_examples.o
+LOAD hal/src/hal_adc_sync.o
+LOAD hal/src/hal_atomic.o
+LOAD hal/src/hal_calendar.o
+LOAD hal/src/hal_delay.o
+LOAD hal/src/hal_ext_irq.o
+LOAD hal/src/hal_gpio.o
+LOAD hal/src/hal_i2c_m_sync.o
+LOAD hal/src/hal_init.o
+LOAD hal/src/hal_io.o
+LOAD hal/src/hal_pwm.o
+LOAD hal/src/hal_slcd_sync.o
+LOAD hal/src/hal_sleep.o
+LOAD hal/utils/src/utils_assert.o
+LOAD hal/utils/src/utils_event.o
+LOAD hal/utils/src/utils_list.o
+LOAD hal/utils/src/utils_syscalls.o
+LOAD hpl/adc/hpl_adc.o
+LOAD hpl/core/hpl_core_m0plus_base.o
+LOAD hpl/core/hpl_init.o
+LOAD hpl/dmac/hpl_dmac.o
+LOAD hpl/eic/hpl_eic.o
+LOAD hpl/gclk/hpl_gclk.o
+LOAD hpl/mclk/hpl_mclk.o
+LOAD hpl/osc32kctrl/hpl_osc32kctrl.o
+LOAD hpl/oscctrl/hpl_oscctrl.o
+LOAD hpl/pm/hpl_pm.o
+LOAD hpl/rtc/hpl_rtc.o
+LOAD hpl/sercom/hpl_sercom.o
+LOAD hpl/slcd/hpl_slcd.o
+LOAD hpl/systick/hpl_systick.o
+LOAD hpl/tcc/hpl_tcc.o
+LOAD hpl/tc/hpl_tc.o
+LOAD main.o
+LOAD sleep_manager/sleep_manager.o
+LOAD sleep_manager_main.o
+LOAD watch-library/watch.o
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+                0x00002000                STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0x2000
+
+.text           0x00000000     0x2140
+                0x00000000                . = ALIGN (0x4)
+                0x00000000                _sfixed = .
+ *(.vectors .vectors.*)
+ .vectors       0x00000000       0xa8 Device_Startup/startup_saml22.o
+                0x00000000                exception_table
+ *(.text .text.* .gnu.linkonce.t.*)
+ .text          0x000000a8       0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .text.atmel_start_init
+                0x00000108       0x14 atmel_start.o
+                0x00000108                atmel_start_init
+ .text.Dummy_Handler
+                0x0000011c        0x2 Device_Startup/startup_saml22.o
+                0x0000011c                SVCall_Handler
+                0x0000011c                DMAC_Handler
+                0x0000011c                TRNG_Handler
+                0x0000011c                HardFault_Handler
+                0x0000011c                TC2_Handler
+                0x0000011c                AC_Handler
+                0x0000011c                SysTick_Handler
+                0x0000011c                PendSV_Handler
+                0x0000011c                SERCOM1_Handler
+                0x0000011c                ADC_Handler
+                0x0000011c                NonMaskableInt_Handler
+                0x0000011c                SERCOM2_Handler
+                0x0000011c                WDT_Handler
+                0x0000011c                TC1_Handler
+                0x0000011c                USB_Handler
+                0x0000011c                Dummy_Handler
+                0x0000011c                EVSYS_Handler
+                0x0000011c                SERCOM3_Handler
+                0x0000011c                NVMCTRL_Handler
+                0x0000011c                SYSTEM_Handler
+                0x0000011c                SERCOM0_Handler
+                0x0000011c                PTC_Handler
+                0x0000011c                FREQM_Handler
+                0x0000011c                TC0_Handler
+                0x0000011c                SLCD_Handler
+                0x0000011c                AES_Handler
+ *fill*         0x0000011e        0x2 
+ .text.Reset_Handler
+                0x00000120       0x68 Device_Startup/startup_saml22.o
+                0x00000120                Reset_Handler
+ .text.CALENDAR_0_CLOCK_init
+                0x00000188       0x14 driver_init.o
+                0x00000188                CALENDAR_0_CLOCK_init
+ .text.CALENDAR_0_init
+                0x0000019c       0x20 driver_init.o
+                0x0000019c                CALENDAR_0_init
+ .text.I2C_0_PORT_init
+                0x000001bc       0x54 driver_init.o
+                0x000001bc                I2C_0_PORT_init
+ .text.I2C_0_CLOCK_init
+                0x00000210       0x24 driver_init.o
+                0x00000210                I2C_0_CLOCK_init
+ .text.I2C_0_init
+                0x00000234       0x28 driver_init.o
+                0x00000234                I2C_0_init
+ .text.delay_driver_init
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+                0x0000025c                delay_driver_init
+ .text.PWM_0_PORT_init
+                0x00000270       0x44 driver_init.o
+                0x00000270                PWM_0_PORT_init
+ .text.PWM_0_CLOCK_init
+                0x000002b4       0x20 driver_init.o
+                0x000002b4                PWM_0_CLOCK_init
+ .text.PWM_0_init
+                0x000002d4       0x34 driver_init.o
+                0x000002d4                PWM_0_init
+ .text.system_init
+                0x00000308       0x94 driver_init.o
+                0x00000308                system_init
+ .text.leap_year
+                0x0000039c        0xc hal/src/hal_calendar.o
+ .text.get_secs_in_month
+                0x000003a8       0x64 hal/src/hal_calendar.o
+ .text.convert_timestamp_to_datetime
+                0x0000040c       0xac hal/src/hal_calendar.o
+ .text.convert_datetime_to_timestamp
+                0x000004b8       0xb8 hal/src/hal_calendar.o
+ .text.calibrate_timestamp
+                0x00000570       0x80 hal/src/hal_calendar.o
+ .text.fill_alarm
+                0x000005f0       0xc4 hal/src/hal_calendar.o
+ .text.calendar_init
+                0x000006b4       0x48 hal/src/hal_calendar.o
+                0x000006b4                calendar_init
+ .text.calendar_enable
+                0x000006fc       0x2c hal/src/hal_calendar.o
+                0x000006fc                calendar_enable
+ .text.calendar_set_time
+                0x00000728       0x64 hal/src/hal_calendar.o
+                0x00000728                calendar_set_time
+ .text.calendar_set_date
+                0x0000078c       0x64 hal/src/hal_calendar.o
+                0x0000078c                calendar_set_date
+ .text.calendar_get_date_time
+                0x000007f0       0x3c hal/src/hal_calendar.o
+                0x000007f0                calendar_get_date_time
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+                0x0000082c                delay_init
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+ .text.i2c_m_sync_read
+                0x00000874       0x34 hal/src/hal_i2c_m_sync.o
+ .text.i2c_m_sync_init
+                0x000008a8       0x40 hal/src/hal_i2c_m_sync.o
+                0x000008a8                i2c_m_sync_init
+ .text.i2c_m_sync_enable
+                0x000008e8        0xc hal/src/hal_i2c_m_sync.o
+                0x000008e8                i2c_m_sync_enable
+ .text.i2c_m_sync_set_slaveaddr
+                0x000008f4       0x12 hal/src/hal_i2c_m_sync.o
+                0x000008f4                i2c_m_sync_set_slaveaddr
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+                0x00000906                i2c_m_sync_get_io_descriptor
+ *fill*         0x0000090e        0x2 
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+                0x00000910                io_write
+ .text.io_read  0x00000948       0x38 hal/src/hal_io.o
+                0x00000948                io_read
+ .text.pwm_period_expired
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+ .text.pwm_detect_fault
+                0x0000098c        0xc hal/src/hal_pwm.o
+ .text.pwm_init
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+                0x00000998                pwm_init
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+                0x000009e8                pwm_enable
+ .text.pwm_set_parameters
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+                0x00000a2c                pwm_set_parameters
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+                0x00000a68                assert
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+                0x00000a70                event_subscribe
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+                0x00000b10                list_insert_as_head
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+                0x00000b3c                _init_chip
+ .text._ext_irq_handler
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+ .text.EIC_Handler
+                0x00000c34        0xc hpl/eic/hpl_eic.o
+                0x00000c34                EIC_Handler
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+                0x00000c40                _gclk_init_generators_by_fref
+ .text._mclk_init
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+                0x00000c78                _mclk_init
+ .text._osc32kctrl_init_sources
+                0x00000c88       0x24 hpl/osc32kctrl/hpl_osc32kctrl.o
+                0x00000c88                _osc32kctrl_init_sources
+ .text._oscctrl_init_sources
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+                0x00000cac                _oscctrl_init_sources
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+                0x00000ce4        0x2 hpl/oscctrl/hpl_oscctrl.o
+                0x00000ce4                _oscctrl_init_referenced_generators
+ *fill*         0x00000ce6        0x2 
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+                0x00000ce8       0x2c hpl/pm/hpl_pm.o
+                0x00000ce8                _set_performance_level
+ .text._rtc_interrupt_handler
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+ *fill*         0x00000d46        0x2 
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+                0x00000d48                _calendar_init
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+                0x00000dd8                _calendar_enable
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+                0x00000e1c                _calendar_set_counter
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+                0x00000e54                _calendar_get_counter
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+                0x00000e88                RTC_Handler
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+ .text._get_i2cm_index
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+                0x00001230                _i2c_m_sync_init
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+                0x00001260                _i2c_m_sync_enable
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+                0x000012e0                _i2c_m_sync_transfer
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+                0x000015e4                _tc_is_pwm_enabled
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diff --git a/Smol Watch Project/My Project/Debug/atmel_start.d b/Smol Watch Project/My Project/Debug/atmel_start.d
new file mode 100644
index 0000000..0aceee6
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/atmel_start.d	
@@ -0,0 +1,433 @@
+atmel_start.d atmel_start.o: .././atmel_start.c ../atmel_start.h \
+ ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_missing_features.h ../hal/include/hal_ext_irq.h \
+ ../hal/include/hpl_ext_irq.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hpl/tc/hpl_tc_base.h \
+ ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h ../sleep_manager_main.h \
+ ../sleep_manager/sleep_manager.h ../hal/utils/include/utils_event.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/events.h
+
+../atmel_start.h:
+
+../driver_init.h:
+
+../atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../sleep_manager_main.h:
+
+../sleep_manager/sleep_manager.h:
+
+../hal/utils/include/utils_event.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/events.h:
diff --git a/Smol Watch Project/My Project/Debug/atmel_start.o b/Smol Watch Project/My Project/Debug/atmel_start.o
new file mode 100644
index 0000000..c7ea221
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/atmel_start.o differ
diff --git a/Smol Watch Project/My Project/Debug/driver_init.d b/Smol Watch Project/My Project/Debug/driver_init.d
new file mode 100644
index 0000000..a1fd95a
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/driver_init.d	
@@ -0,0 +1,434 @@
+driver_init.d driver_init.o: .././driver_init.c .././driver_init.h \
+ .././atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_missing_features.h ../hal/include/hal_ext_irq.h \
+ ../hal/include/hpl_ext_irq.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hpl/tc/hpl_tc_base.h \
+ ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h ../Config/peripheral_clk_config.h \
+ ../Config/hpl_osc32kctrl_config.h ../hal/utils/include/utils.h \
+ ../hpl/adc/hpl_adc_base.h ../hal/include/hpl_adc_async.h \
+ ../hal/include/hpl_adc_sync.h
+
+.././driver_init.h:
+
+.././atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/utils/include/utils.h:
+
+../hpl/adc/hpl_adc_base.h:
+
+../hal/include/hpl_adc_async.h:
+
+../hal/include/hpl_adc_sync.h:
diff --git a/Smol Watch Project/My Project/Debug/driver_init.o b/Smol Watch Project/My Project/Debug/driver_init.o
new file mode 100644
index 0000000..c412af5
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/driver_init.o differ
diff --git a/Smol Watch Project/My Project/Debug/examples/driver_examples.d b/Smol Watch Project/My Project/Debug/examples/driver_examples.d
new file mode 100644
index 0000000..1a2dd8c
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/examples/driver_examples.d	
@@ -0,0 +1,424 @@
+examples/driver_examples.d examples/driver_examples.o: \
+ ../examples/driver_examples.c ../examples/driver_examples.h \
+ ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_missing_features.h ../hal/include/hal_ext_irq.h \
+ ../hal/include/hpl_ext_irq.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hpl/tc/hpl_tc_base.h \
+ ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h ../hal/utils/include/utils.h
+
+../examples/driver_examples.h:
+
+../driver_init.h:
+
+../atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../hal/utils/include/utils.h:
diff --git a/Smol Watch Project/My Project/Debug/examples/driver_examples.o b/Smol Watch Project/My Project/Debug/examples/driver_examples.o
new file mode 100644
index 0000000..cc48205
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/examples/driver_examples.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.d b/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.d
new file mode 100644
index 0000000..e1e47e5
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.d	
@@ -0,0 +1,345 @@
+hal/src/hal_adc_sync.d hal/src/hal_adc_sync.o: ../hal/src/hal_adc_sync.c \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_missing_features.h \
+ ../hal/utils/include/utils_assert.h
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.o b/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.o
new file mode 100644
index 0000000..9412bb4
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_adc_sync.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.d b/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.d
new file mode 100644
index 0000000..8903787
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.d	
@@ -0,0 +1,335 @@
+hal/src/hal_atomic.d hal/src/hal_atomic.o: ../hal/src/hal_atomic.c \
+ ../hal/include/hal_atomic.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hri/hri_adc_l22.h ../hri/hri_aes_l22.h \
+ ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h ../hri/hri_dsu_l22.h \
+ ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h ../hri/hri_freqm_l22.h \
+ ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h ../hri/hri_mtb_l22.h \
+ ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/include/hal_atomic.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.o b/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.o
new file mode 100644
index 0000000..a120e63
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_atomic.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.d b/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.d
new file mode 100644
index 0000000..3ff2e99
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.d	
@@ -0,0 +1,350 @@
+hal/src/hal_calendar.d hal/src/hal_calendar.o: ../hal/src/hal_calendar.c \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.o b/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.o
new file mode 100644
index 0000000..fe4f010
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_calendar.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_delay.d b/Smol Watch Project/My Project/Debug/hal/src/hal_delay.d
new file mode 100644
index 0000000..1f5d578
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_delay.d	
@@ -0,0 +1,347 @@
+hal/src/hal_delay.d hal/src/hal_delay.o: ../hal/src/hal_delay.c \
+ ../hal/include/hpl_irq.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_reset.h \
+ ../hal/include/hpl_sleep.h ../hal/include/hal_delay.h \
+ ../hal/include/hpl_delay.h
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_delay.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_delay.o b/Smol Watch Project/My Project/Debug/hal/src/hal_delay.o
new file mode 100644
index 0000000..15e608b
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_delay.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.d b/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.d
new file mode 100644
index 0000000..68dc055
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.d	
@@ -0,0 +1,340 @@
+hal/src/hal_ext_irq.d hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c \
+ ../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.o b/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.o
new file mode 100644
index 0000000..0cab237
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_ext_irq.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.d b/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.d
new file mode 100644
index 0000000..fd051e0
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.d	
@@ -0,0 +1,347 @@
+hal/src/hal_gpio.d hal/src/hal_gpio.o: ../hal/src/hal_gpio.c \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.o b/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.o
new file mode 100644
index 0000000..8dfde30
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_gpio.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.d b/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.d
new file mode 100644
index 0000000..65d8ec0
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.d	
@@ -0,0 +1,347 @@
+hal/src/hal_i2c_m_sync.d hal/src/hal_i2c_m_sync.o: \
+ ../hal/src/hal_i2c_m_sync.c ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hal_io.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hal_io.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.o b/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.o
new file mode 100644
index 0000000..abd246d
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_i2c_m_sync.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_init.d b/Smol Watch Project/My Project/Debug/hal/src/hal_init.d
new file mode 100644
index 0000000..81a2b98
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_init.d	
@@ -0,0 +1,340 @@
+hal/src/hal_init.d hal/src/hal_init.o: ../hal/src/hal_init.c \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_init.o b/Smol Watch Project/My Project/Debug/hal/src/hal_init.o
new file mode 100644
index 0000000..8bb5da0
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_init.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_io.d b/Smol Watch Project/My Project/Debug/hal/src/hal_io.d
new file mode 100644
index 0000000..1c1f72f
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_io.d	
@@ -0,0 +1,339 @@
+hal/src/hal_io.d hal/src/hal_io.o: ../hal/src/hal_io.c \
+ ../hal/include/hal_io.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+
+../hal/include/hal_io.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_io.o b/Smol Watch Project/My Project/Debug/hal/src/hal_io.o
new file mode 100644
index 0000000..94a7d91
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_io.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.d b/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.d
new file mode 100644
index 0000000..fdb3f96
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.d	
@@ -0,0 +1,347 @@
+hal/src/hal_pwm.d hal/src/hal_pwm.o: ../hal/src/hal_pwm.c \
+ ../hal/include/hal_pwm.h ../hal/include/hpl_pwm.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/utils.h
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/utils.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.o b/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.o
new file mode 100644
index 0000000..a408307
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_pwm.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.d b/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.d
new file mode 100644
index 0000000..bfe0570
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.d	
@@ -0,0 +1,345 @@
+hal/src/hal_slcd_sync.d hal/src/hal_slcd_sync.o: \
+ ../hal/src/hal_slcd_sync.c ../hal/include/hal_slcd_sync.h \
+ ../hal/include/hpl_slcd_sync.h ../hal/include/hpl_slcd.h \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.o b/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.o
new file mode 100644
index 0000000..d983f51
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_slcd_sync.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.d b/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.d
new file mode 100644
index 0000000..99b766a
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.d	
@@ -0,0 +1,340 @@
+hal/src/hal_sleep.d hal/src/hal_sleep.o: ../hal/src/hal_sleep.c \
+ ../hal/include/hal_sleep.h ../hal/include/hpl_sleep.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.o b/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.o
new file mode 100644
index 0000000..7cd675f
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/src/hal_sleep.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.d b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.d
new file mode 100644
index 0000000..aa216d6
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.d	
@@ -0,0 +1,338 @@
+hal/utils/src/utils_assert.d hal/utils/src/utils_assert.o: \
+ ../hal/utils/src/utils_assert.c ../hal/utils/include/utils_assert.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.o b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.o
new file mode 100644
index 0000000..ca1504d
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_assert.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.d b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.d
new file mode 100644
index 0000000..aa76e8d
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.d	
@@ -0,0 +1,387 @@
+hal/utils/src/utils_event.d hal/utils/src/utils_event.o: \
+ ../hal/utils/src/utils_event.c ../hal/utils/include/utils_event.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_list.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/events.h \
+ ../hal/utils/include/utils_assert.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h
+
+../hal/utils/include/utils_event.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/events.h:
+
+../hal/utils/include/utils_assert.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.o b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.o
new file mode 100644
index 0000000..8212b7e
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_event.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.d b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.d
new file mode 100644
index 0000000..d9379a5
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.d	
@@ -0,0 +1,340 @@
+hal/utils/src/utils_list.d hal/utils/src/utils_list.o: \
+ ../hal/utils/src/utils_list.c ../hal/utils/include/utils_list.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+
+../hal/utils/include/utils_list.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.o b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.o
new file mode 100644
index 0000000..0a98d44
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_list.o differ
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.d b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.d
new file mode 100644
index 0000000..e48bca8
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.d	
@@ -0,0 +1,98 @@
+hal/utils/src/utils_syscalls.d hal/utils/src/utils_syscalls.o: \
+ ../hal/utils/src/utils_syscalls.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
diff --git a/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.o b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.o
new file mode 100644
index 0000000..807df4c
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hal/utils/src/utils_syscalls.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.d b/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.d
new file mode 100644
index 0000000..4df6043
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.d	
@@ -0,0 +1,360 @@
+hpl/adc/hpl_adc.d hpl/adc/hpl_adc.o: ../hpl/adc/hpl_adc.c \
+ ../hal/include/hpl_adc_async.h ../hal/include/hpl_adc_sync.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_adc_dma.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils_assert.h \
+ ../hal/utils/include/utils_repeat_macro.h \
+ ../hal/utils/include/utils_increment_macro.h ../Config/hpl_adc_config.h
+
+../hal/include/hpl_adc_async.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_adc_dma.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/utils_repeat_macro.h:
+
+../hal/utils/include/utils_increment_macro.h:
+
+../Config/hpl_adc_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.o b/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.o
new file mode 100644
index 0000000..0cd69c7
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/adc/hpl_adc.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.d b/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.d
new file mode 100644
index 0000000..98a14b8
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.d	
@@ -0,0 +1,360 @@
+hpl/core/hpl_core_m0plus_base.d hpl/core/hpl_core_m0plus_base.o: \
+ ../hpl/core/hpl_core_m0plus_base.c ../hal/include/hpl_core.h \
+ ../hpl/core/hpl_core_port.h ../Config/peripheral_clk_config.h \
+ ../Config/hpl_osc32kctrl_config.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hpl_delay.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h
+
+../hal/include/hpl_core.h:
+
+../hpl/core/hpl_core_port.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hpl_delay.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.o b/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.o
new file mode 100644
index 0000000..1fdece0
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/core/hpl_core_m0plus_base.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.d b/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.d
new file mode 100644
index 0000000..9fb9d61
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.d	
@@ -0,0 +1,364 @@
+hpl/core/hpl_init.d hpl/core/hpl_init.o: ../hpl/core/hpl_init.c \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hpl_init.h ../hpl/gclk/hpl_gclk_base.h \
+ ../Config/hpl_mclk_config.h ../Config/peripheral_clk_config.h \
+ ../Config/hpl_osc32kctrl_config.h ../hal/include/hpl_dma.h \
+ ../hal/include/hpl_irq.h ../Config/hpl_dmac_config.h
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hpl_init.h:
+
+../hpl/gclk/hpl_gclk_base.h:
+
+../Config/hpl_mclk_config.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/include/hpl_dma.h:
+
+../hal/include/hpl_irq.h:
+
+../Config/hpl_dmac_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.o b/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.o
new file mode 100644
index 0000000..682c75a
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/core/hpl_init.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.d b/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.d
new file mode 100644
index 0000000..679e1bb
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.d	
@@ -0,0 +1,353 @@
+hpl/dmac/hpl_dmac.d hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_dma.h \
+ ../hal/include/hpl_irq.h ../Config/hpl_dmac_config.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h \
+ ../hal/utils/include/utils_repeat_macro.h \
+ ../hal/utils/include/utils_increment_macro.h
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_dma.h:
+
+../hal/include/hpl_irq.h:
+
+../Config/hpl_dmac_config.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/utils_repeat_macro.h:
+
+../hal/utils/include/utils_increment_macro.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.o b/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.o
new file mode 100644
index 0000000..fae5daa
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/dmac/hpl_dmac.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.d b/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.d
new file mode 100644
index 0000000..8be16af
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.d	
@@ -0,0 +1,384 @@
+hpl/eic/hpl_eic.d hpl/eic/hpl_eic.o: ../hpl/eic/hpl_eic.c \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../Config/hpl_eic_config.h \
+ ../hal/include/hpl_ext_irq.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../Config/hpl_eic_config.h:
+
+../hal/include/hpl_ext_irq.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.o b/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.o
new file mode 100644
index 0000000..fa16052
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/eic/hpl_eic.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.d b/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.d
new file mode 100644
index 0000000..fb30c10
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.d	
@@ -0,0 +1,342 @@
+hpl/gclk/hpl_gclk.d hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c \
+ ../Config/hpl_gclk_config.h ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h
+
+../Config/hpl_gclk_config.h:
+
+../hal/include/hpl_init.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.o b/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.o
new file mode 100644
index 0000000..ebaa9cb
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/gclk/hpl_gclk.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.d b/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.d
new file mode 100644
index 0000000..e61ee56
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.d	
@@ -0,0 +1,342 @@
+hpl/mclk/hpl_mclk.d hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../Config/hpl_mclk_config.h \
+ ../Config/peripheral_clk_config.h ../Config/hpl_osc32kctrl_config.h
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../Config/hpl_mclk_config.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.o b/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.o
new file mode 100644
index 0000000..cd21916
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/mclk/hpl_mclk.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.d b/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.d
new file mode 100644
index 0000000..2af8901
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.d	
@@ -0,0 +1,340 @@
+hpl/osc32kctrl/hpl_osc32kctrl.d hpl/osc32kctrl/hpl_osc32kctrl.o: \
+ ../hpl/osc32kctrl/hpl_osc32kctrl.c ../hal/include/hpl_init.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../Config/hpl_osc32kctrl_config.h
+
+../hal/include/hpl_init.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../Config/hpl_osc32kctrl_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.o b/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.o
new file mode 100644
index 0000000..9275944
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/osc32kctrl/hpl_osc32kctrl.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.d b/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.d
new file mode 100644
index 0000000..1897bd0
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.d	
@@ -0,0 +1,340 @@
+hpl/oscctrl/hpl_oscctrl.d hpl/oscctrl/hpl_oscctrl.o: \
+ ../hpl/oscctrl/hpl_oscctrl.c ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_init.h \
+ ../Config/hpl_oscctrl_config.h
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_init.h:
+
+../Config/hpl_oscctrl_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.o b/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.o
new file mode 100644
index 0000000..5c00324
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/oscctrl/hpl_oscctrl.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.d b/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.d
new file mode 100644
index 0000000..590c2cd
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.d	
@@ -0,0 +1,342 @@
+hpl/pm/hpl_pm.d hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c \
+ ../hal/include/hpl_sleep.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_reset.h \
+ ../hal/include/hpl_init.h
+
+../hal/include/hpl_sleep.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_init.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.o b/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.o
new file mode 100644
index 0000000..1e96fa9
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/pm/hpl_pm.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.d b/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.d
new file mode 100644
index 0000000..23d03c1
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.d	
@@ -0,0 +1,347 @@
+hpl/rtc/hpl_rtc.d hpl/rtc/hpl_rtc.o: ../hpl/rtc/hpl_rtc.c \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils_assert.h \
+ ../Config/hpl_rtc_config.h
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_rtc_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.o b/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.o
new file mode 100644
index 0000000..af5e19d
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/rtc/hpl_rtc.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.d b/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.d
new file mode 100644
index 0000000..f89d344
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.d	
@@ -0,0 +1,395 @@
+hpl/sercom/hpl_sercom.d hpl/sercom/hpl_sercom.o: \
+ ../hpl/sercom/hpl_sercom.c ../hal/include/hpl_dma.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_i2c_m_async.h ../hal/include/hpl_i2c_m_sync.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hpl_i2c_s_async.h \
+ ../hal/include/hpl_i2c_s_sync.h ../Config/hpl_sercom_config.h \
+ ../Config/peripheral_clk_config.h ../Config/hpl_osc32kctrl_config.h \
+ ../hal/include/hpl_spi_m_async.h ../hal/include/hpl_spi.h \
+ ../hal/include/hpl_spi_async.h ../hal/include/hpl_spi_m_sync.h \
+ ../hal/include/hpl_spi_sync.h ../hal/include/hpl_spi_s_async.h \
+ ../hal/include/hpl_spi_s_sync.h ../hal/include/hpl_usart_async.h \
+ ../hal/include/hpl_usart.h ../hal/include/hpl_usart_sync.h \
+ ../hal/include/hpl_usart.h ../hal/utils/include/utils_assert.h
+
+../hal/include/hpl_dma.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_i2c_m_async.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_s_async.h:
+
+../hal/include/hpl_i2c_s_sync.h:
+
+../Config/hpl_sercom_config.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/include/hpl_spi_m_async.h:
+
+../hal/include/hpl_spi.h:
+
+../hal/include/hpl_spi_async.h:
+
+../hal/include/hpl_spi_m_sync.h:
+
+../hal/include/hpl_spi_sync.h:
+
+../hal/include/hpl_spi_s_async.h:
+
+../hal/include/hpl_spi_s_sync.h:
+
+../hal/include/hpl_usart_async.h:
+
+../hal/include/hpl_usart.h:
+
+../hal/include/hpl_usart_sync.h:
+
+../hal/include/hpl_usart.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.o b/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.o
new file mode 100644
index 0000000..563384a
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/sercom/hpl_sercom.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.d b/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.d
new file mode 100644
index 0000000..aad4138
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.d	
@@ -0,0 +1,358 @@
+hpl/slcd/hpl_slcd.d hpl/slcd/hpl_slcd.o: ../hpl/slcd/hpl_slcd.c \
+ ../hal/utils/include/utils_assert.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h ../Config/hpl_slcd_config.h \
+ ../hpl/slcd/hpl_slcd_cm.h ../Config/peripheral_clk_config.h \
+ ../Config/hpl_osc32kctrl_config.h \
+ ../hpl/slcd/hpl_slcd_cm_7_seg_mapping.h \
+ ../hpl/slcd/hpl_slcd_cm_14_seg_mapping.h
+
+../hal/utils/include/utils_assert.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../Config/hpl_slcd_config.h:
+
+../hpl/slcd/hpl_slcd_cm.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hpl/slcd/hpl_slcd_cm_7_seg_mapping.h:
+
+../hpl/slcd/hpl_slcd_cm_14_seg_mapping.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.o b/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.o
new file mode 100644
index 0000000..2f0a690
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/slcd/hpl_slcd.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.d b/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.d
new file mode 100644
index 0000000..d4275e3
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.d	
@@ -0,0 +1,340 @@
+hpl/systick/hpl_systick.d hpl/systick/hpl_systick.o: \
+ ../hpl/systick/hpl_systick.c ../hal/include/hpl_time_measure.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../Config/hpl_systick_config.h
+
+../hal/include/hpl_time_measure.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../Config/hpl_systick_config.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.o b/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.o
new file mode 100644
index 0000000..9d47116
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/systick/hpl_systick.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.d b/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.d
new file mode 100644
index 0000000..c7a07d1
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.d	
@@ -0,0 +1,359 @@
+hpl/tc/hpl_tc.d hpl/tc/hpl_tc.o: ../hpl/tc/hpl_tc.c \
+ ../hal/include/hpl_pwm.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \
+ ../Config/hpl_tc_config.h ../Config/peripheral_clk_config.h \
+ ../Config/hpl_osc32kctrl_config.h ../hal/include/hpl_timer.h \
+ ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_assert.h ../hpl/tc/hpl_tc_base.h
+
+../hal/include/hpl_pwm.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_irq.h:
+
+../Config/hpl_tc_config.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/include/hpl_timer.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
+
+../hpl/tc/hpl_tc_base.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.o b/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.o
new file mode 100644
index 0000000..aacfa51
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/tc/hpl_tc.o differ
diff --git a/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.d b/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.d
new file mode 100644
index 0000000..04ebedb
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.d	
@@ -0,0 +1,359 @@
+hpl/tcc/hpl_tcc.d hpl/tcc/hpl_tcc.o: ../hpl/tcc/hpl_tcc.c \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/include/hpl_pwm.h \
+ ../hal/include/hpl_irq.h ../hpl/tcc/hpl_tcc.h ../hal/include/hpl_timer.h \
+ ../hal/include/hpl_irq.h ../Config/hpl_tcc_config.h \
+ ../Config/peripheral_clk_config.h ../Config/hpl_osc32kctrl_config.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/include/hpl_pwm.h:
+
+../hal/include/hpl_irq.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hpl_timer.h:
+
+../hal/include/hpl_irq.h:
+
+../Config/hpl_tcc_config.h:
+
+../Config/peripheral_clk_config.h:
+
+../Config/hpl_osc32kctrl_config.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.o b/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.o
new file mode 100644
index 0000000..c47dfd7
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/hpl/tcc/hpl_tcc.o differ
diff --git a/Smol Watch Project/My Project/Debug/main.d b/Smol Watch Project/My Project/Debug/main.d
new file mode 100644
index 0000000..77a174c
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/main.d	
@@ -0,0 +1,438 @@
+main.d main.o: .././main.c ../atmel_start.h ../driver_init.h \
+ ../atmel_start_pins.h ../hal/include/hal_gpio.h \
+ ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_missing_features.h ../hal/include/hal_ext_irq.h \
+ ../hal/include/hpl_ext_irq.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hpl/tc/hpl_tc_base.h \
+ ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h ../sleep_manager_main.h \
+ ../sleep_manager/sleep_manager.h ../hal/utils/include/utils_event.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/events.h \
+ .././watch-library/watch.h ../hal/include/hpl_calendar.h
+
+../atmel_start.h:
+
+../driver_init.h:
+
+../atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+../sleep_manager_main.h:
+
+../sleep_manager/sleep_manager.h:
+
+../hal/utils/include/utils_event.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/events.h:
+
+.././watch-library/watch.h:
+
+../hal/include/hpl_calendar.h:
diff --git a/Smol Watch Project/My Project/Debug/main.o b/Smol Watch Project/My Project/Debug/main.o
new file mode 100644
index 0000000..36f21e9
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/main.o differ
diff --git a/Smol Watch Project/My Project/Debug/makedep.mk b/Smol Watch Project/My Project/Debug/makedep.mk
new file mode 100644
index 0000000..4fdfcec
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/makedep.mk	
@@ -0,0 +1,86 @@
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+atmel_start.c
+
+Device_Startup\startup_saml22.c
+
+Device_Startup\system_saml22.c
+
+driver_init.c
+
+examples\driver_examples.c
+
+hal\src\hal_adc_sync.c
+
+hal\src\hal_atomic.c
+
+hal\src\hal_calendar.c
+
+hal\src\hal_delay.c
+
+hal\src\hal_ext_irq.c
+
+hal\src\hal_gpio.c
+
+hal\src\hal_i2c_m_sync.c
+
+hal\src\hal_init.c
+
+hal\src\hal_io.c
+
+hal\src\hal_pwm.c
+
+hal\src\hal_slcd_sync.c
+
+hal\src\hal_sleep.c
+
+hal\utils\src\utils_assert.c
+
+hal\utils\src\utils_event.c
+
+hal\utils\src\utils_list.c
+
+hal\utils\src\utils_syscalls.c
+
+hpl\adc\hpl_adc.c
+
+hpl\core\hpl_core_m0plus_base.c
+
+hpl\core\hpl_init.c
+
+hpl\dmac\hpl_dmac.c
+
+hpl\eic\hpl_eic.c
+
+hpl\gclk\hpl_gclk.c
+
+hpl\mclk\hpl_mclk.c
+
+hpl\osc32kctrl\hpl_osc32kctrl.c
+
+hpl\oscctrl\hpl_oscctrl.c
+
+hpl\pm\hpl_pm.c
+
+hpl\rtc\hpl_rtc.c
+
+hpl\sercom\hpl_sercom.c
+
+hpl\slcd\hpl_slcd.c
+
+hpl\systick\hpl_systick.c
+
+hpl\tcc\hpl_tcc.c
+
+hpl\tc\hpl_tc.c
+
+main.c
+
+sleep_manager\sleep_manager.c
+
+sleep_manager_main.c
+
+watch-library\watch.c
+
diff --git a/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.d b/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.d
new file mode 100644
index 0000000..09ed508
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.d	
@@ -0,0 +1,355 @@
+sleep_manager/sleep_manager.d sleep_manager/sleep_manager.o: \
+ ../sleep_manager/sleep_manager.c ../sleep_manager/sleep_manager.h \
+ ../hal/utils/include/utils_event.h ../hal/utils/include/utils.h \
+ ../hal/utils/include/utils_list.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/events.h \
+ ../hal/include/hal_sleep.h ../hal/include/hpl_sleep.h \
+ ../hal/utils/include/utils_assert.h
+
+../sleep_manager/sleep_manager.h:
+
+../hal/utils/include/utils_event.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/events.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/utils/include/utils_assert.h:
diff --git a/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.o b/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.o
new file mode 100644
index 0000000..3a9d201
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/sleep_manager/sleep_manager.o differ
diff --git a/Smol Watch Project/My Project/Debug/sleep_manager_main.d b/Smol Watch Project/My Project/Debug/sleep_manager_main.d
new file mode 100644
index 0000000..996e288
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/sleep_manager_main.d	
@@ -0,0 +1,434 @@
+sleep_manager_main.d sleep_manager_main.o: .././sleep_manager_main.c \
+ .././atmel_start.h .././driver_init.h .././atmel_start_pins.h \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \
+ ../hal/utils/include/utils_assert.h ../Config/hpl_port_config.h \
+ ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \
+ ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \
+ ../hal/include/hal_init.h ../hal/include/hpl_init.h \
+ ../hal/include/hal_io.h ../hal/include/hal_sleep.h \
+ ../hal/include/hal_adc_sync.h ../hal/include/hpl_adc_sync.h \
+ ../hal/include/hpl_missing_features.h ../hal/include/hal_ext_irq.h \
+ ../hal/include/hpl_ext_irq.h ../hal/include/hal_calendar.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../hal/include/hal_i2c_m_sync.h \
+ ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_pwm.h \
+ ../hal/include/hpl_pwm.h ../hpl/tc/hpl_tc_base.h \
+ ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h .././sleep_manager_main.h \
+ ../sleep_manager/sleep_manager.h ../hal/utils/include/utils_event.h \
+ ../hal/utils/include/utils.h ../hal/utils/include/events.h
+
+.././atmel_start.h:
+
+.././driver_init.h:
+
+.././atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
+
+.././sleep_manager_main.h:
+
+../sleep_manager/sleep_manager.h:
+
+../hal/utils/include/utils_event.h:
+
+../hal/utils/include/utils.h:
+
+../hal/utils/include/events.h:
diff --git a/Smol Watch Project/My Project/Debug/sleep_manager_main.o b/Smol Watch Project/My Project/Debug/sleep_manager_main.o
new file mode 100644
index 0000000..be9c916
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/sleep_manager_main.o differ
diff --git a/Smol Watch Project/My Project/Debug/watch-library/watch.d b/Smol Watch Project/My Project/Debug/watch-library/watch.d
new file mode 100644
index 0000000..838c982
--- /dev/null
+++ b/Smol Watch Project/My Project/Debug/watch-library/watch.d	
@@ -0,0 +1,424 @@
+watch-library/watch.d watch-library/watch.o: ../watch-library/watch.c \
+ ../watch-library/watch.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ../hal/include/hpl_calendar.h ../hal/utils/include/compiler.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ ../hal/utils/include/parts.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h \
+ ../hri/hri_l22.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h \
+ ../hri/hri_ac_l22.h ../hal/include/hal_atomic.h ../hri/hri_adc_l22.h \
+ ../hri/hri_aes_l22.h ../hri/hri_ccl_l22.h ../hri/hri_dmac_l22.h \
+ ../hri/hri_dsu_l22.h ../hri/hri_eic_l22.h ../hri/hri_evsys_l22.h \
+ ../hri/hri_freqm_l22.h ../hri/hri_gclk_l22.h ../hri/hri_mclk_l22.h \
+ ../hri/hri_mtb_l22.h ../hri/hri_nvic_l22.h ../hri/hri_nvmctrl_l22.h \
+ ../hri/hri_osc32kctrl_l22.h ../hri/hri_oscctrl_l22.h \
+ ../hri/hri_pac_l22.h ../hri/hri_pm_l22.h ../hri/hri_port_l22.h \
+ ../hri/hri_rstc_l22.h ../hri/hri_rtc_l22.h ../hri/hri_sercom_l22.h \
+ ../hri/hri_slcd_l22.h ../hri/hri_supc_l22.h \
+ ../hri/hri_systemcontrol_l22.h ../hri/hri_systick_l22.h \
+ ../hri/hri_tc_l22.h ../hri/hri_tcc_l22.h ../hri/hri_trng_l22.h \
+ ../hri/hri_usb_l22.h ../hri/hri_wdt_l22.h \
+ ../hal/utils/include/err_codes.h ../hal/utils/include/utils_list.h \
+ ../hal/include/hpl_irq.h ../driver_init.h ../atmel_start_pins.h \
+ ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \
+ ../hpl/port/hpl_gpio_base.h ../hal/utils/include/utils_assert.h \
+ ../Config/hpl_port_config.h ../hal/include/hal_delay.h \
+ ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \
+ ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \
+ ../hal/include/hpl_init.h ../hal/include/hal_io.h \
+ ../hal/include/hal_sleep.h ../hal/include/hal_adc_sync.h \
+ ../hal/include/hpl_adc_sync.h ../hal/include/hpl_missing_features.h \
+ ../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \
+ ../hal/include/hal_calendar.h ../hal/include/hpl_calendar.h \
+ ../hal/include/hal_i2c_m_sync.h ../hal/include/hpl_i2c_m_sync.h \
+ ../hal/include/hal_pwm.h ../hal/include/hpl_pwm.h \
+ ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_timer.h ../hpl/tcc/hpl_tcc.h \
+ ../hal/include/hal_slcd_sync.h ../hal/include/hpl_slcd_sync.h \
+ ../hal/include/hpl_slcd.h
+
+../watch-library/watch.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/utils/include/compiler.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+../hal/utils/include/parts.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/saml22j18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/mpu_armv7.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/system_saml22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/sercom.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/tcc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/component/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/adc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/aes.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ccl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dmac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/dsu.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/eic.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/evsys.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/freqm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/gclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mclk.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/mtb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/nvmctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/oscctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/osc32kctrl.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pac.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/pm.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/port.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/ptc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rstc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/rtc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/sercom3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/slcd.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/supc.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc1.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc2.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tc3.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/tcc0.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/trng.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/usb.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/instance/wdt.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/pio/saml22j18a.h:
+
+../hri/hri_l22.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include/sam.h:
+
+../hri/hri_ac_l22.h:
+
+../hal/include/hal_atomic.h:
+
+../hri/hri_adc_l22.h:
+
+../hri/hri_aes_l22.h:
+
+../hri/hri_ccl_l22.h:
+
+../hri/hri_dmac_l22.h:
+
+../hri/hri_dsu_l22.h:
+
+../hri/hri_eic_l22.h:
+
+../hri/hri_evsys_l22.h:
+
+../hri/hri_freqm_l22.h:
+
+../hri/hri_gclk_l22.h:
+
+../hri/hri_mclk_l22.h:
+
+../hri/hri_mtb_l22.h:
+
+../hri/hri_nvic_l22.h:
+
+../hri/hri_nvmctrl_l22.h:
+
+../hri/hri_osc32kctrl_l22.h:
+
+../hri/hri_oscctrl_l22.h:
+
+../hri/hri_pac_l22.h:
+
+../hri/hri_pm_l22.h:
+
+../hri/hri_port_l22.h:
+
+../hri/hri_rstc_l22.h:
+
+../hri/hri_rtc_l22.h:
+
+../hri/hri_sercom_l22.h:
+
+../hri/hri_slcd_l22.h:
+
+../hri/hri_supc_l22.h:
+
+../hri/hri_systemcontrol_l22.h:
+
+../hri/hri_systick_l22.h:
+
+../hri/hri_tc_l22.h:
+
+../hri/hri_tcc_l22.h:
+
+../hri/hri_trng_l22.h:
+
+../hri/hri_usb_l22.h:
+
+../hri/hri_wdt_l22.h:
+
+../hal/utils/include/err_codes.h:
+
+../hal/utils/include/utils_list.h:
+
+../hal/include/hpl_irq.h:
+
+../driver_init.h:
+
+../atmel_start_pins.h:
+
+../hal/include/hal_gpio.h:
+
+../hal/include/hpl_gpio.h:
+
+../hpl/port/hpl_gpio_base.h:
+
+../hal/utils/include/utils_assert.h:
+
+../Config/hpl_port_config.h:
+
+../hal/include/hal_delay.h:
+
+../hal/include/hpl_irq.h:
+
+../hal/include/hpl_reset.h:
+
+../hal/include/hpl_sleep.h:
+
+../hal/include/hal_init.h:
+
+../hal/include/hpl_init.h:
+
+../hal/include/hal_io.h:
+
+../hal/include/hal_sleep.h:
+
+../hal/include/hal_adc_sync.h:
+
+../hal/include/hpl_adc_sync.h:
+
+../hal/include/hpl_missing_features.h:
+
+../hal/include/hal_ext_irq.h:
+
+../hal/include/hpl_ext_irq.h:
+
+../hal/include/hal_calendar.h:
+
+../hal/include/hpl_calendar.h:
+
+../hal/include/hal_i2c_m_sync.h:
+
+../hal/include/hpl_i2c_m_sync.h:
+
+../hal/include/hal_pwm.h:
+
+../hal/include/hpl_pwm.h:
+
+../hpl/tc/hpl_tc_base.h:
+
+../hal/include/hpl_timer.h:
+
+../hpl/tcc/hpl_tcc.h:
+
+../hal/include/hal_slcd_sync.h:
+
+../hal/include/hpl_slcd_sync.h:
+
+../hal/include/hpl_slcd.h:
diff --git a/Smol Watch Project/My Project/Debug/watch-library/watch.o b/Smol Watch Project/My Project/Debug/watch-library/watch.o
new file mode 100644
index 0000000..21ba853
Binary files /dev/null and b/Smol Watch Project/My Project/Debug/watch-library/watch.o differ
diff --git a/Smol Watch Project/My Project/Default.xml b/Smol Watch Project/My Project/Default.xml
new file mode 100644
index 0000000..cd31a2b
--- /dev/null
+++ b/Smol Watch Project/My Project/Default.xml	
@@ -0,0 +1,475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
+	<Configurations>
+		<Configuration z:Id="i2">
+			<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>DebugLevel</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>IncludePaths</d4p1:Key>
+					<d4p1:Value>NDEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-std=gnu99</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>OptimizationLevel</d4p1:Key>
+					<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolDefines</d4p1:Key>
+					<d4p1:Value>NDEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolUndefines</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Verbose</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>WarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Compiler_dictionary>
+			<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Libraries</d4p1:Key>
+					<d4p1:Value>libm</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>LibrarySearchPath</d4p1:Key>
+					<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-Tsaml22j18a_flash.ld</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Linker_dictionary>
+			<Name>Release</Name>
+		</Configuration>
+		<Configuration z:Id="i3">
+			<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>DebugLevel</d4p1:Key>
+					<d4p1:Value>Maximum (-g3)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>IncludePaths</d4p1:Key>
+					<d4p1:Value>DEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-std=gnu99</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>OptimizationLevel</d4p1:Key>
+					<d4p1:Value>Optimize debugging experience (-Og)</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolDefines</d4p1:Key>
+					<d4p1:Value>DEBUG</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>SymbolUndefines</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Verbose</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>WarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Compiler_dictionary>
+			<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>Libraries</d4p1:Key>
+					<d4p1:Value>libm</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>LibrarySearchPath</d4p1:Key>
+					<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>MiscellaneousSettings</d4p1:Key>
+					<d4p1:Value>-Tsaml22j18a_flash.ld</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
+					<d4p1:Value>None</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
+					<d4p1:Value>True</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
+					<d4p1:Value>False</d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+				<d4p1:KeyValueOfstringstring>
+					<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
+					<d4p1:Value></d4p1:Value>
+				</d4p1:KeyValueOfstringstring>
+			</Linker_dictionary>
+			<Name>Debug</Name>
+		</Configuration>
+	</Configurations>
+</Configurations>
\ No newline at end of file
diff --git a/Smol Watch Project/My Project/Device_Startup/saml22j18a_flash.ld b/Smol Watch Project/My Project/Device_Startup/saml22j18a_flash.ld
new file mode 100644
index 0000000..b6b68f3
--- /dev/null
+++ b/Smol Watch Project/My Project/Device_Startup/saml22j18a_flash.ld	
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAML22J18A
+ *
+ * Copyright (c) 2018 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/Smol Watch Project/My Project/Device_Startup/saml22j18a_sram.ld b/Smol Watch Project/My Project/Device_Startup/saml22j18a_sram.ld
new file mode 100644
index 0000000..3e6279d
--- /dev/null
+++ b/Smol Watch Project/My Project/Device_Startup/saml22j18a_sram.ld	
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAML22J18A
+ *
+ * Copyright (c) 2018 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/Smol Watch Project/My Project/Device_Startup/startup_saml22.c b/Smol Watch Project/My Project/Device_Startup/startup_saml22.c
new file mode 100644
index 0000000..7bd85ca
--- /dev/null
+++ b/Smol Watch Project/My Project/Device_Startup/startup_saml22.c	
@@ -0,0 +1,225 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAML22
+ *
+ * Copyright (c) 2018 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "saml22.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SYSTEM_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM3
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void SLCD_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_AES
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TRNG
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pvReservedM12          = (void*) (0UL), /* Reserved */
+        .pvReservedM11          = (void*) (0UL), /* Reserved */
+        .pvReservedM10          = (void*) (0UL), /* Reserved */
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pvReservedM4           = (void*) (0UL), /* Reserved */
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnSYSTEM_Handler      = (void*) SYSTEM_Handler,         /*  0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /*  1 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /*  2 Real-Time Counter */
+        .pfnEIC_Handler         = (void*) EIC_Handler,            /*  3 External Interrupt Controller */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /*  4 Frequency Meter */
+#ifdef ID_USB
+        .pfnUSB_Handler         = (void*) USB_Handler,            /*  5 Universal Serial Bus */
+#else
+        .pvReserved5            = (void*) (0UL),                  /*  5 Reserved */
+#endif
+        .pfnNVMCTRL_Handler     = (void*) NVMCTRL_Handler,        /*  6 Non-Volatile Memory Controller */
+        .pfnDMAC_Handler        = (void*) DMAC_Handler,           /*  7 Direct Memory Access Controller */
+        .pfnEVSYS_Handler       = (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        .pfnSERCOM0_Handler     = (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        .pfnSERCOM1_Handler     = (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        .pfnSERCOM2_Handler     = (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+#ifdef ID_SERCOM3
+        .pfnSERCOM3_Handler     = (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#else
+        .pvReserved12           = (void*) (0UL),                  /* 12 Reserved */
+#endif
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_Handler     = (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        .pvReserved13           = (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_Handler     = (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        .pvReserved14           = (void*) (0UL),                  /* 14 Reserved */
+#endif
+        .pfnTCC0_Handler        = (void*) TCC0_Handler,           /* 15 Timer Counter Control */
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 16 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 17 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 18 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 19 Basic Timer Counter 3 */
+        .pfnADC_Handler         = (void*) ADC_Handler,            /* 20 Analog Digital Converter */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 21 Analog Comparators */
+#ifdef ID_PTC
+        .pfnPTC_Handler         = (void*) PTC_Handler,            /* 22 Peripheral Touch Controller */
+#else
+        .pvReserved22           = (void*) (0UL),                  /* 22 Reserved */
+#endif
+        .pfnSLCD_Handler        = (void*) SLCD_Handler,           /* 23 Segment Liquid Crystal Display Controller */
+#ifdef ID_AES
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 24 Advanced Encryption Standard */
+#else
+        .pvReserved24           = (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_TRNG
+        .pfnTRNG_Handler        = (void*) TRNG_Handler            /* 25 True Random Generator */
+#else
+        .pvReserved25           = (void*) (0UL)                   /* 25 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        /* Initialize the C library */
+        __libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/Smol Watch Project/My Project/Device_Startup/system_saml22.c b/Smol Watch Project/My Project/Device_Startup/system_saml22.c
new file mode 100644
index 0000000..3c8fd29
--- /dev/null
+++ b/Smol Watch Project/My Project/Device_Startup/system_saml22.c	
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2018 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "saml22.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+        // Keep the default device state after reset
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+        // Not implemented
+        SystemCoreClock = __SYSTEM_CLOCK;
+        return;
+}
diff --git a/Smol Watch Project/My Project/My Project.componentinfo.xml b/Smol Watch Project/My Project/My Project.componentinfo.xml
new file mode 100644
index 0000000..95f62c9
--- /dev/null
+++ b/Smol Watch Project/My Project/My Project.componentinfo.xml	
@@ -0,0 +1,169 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+	<ProjectComponents>
+		<ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+			<CApiVersion></CApiVersion>
+			<CBundle></CBundle>
+			<CClass>CMSIS</CClass>
+			<CGroup>CORE</CGroup>
+			<CSub></CSub>
+			<CVariant></CVariant>
+			<CVendor>ARM</CVendor>
+			<CVersion>5.1.2</CVersion>
+			<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+			<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
+			<Description></Description>
+			<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html</AbsolutePath>
+					<Attribute></Attribute>
+					<Category>doc</Category>
+					<Condition></Condition>
+					<FileContentHash i:nil="true" />
+					<FileVersion></FileVersion>
+					<Name>CMSIS/Documentation/Core/html/index.html</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\</AbsolutePath>
+					<Attribute></Attribute>
+					<Category>include</Category>
+					<Condition></Condition>
+					<FileContentHash i:nil="true" />
+					<FileVersion></FileVersion>
+					<Name>CMSIS/Core/Include/</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+			</Files>
+			<PackName>CMSIS</PackName>
+			<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
+			<PackVersion>5.4.0</PackVersion>
+			<PresentInProject>true</PresentInProject>
+			<ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
+			<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:string></d4p1:string>
+			</RteComponents>
+			<Status>Resolved</Status>
+			<VersionMode>Fixed</VersionMode>
+			<IsComponentInAtProject>true</IsComponentInAtProject>
+		</ProjectComponent>
+		<ProjectComponent z:Id="i2" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+			<CApiVersion></CApiVersion>
+			<CBundle></CBundle>
+			<CClass>Device</CClass>
+			<CGroup>Startup</CGroup>
+			<CSub></CSub>
+			<CVariant></CVariant>
+			<CVendor>Atmel</CVendor>
+			<CVersion>1.2.0</CVersion>
+			<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+			<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:anyType z:Ref="i1" />
+			</DependentComponents>
+			<Description></Description>
+			<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include</AbsolutePath>
+					<Attribute></Attribute>
+					<Category>include</Category>
+					<Condition>C</Condition>
+					<FileContentHash i:nil="true" />
+					<FileVersion></FileVersion>
+					<Name>include</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include\sam.h</AbsolutePath>
+					<Attribute></Attribute>
+					<Category>header</Category>
+					<Condition>C</Condition>
+					<FileContentHash>hIYDkoKMf0OfmYW7d/j2kw==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>include/sam.h</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\templates\main.c</AbsolutePath>
+					<Attribute>template</Attribute>
+					<Category>source</Category>
+					<Condition>C Exe</Condition>
+					<FileContentHash>D8GE7XTFu2b4QutVWp6lCg==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>templates/main.c</Name>
+					<SelectString>Main file (.c)</SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\templates\main.cpp</AbsolutePath>
+					<Attribute>template</Attribute>
+					<Category>source</Category>
+					<Condition>C Exe</Condition>
+					<FileContentHash>nU+WlKcYaWh0AWBBS+WVpA==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>templates/main.cpp</Name>
+					<SelectString>Main file (.cpp)</SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\system_saml22.c</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>source</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>PrvYHyBfxNZHSGYPLxcSug==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>gcc/system_saml22.c</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\startup_saml22.c</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>source</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>BLzyJq7J25P7XTztxvVwNw==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>gcc/gcc/startup_saml22.c</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\saml22j18a_flash.ld</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>linkerScript</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>Ys4aTlim2ZJU0Qo003K8VQ==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>gcc/gcc/saml22j18a_flash.ld</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+				<d4p1:anyType i:type="FileInfo">
+					<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\saml22j18a_sram.ld</AbsolutePath>
+					<Attribute>config</Attribute>
+					<Category>other</Category>
+					<Condition>GCC Exe</Condition>
+					<FileContentHash>hDqTHEM9gCdn4WKPS2tHzg==</FileContentHash>
+					<FileVersion></FileVersion>
+					<Name>gcc/gcc/saml22j18a_sram.ld</Name>
+					<SelectString></SelectString>
+					<SourcePath></SourcePath>
+				</d4p1:anyType>
+			</Files>
+			<PackName>SAML22_DFP</PackName>
+			<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAML22_DFP/1.2.77/Atmel.SAML22_DFP.pdsc</PackPath>
+			<PackVersion>1.2.77</PackVersion>
+			<PresentInProject>true</PresentInProject>
+			<ReferenceConditionId>ATSAML22J18A</ReferenceConditionId>
+			<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+				<d4p1:string></d4p1:string>
+			</RteComponents>
+			<Status>Resolved</Status>
+			<VersionMode>Fixed</VersionMode>
+			<IsComponentInAtProject>true</IsComponentInAtProject>
+		</ProjectComponent>
+	</ProjectComponents>
+</Store>
\ No newline at end of file
diff --git a/Smol Watch Project/My Project/My Project.cproj b/Smol Watch Project/My Project/My Project.cproj
new file mode 100644
index 0000000..bffa970
--- /dev/null
+++ b/Smol Watch Project/My Project/My Project.cproj	
@@ -0,0 +1,1040 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
+    <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
+    <avrdevice>ATSAML22J18A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>C</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>My Project</AssemblyName>
+    <Name>My Project</Name>
+    <RootNamespace>My Project</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>0</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <Compiler>gcc</Compiler>
+    <atStartFilePath>.atmelstart\atmel_start_config.atstart</atStartFilePath>
+    <GpdscFilePath>.atmelstart\AtmelStart.gpdsc</GpdscFilePath>
+    <AcmeProjectConfig>
+      <AcmeProjectConfig>
+        <TopLevelComponents>
+          <AcmeProjectComponent IsAutoGenerated="false" CClass="AtmelStart" Cgroup="Framework" CVersion="1.0.0" />
+          <AcmeProjectComponent IsAutoGenerated="false" CClass="CMSIS" Cgroup="CORE" CVersion="5.1.2" />
+          <AcmeProjectComponent IsAutoGenerated="false" CClass="Device" Cgroup="Startup" CVersion="1.2.0" />
+        </TopLevelComponents>
+        <AcmeActionInfos>
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_atomic.h" IsConfig="false" Hash="dAg/XLzGqPqh12ZGWK6HLw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_calendar.h" IsConfig="false" Hash="IOHRFf7MhZs7fuBZjRT+9Q" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_delay.h" IsConfig="false" Hash="snalDV+S1QGquCV38zAdoA" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_ext_irq.h" IsConfig="false" Hash="sm9cN3GPkLctaX5iRw7wzw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_gpio.h" IsConfig="false" Hash="3mBEQ9Ix28YOArddDes83Q" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_i2c_m_sync.h" IsConfig="false" Hash="wYjgBbVVd/11drj/bh4EaQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_init.h" IsConfig="false" Hash="OrYSVpF3YA5XrOBImWpdSg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_io.h" IsConfig="false" Hash="XZRSabc39WU/0MFBLYGLvQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_slcd_sync.h" IsConfig="false" Hash="dFBZDIPKIaMtJ6KD3XUQSw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hal_sleep.h" IsConfig="false" Hash="KuZDwgrLdU+fuMG82ZFTqg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_adc_dma.h" IsConfig="false" Hash="ZNWJ5APLfPqPLqI7LDqlMA" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_core.h" IsConfig="false" Hash="XeEtUlBSwXUmLA41hFYYWg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_delay.h" IsConfig="false" Hash="3tgjyGPrs0ePCewpMUQPbQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_dma.h" IsConfig="false" Hash="C3XG0wWxKLSRQVHSNMCgIQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_ext_irq.h" IsConfig="false" Hash="IEyup/01CSWudIu8vklYPQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_gpio.h" IsConfig="false" Hash="kGeglKjrgbcKZDOsM+XTrw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_i2c_m_async.h" IsConfig="false" Hash="2YKSxDd++st93P4wS0x3sw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_i2c_m_sync.h" IsConfig="false" Hash="9PBv4UnwhtkmG2PaLCX74Q" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_i2c_s_async.h" IsConfig="false" Hash="rC7cV+Zqg8W12ys0twQG1w" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_i2c_s_sync.h" IsConfig="false" Hash="JNLMe72Fd6Uy3vXkh8HGxg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_init.h" IsConfig="false" Hash="QtMCPnjBzySOYli3ce/dyQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_irq.h" IsConfig="false" Hash="n8mGC0gLHfUhVTjLflKVXw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_slcd.h" IsConfig="false" Hash="jgX8EWZhgDk54rgf3g31+g" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_slcd_sync.h" IsConfig="false" Hash="nQlsLbODGl1sCT2yMjkbug" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_sleep.h" IsConfig="false" Hash="JOXa2/KqNtt950+B1ZJfSQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi.h" IsConfig="false" Hash="wAxvxvj1p/CvWEoawsWIBw" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_async.h" IsConfig="false" Hash="sUIART4unR3sm4AlXv5LlQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_spi_sync.h" IsConfig="false" Hash="Qr5slVYsVsngWiAyjLwx8A" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_time_measure.h" IsConfig="false" Hash="3gMv9Ur+2bKt2LK5h7IEcQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/include/hpl_usart.h" IsConfig="false" Hash="gkIcItnlv0v8NvwxEz9neA" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_atomic.c" IsConfig="false" Hash="jOsfB5ZnunjCPnUQXuXi9g" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_delay.c" IsConfig="false" Hash="vZ+YYOpHjTcAZaAaTE3Izg" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_gpio.c" IsConfig="false" Hash="wIzN9zQd1b8qd+RDoSkD7Q" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_i2c_m_sync.c" IsConfig="false" Hash="rXHlXpjvdMJ9o6yJQwR90g" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_init.c" IsConfig="false" Hash="bJvq8kpNbbOE2nZfChOGTQ" />
+          <AcmeProjectActionInfo Action="File" Source="hal/src/hal_io.c" IsConfig="false" Hash="FYpavzYSxhFzVrBQtcH2ZA" />
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+    </Compile>
+    <Compile Include="hpl\tc\hpl_tc.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hpl\tc\hpl_tc_base.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_ac_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_adc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_aes_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_ccl_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_dmac_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_dsu_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_eic_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_evsys_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_freqm_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_gclk_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_mclk_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_mtb_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_nvic_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_nvmctrl_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_osc32kctrl_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_oscctrl_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pac_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pm_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_port_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rstc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rtc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_sercom_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_slcd_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_supc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_systemcontrol_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_systick_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tcc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tc_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_trng_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_usb_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_wdt_l22.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="main.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="sleep_manager\sleep_manager.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="sleep_manager\sleep_manager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="sleep_manager_main.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="sleep_manager_main.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="watch-library\watch.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="watch-library\watch.h">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Config\" />
+    <Folder Include="Device_Startup\" />
+    <Folder Include="documentation\" />
+    <Folder Include="examples\" />
+    <Folder Include="hal\" />
+    <Folder Include="hal\documentation\" />
+    <Folder Include="hal\include\" />
+    <Folder Include="hal\src\" />
+    <Folder Include="hal\utils\" />
+    <Folder Include="hal\utils\include\" />
+    <Folder Include="hal\utils\src\" />
+    <Folder Include="hpl\" />
+    <Folder Include="hpl\adc\" />
+    <Folder Include="hpl\core\" />
+    <Folder Include="hpl\dmac\" />
+    <Folder Include="hpl\eic\" />
+    <Folder Include="hpl\gclk\" />
+    <Folder Include="hpl\mclk\" />
+    <Folder Include="hpl\osc32kctrl\" />
+    <Folder Include="hpl\oscctrl\" />
+    <Folder Include="hpl\pm\" />
+    <Folder Include="hpl\port\" />
+    <Folder Include="hpl\rtc\" />
+    <Folder Include="hpl\sercom\" />
+    <Folder Include="hpl\slcd\" />
+    <Folder Include="hpl\systick\" />
+    <Folder Include="hpl\tcc\" />
+    <Folder Include="hpl\tc\" />
+    <Folder Include="hri\" />
+    <Folder Include="sleep_manager\" />
+    <Folder Include="watch-library" />
+  </ItemGroup>
+  <ItemGroup>
+    <None Include="Device_Startup\saml22j18a_flash.ld">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="Device_Startup\saml22j18a_sram.ld">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="documentation\sleep_manager.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\adc_sync.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\calendar.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\ext_irq.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\i2c_master_sync.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\pwm.rst">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="hal\documentation\slcd_sync.rst">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/Smol Watch Project/My Project/atmel_start.c b/Smol Watch Project/My Project/atmel_start.c
new file mode 100644
index 0000000..b54b7d2
--- /dev/null
+++ b/Smol Watch Project/My Project/atmel_start.c	
@@ -0,0 +1,10 @@
+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+	sleep_manager_init();
+}
diff --git a/Smol Watch Project/My Project/atmel_start.h b/Smol Watch Project/My Project/atmel_start.h
new file mode 100644
index 0000000..01435cc
--- /dev/null
+++ b/Smol Watch Project/My Project/atmel_start.h	
@@ -0,0 +1,19 @@
+#ifndef ATMEL_START_H_INCLUDED
+#define ATMEL_START_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "driver_init.h"
+#include "sleep_manager_main.h"
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/Smol Watch Project/My Project/atmel_start_pins.h b/Smol Watch Project/My Project/atmel_start_pins.h
new file mode 100644
index 0000000..36fe6bf
--- /dev/null
+++ b/Smol Watch Project/My Project/atmel_start_pins.h	
@@ -0,0 +1,67 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include <hal_gpio.h>
+
+// SAML22 has 9 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+#define GPIO_PIN_FUNCTION_E 4
+#define GPIO_PIN_FUNCTION_F 5
+#define GPIO_PIN_FUNCTION_G 6
+#define GPIO_PIN_FUNCTION_H 7
+#define GPIO_PIN_FUNCTION_I 8
+
+#define VBUS_DET GPIO(GPIO_PORTA, 2)
+#define SEG1 GPIO(GPIO_PORTA, 4)
+#define SEG2 GPIO(GPIO_PORTA, 5)
+#define SEG3 GPIO(GPIO_PORTA, 6)
+#define SEG4 GPIO(GPIO_PORTA, 7)
+#define SEG5 GPIO(GPIO_PORTA, 8)
+#define SEG6 GPIO(GPIO_PORTA, 9)
+#define SEG7 GPIO(GPIO_PORTA, 10)
+#define SEG8 GPIO(GPIO_PORTA, 11)
+#define SEG14 GPIO(GPIO_PORTA, 12)
+#define SEG15 GPIO(GPIO_PORTA, 13)
+#define SEG16 GPIO(GPIO_PORTA, 14)
+#define SEG17 GPIO(GPIO_PORTA, 15)
+#define SEG18 GPIO(GPIO_PORTA, 16)
+#define SEG19 GPIO(GPIO_PORTA, 17)
+#define SEG20 GPIO(GPIO_PORTA, 18)
+#define SEG21 GPIO(GPIO_PORTA, 19)
+#define RED GPIO(GPIO_PORTA, 20)
+#define GREEN GPIO(GPIO_PORTA, 21)
+#define BTN_LIGHT GPIO(GPIO_PORTA, 22)
+#define BTN_MODE GPIO(GPIO_PORTA, 23)
+#define BUZZER GPIO(GPIO_PORTA, 27)
+#define D1 GPIO(GPIO_PORTB, 0)
+#define A1 GPIO(GPIO_PORTB, 1)
+#define A2 GPIO(GPIO_PORTB, 2)
+#define D0 GPIO(GPIO_PORTB, 3)
+#define A0 GPIO(GPIO_PORTB, 4)
+#define BTN_ALARM GPIO(GPIO_PORTB, 5)
+#define COM0 GPIO(GPIO_PORTB, 6)
+#define COM1 GPIO(GPIO_PORTB, 7)
+#define COM2 GPIO(GPIO_PORTB, 8)
+#define SEG0 GPIO(GPIO_PORTB, 9)
+#define SEG9 GPIO(GPIO_PORTB, 11)
+#define SEG10 GPIO(GPIO_PORTB, 12)
+#define SEG11 GPIO(GPIO_PORTB, 13)
+#define SEG12 GPIO(GPIO_PORTB, 14)
+#define SEG13 GPIO(GPIO_PORTB, 15)
+#define SEG22 GPIO(GPIO_PORTB, 16)
+#define SEG23 GPIO(GPIO_PORTB, 17)
+#define SDA GPIO(GPIO_PORTB, 30)
+#define SCL GPIO(GPIO_PORTB, 31)
+
+#endif // ATMEL_START_PINS_H_INCLUDED
diff --git a/Smol Watch Project/My Project/documentation/sleep_manager.rst b/Smol Watch Project/My Project/documentation/sleep_manager.rst
new file mode 100644
index 0000000..a374558
--- /dev/null
+++ b/Smol Watch Project/My Project/documentation/sleep_manager.rst	
@@ -0,0 +1,38 @@
+=============
+Sleep Manager
+=============
+
+The sleep manager is the middle-ware which provides means to control the sleep of
+an MCU by multiple software modules.
+
+The sleep manager uses publish-subscribe pattern to ask subscribers if they are
+ready to sleep and to notify them about preparation to sleep and waking up.
+
+If any of the subscribers is not ready to go to sleep, an MCU may stay in active
+mode. To let the sleep manager know that a software module is not ready to sleep,
+the parameter passed to callback must to set to false. No additional action is
+required from the software module to state that it is ready to go to sleep.
+Notification about waking up is delivered to all subscribers with information
+about wake-up reason.
+
+There are currently only two wake-up reasons: internal interrupt and external
+interrupt. It is up to the user to extend this list if required.
+
+Features
+--------
+
+* Sleep control
+* Notifications:
+	* ready to sleep
+	* preparation to sleep
+	* waking up
+
+Dependencies
+------------
+
+* The sleep driver
+
+Limitations
+-----------
+
+* Only two wake-up reasons are supported by default
diff --git a/Smol Watch Project/My Project/driver_init.c b/Smol Watch Project/My Project/driver_init.c
new file mode 100644
index 0000000..b10ed0e
--- /dev/null
+++ b/Smol Watch Project/My Project/driver_init.c	
@@ -0,0 +1,334 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_init.h"
+#include <peripheral_clk_config.h>
+#include <utils.h>
+#include <hal_init.h>
+
+#include <hpl_adc_base.h>
+
+struct slcd_sync_descriptor SEGMENT_LCD_0;
+
+struct adc_sync_descriptor ADC_0;
+
+struct calendar_descriptor CALENDAR_0;
+
+struct i2c_m_sync_desc I2C_0;
+
+struct pwm_descriptor PWM_0;
+
+struct pwm_descriptor PWM_1;
+
+void ADC_0_PORT_init(void)
+{
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(A1, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(A1, PINMUX_PB01B_ADC_AIN9);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(A2, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(A2, PINMUX_PB02B_ADC_AIN10);
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(A0, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(A0, PINMUX_PB04B_ADC_AIN12);
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_ADC_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC_GCLK_ID, CONF_GCLK_ADC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC, (void *)NULL);
+}
+
+void EXTERNAL_IRQ_0_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_mclk_set_APBAMASK_EIC_bit(MCLK);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(BTN_ALARM, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(BTN_ALARM,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_DOWN);
+
+	gpio_set_pin_function(BTN_ALARM, PINMUX_PB05A_EIC_EXTINT5);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(BTN_LIGHT, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(BTN_LIGHT,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_DOWN);
+
+	gpio_set_pin_function(BTN_LIGHT, PINMUX_PA22A_EIC_EXTINT6);
+
+	// Set pin direction to input
+	gpio_set_pin_direction(BTN_MODE, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(BTN_MODE,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_DOWN);
+
+	gpio_set_pin_function(BTN_MODE, PINMUX_PA23A_EIC_EXTINT7);
+
+	ext_irq_init();
+}
+
+void CALENDAR_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBAMASK_RTC_bit(MCLK);
+}
+
+void CALENDAR_0_init(void)
+{
+	CALENDAR_0_CLOCK_init();
+	calendar_init(&CALENDAR_0, RTC);
+}
+
+void I2C_0_PORT_init(void)
+{
+
+	gpio_set_pin_pull_mode(SDA,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SDA, PINMUX_PB30C_SERCOM1_PAD0);
+
+	gpio_set_pin_pull_mode(SCL,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(SCL, PINMUX_PB31C_SERCOM1_PAD1);
+}
+
+void I2C_0_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_mclk_set_APBCMASK_SERCOM1_bit(MCLK);
+}
+
+void I2C_0_init(void)
+{
+	I2C_0_CLOCK_init();
+	i2c_m_sync_init(&I2C_0, SERCOM1);
+	I2C_0_PORT_init();
+}
+
+void delay_driver_init(void)
+{
+	delay_init(SysTick);
+}
+
+void PWM_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(RED, PINMUX_PA20E_TC3_WO0);
+
+	gpio_set_pin_function(GREEN, PINMUX_PA21E_TC3_WO1);
+}
+
+void PWM_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_TC3_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TC3_GCLK_ID, CONF_GCLK_TC3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_0_init(void)
+{
+	PWM_0_CLOCK_init();
+	PWM_0_PORT_init();
+	pwm_init(&PWM_0, TC3, _tc_get_pwm());
+}
+
+void PWM_1_PORT_init(void)
+{
+
+	gpio_set_pin_function(BUZZER, PINMUX_PA27F_TCC0_WO5);
+}
+
+void PWM_1_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void PWM_1_init(void)
+{
+	PWM_1_CLOCK_init();
+	PWM_1_PORT_init();
+	pwm_init(&PWM_1, TCC0, _tcc_get_pwm());
+}
+
+void SEGMENT_LCD_0_PORT_init(void)
+{
+
+	gpio_set_pin_function(COM0, PINMUX_PB06B_SLCD_LP0);
+
+	gpio_set_pin_function(COM1, PINMUX_PB07B_SLCD_LP1);
+
+	gpio_set_pin_function(COM2, PINMUX_PB08B_SLCD_LP2);
+
+	gpio_set_pin_function(SEG0, PINMUX_PB09B_SLCD_LP3);
+
+	gpio_set_pin_function(SEG1, PINMUX_PA04B_SLCD_LP4);
+
+	gpio_set_pin_function(SEG2, PINMUX_PA05B_SLCD_LP5);
+
+	gpio_set_pin_function(SEG3, PINMUX_PA06B_SLCD_LP6);
+
+	gpio_set_pin_function(SEG4, PINMUX_PA07B_SLCD_LP7);
+
+	gpio_set_pin_function(SEG5, PINMUX_PA08B_SLCD_LP11);
+
+	gpio_set_pin_function(SEG6, PINMUX_PA09B_SLCD_LP12);
+
+	gpio_set_pin_function(SEG7, PINMUX_PA10B_SLCD_LP13);
+
+	gpio_set_pin_function(SEG8, PINMUX_PA11B_SLCD_LP14);
+
+	gpio_set_pin_function(SEG9, PINMUX_PB11B_SLCD_LP21);
+
+	gpio_set_pin_function(SEG10, PINMUX_PB12B_SLCD_LP22);
+
+	gpio_set_pin_function(SEG11, PINMUX_PB13B_SLCD_LP23);
+
+	gpio_set_pin_function(SEG12, PINMUX_PB14B_SLCD_LP24);
+
+	gpio_set_pin_function(SEG13, PINMUX_PB15B_SLCD_LP25);
+
+	gpio_set_pin_function(SEG14, PINMUX_PA12B_SLCD_LP28);
+
+	gpio_set_pin_function(SEG15, PINMUX_PA13B_SLCD_LP29);
+
+	gpio_set_pin_function(SEG16, PINMUX_PA14B_SLCD_LP30);
+
+	gpio_set_pin_function(SEG17, PINMUX_PA15B_SLCD_LP31);
+
+	gpio_set_pin_function(SEG18, PINMUX_PA16B_SLCD_LP32);
+
+	gpio_set_pin_function(SEG19, PINMUX_PA17B_SLCD_LP33);
+
+	gpio_set_pin_function(SEG20, PINMUX_PA18B_SLCD_LP34);
+
+	gpio_set_pin_function(SEG21, PINMUX_PA19B_SLCD_LP35);
+
+	gpio_set_pin_function(SEG22, PINMUX_PB16B_SLCD_LP42);
+
+	gpio_set_pin_function(SEG23, PINMUX_PB17B_SLCD_LP43);
+}
+/**
+ * \brief SLCD initialization function
+ *
+ * Enables SLCD peripheral, clocks and initializes SLCD driver
+ */
+void SEGMENT_LCD_0_init(void)
+{
+	hri_mclk_set_APBCMASK_SLCD_bit(SLCD);
+	slcd_sync_init(&SEGMENT_LCD_0, SLCD);
+	SEGMENT_LCD_0_PORT_init();
+}
+
+void system_init(void)
+{
+	init_mcu();
+
+	// GPIO on PA02
+
+	// Set pin direction to input
+	gpio_set_pin_direction(VBUS_DET, GPIO_DIRECTION_IN);
+
+	gpio_set_pin_pull_mode(VBUS_DET,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_DOWN);
+
+	gpio_set_pin_function(VBUS_DET, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB00
+
+	gpio_set_pin_level(D1,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(D1, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(D1, GPIO_PIN_FUNCTION_OFF);
+
+	// GPIO on PB03
+
+	gpio_set_pin_level(D0,
+	                   // <y> Initial level
+	                   // <id> pad_initial_level
+	                   // <false"> Low
+	                   // <true"> High
+	                   false);
+
+	// Set pin direction to output
+	gpio_set_pin_direction(D0, GPIO_DIRECTION_OUT);
+
+	gpio_set_pin_function(D0, GPIO_PIN_FUNCTION_OFF);
+
+	delay_driver_init();
+
+
+/*
+	ADC_0_init();
+
+	EXTERNAL_IRQ_0_init();
+
+	CALENDAR_0_init();
+
+	I2C_0_init();
+
+	PWM_0_init();
+
+	PWM_1_init();
+	SEGMENT_LCD_0_init();
+*/
+}
diff --git a/Smol Watch Project/My Project/driver_init.h b/Smol Watch Project/My Project/driver_init.h
new file mode 100644
index 0000000..54b8395
--- /dev/null
+++ b/Smol Watch Project/My Project/driver_init.h	
@@ -0,0 +1,81 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_INIT_INCLUDED
+#define DRIVER_INIT_INCLUDED
+
+#include "atmel_start_pins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <hal_atomic.h>
+#include <hal_delay.h>
+#include <hal_gpio.h>
+#include <hal_init.h>
+#include <hal_io.h>
+#include <hal_sleep.h>
+
+#include <hal_adc_sync.h>
+
+#include <hal_ext_irq.h>
+
+#include <hal_calendar.h>
+
+#include <hal_i2c_m_sync.h>
+
+#include <hal_delay.h>
+#include <hal_pwm.h>
+#include <hpl_tc_base.h>
+
+#include <hal_pwm.h>
+#include <hpl_tcc.h>
+#include <hal_slcd_sync.h>
+
+extern struct adc_sync_descriptor ADC_0;
+
+extern struct calendar_descriptor CALENDAR_0;
+
+extern struct i2c_m_sync_desc I2C_0;
+
+extern struct pwm_descriptor PWM_0;
+
+extern struct pwm_descriptor       PWM_1;
+extern struct slcd_sync_descriptor SEGMENT_LCD_0;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
+
+void CALENDAR_0_CLOCK_init(void);
+void CALENDAR_0_init(void);
+
+void I2C_0_CLOCK_init(void);
+void I2C_0_init(void);
+void I2C_0_PORT_init(void);
+
+void delay_driver_init(void);
+
+void PWM_0_PORT_init(void);
+void PWM_0_CLOCK_init(void);
+void PWM_0_init(void);
+
+void PWM_1_PORT_init(void);
+void PWM_1_CLOCK_init(void);
+void PWM_1_init(void);
+
+/**
+ * \brief Perform system initialization, initialize pins and clocks for
+ * peripherals
+ */
+void system_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_INIT_INCLUDED
diff --git a/Smol Watch Project/My Project/examples/driver_examples.c b/Smol Watch Project/My Project/examples/driver_examples.c
new file mode 100644
index 0000000..1932700
--- /dev/null
+++ b/Smol Watch Project/My Project/examples/driver_examples.c	
@@ -0,0 +1,126 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+
+#include "driver_examples.h"
+#include "driver_init.h"
+#include "utils.h"
+
+/**
+ * Example of using ADC_0 to generate waveform.
+ */
+void ADC_0_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_0, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
+}
+
+static void button_on_PB05_pressed(void)
+{
+}
+
+static void button_on_PA22_pressed(void)
+{
+}
+
+static void button_on_PA23_pressed(void)
+{
+}
+
+/**
+ * Example of using EXTERNAL_IRQ_0
+ */
+void EXTERNAL_IRQ_0_example(void)
+{
+
+	ext_irq_register(PIN_PB05, button_on_PB05_pressed);
+	ext_irq_register(PIN_PA22, button_on_PA22_pressed);
+	ext_irq_register(PIN_PA23, button_on_PA23_pressed);
+}
+
+/**
+ * Example of using CALENDAR_0.
+ */
+static struct calendar_alarm alarm;
+
+static void alarm_cb(struct calendar_descriptor *const descr)
+{
+	/* alarm expired */
+}
+
+void CALENDAR_0_example(void)
+{
+	struct calendar_date date;
+	struct calendar_time time;
+
+	calendar_enable(&CALENDAR_0);
+
+	date.year  = 2000;
+	date.month = 12;
+	date.day   = 31;
+
+	time.hour = 12;
+	time.min  = 59;
+	time.sec  = 59;
+
+	calendar_set_date(&CALENDAR_0, &date);
+	calendar_set_time(&CALENDAR_0, &time);
+
+	alarm.cal_alarm.datetime.time.sec = 4;
+	alarm.cal_alarm.option            = CALENDAR_ALARM_MATCH_SEC;
+	alarm.cal_alarm.mode              = REPEAT;
+
+	calendar_set_alarm(&CALENDAR_0, &alarm, alarm_cb);
+}
+
+void I2C_0_example(void)
+{
+	struct io_descriptor *I2C_0_io;
+
+	i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_sync_enable(&I2C_0);
+	i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
+	io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
+}
+
+void delay_example(void)
+{
+	delay_ms(5000);
+}
+
+/**
+ * Example of using PWM_0.
+ */
+void PWM_0_example(void)
+{
+	pwm_set_parameters(&PWM_0, 10000, 5000);
+	pwm_enable(&PWM_0);
+}
+
+/**
+ * Example of using PWM_1.
+ */
+void PWM_1_example(void)
+{
+	pwm_set_parameters(&PWM_1, 10000, 5000);
+	pwm_enable(&PWM_1);
+}
+
+#define SLCD_EXAMPLE_SEGID SLCD_SEGID(1, 0)
+/**
+ * Example of using SEGMENT_LCD_0
+ */
+void SEGMENT_LCD_0_example(void)
+{
+	slcd_sync_enable(&SEGMENT_LCD_0);
+	slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_EXAMPLE_SEGID);
+}
diff --git a/Smol Watch Project/My Project/examples/driver_examples.h b/Smol Watch Project/My Project/examples/driver_examples.h
new file mode 100644
index 0000000..4295ca9
--- /dev/null
+++ b/Smol Watch Project/My Project/examples/driver_examples.h	
@@ -0,0 +1,34 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef DRIVER_EXAMPLES_H_INCLUDED
+#define DRIVER_EXAMPLES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ADC_0_example(void);
+
+void EXTERNAL_IRQ_0_example(void);
+
+void CALENDAR_0_example(void);
+
+void I2C_0_example(void);
+
+void delay_example(void);
+
+void PWM_0_example(void);
+
+void PWM_1_example(void);
+
+void SEGMENT_LCD_0_example(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // DRIVER_EXAMPLES_H_INCLUDED
diff --git a/Smol Watch Project/My Project/hal/documentation/adc_sync.rst b/Smol Watch Project/My Project/hal/documentation/adc_sync.rst
new file mode 100644
index 0000000..d189565
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/adc_sync.rst	
@@ -0,0 +1,74 @@
+======================
+ADC Synchronous driver
+======================
+
+An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
+A reference signal with a known voltage level is quantified into equally
+sized chunks, each representing a digital value from 0 to the highest number
+possible with the bit resolution supported by the ADC. The input voltage
+measured by the ADC is compared against these chunks and the chunk with the
+closest voltage level defines the digital value that can be used to represent
+the analog input voltage level.
+
+Usually an ADC can operate in either differential or single-ended mode.
+In differential mode two signals (V+ and V-) are compared against each other
+and the resulting digital value represents the relative voltage level between
+V+ and V-. This means that if the input voltage level on V+ is lower than on
+V- the digital value is negative, which also means that in differential
+mode one bit is lost to the sign. In single-ended mode only V+ is compared
+against the reference voltage, and the resulting digital value can only be
+positive, but the full bit-range of the ADC can be used.
+
+Usually multiple resolutions are supported by the ADC, lower resolution can
+reduce the conversion time, but lose accuracy.
+
+Some ADCs has a gain stage on the input lines which can be used to increase the
+dynamic range. The default gain value is usually x1, which means that the
+conversion range is from 0V to the reference voltage.
+Applications can change the gain stage, to increase or reduce the conversion
+range.
+
+The window mode allows the conversion result to be compared to a set of
+predefined threshold values. Applications can use callback function to monitor
+if the conversion result exceeds predefined threshold value.
+
+Usually multiple reference voltages are supported by the ADC, both internal and
+external with difference voltage levels. The reference voltage have an impact
+on the accuracy, and should be selected to cover the full range of the analog
+input signal and never less than the expected maximum input voltage.
+
+There are two conversion modes supported by ADC, single shot and free running.
+In single shot mode the ADC only make one conversion when triggered by the
+application, in free running mode it continues to make conversion from it
+is triggered until it is stopped by the application. When window monitoring,
+the ADC should be set to free running mode.
+
+Features
+--------
+* Initialization and de-initialization
+* Support multiple Conversion Mode, Single or Free run
+* Start ADC Conversion
+* Read Conversion Result
+
+Applications
+------------
+* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
+* Measurement of external sensor. E.g., Temperature, humidity sensor value.
+* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
+
+Dependencies
+------------
+* ADC hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+
diff --git a/Smol Watch Project/My Project/hal/documentation/calendar.rst b/Smol Watch Project/My Project/hal/documentation/calendar.rst
new file mode 100644
index 0000000..8a3de6e
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/calendar.rst	
@@ -0,0 +1,72 @@
+===============================
+The Calendar driver (bare-bone)
+===============================
+
+The Calendar driver provides means to set and get current date and time.
+After enabling, an instance of the driver starts counting time from the base date with
+the resolution of one second. The default base date is 00:00:00 1st of January 1970.
+Only the base year of the base date can be changed via the driver API.
+
+The current date and time is kept internally in a relative form as the difference between
+current date and time and the base date and time. This means that changing the base year changes
+current date.
+
+The base date and time defines time "zero" or the earliest possible point in time that the calender driver can describe,
+this means that current time and alarms can not be set to anything earlier than this time.
+
+The Calendar driver provides alarm functionality.
+An alarm is a software trigger which fires on particular date and time with particular periodicity.
+Upon firing the given callback function is called.
+
+An alarm can be in single-shot mode, firing only once at matching time; or in repeating mode, meaning that it will
+reschedule a new alarm automatically based on repeating mode configuration.
+In single-shot mode an alarm is removed from the alarm queue before its callback is called. It allows an application to
+reuse the memory of expired alarm in the callback.
+
+An alarm can be triggered on the following events: match on second, minute, hour, day, month or year.
+Matching on second means that the alarm is triggered when the value of seconds of the current time is equal to
+the alarm's value of seconds. This means repeating alarm with match on seconds is triggered with the period of a minute.
+Matching on minute means that the calendars minute and seconds values has to match the alarms, the rest of the date-time
+value is ignored. In repeating mode this means a new alarm every hour.
+The same logic is applied to match on hour, day, month and year.
+
+Each instance of the Calendar driver supports infinite amount of software alarms, only limited by the amount of RAM available.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+* Date and time operations
+* Software alarms
+
+Applications
+------------
+* A source of current date and time for an embedded system.
+* Periodical functionality in low-power applications since the driver is designed to use 1Hz clock.
+* Periodical function calls in case if it is more convenient to operate with absolute time.
+
+Dependencies
+------------
+* This driver expects a counter to be increased by one every second to count date and time correctly.
+* Each instance of the driver requires separate hardware timer.
+
+Concurrency
+-----------
+The Calendar driver is an interrupt driven driver.This means that the interrupt that triggers an alarm may occur during
+the process of adding or removing an alarm via the driver's API. In such case the interrupt processing is postponed
+until the alarm adding or removing is complete.
+
+The alarm queue is not protected from the access by interrupts not used by the driver. Due to this
+it is not recommended to add or remove an alarm from such interrupts: in case if a higher priority interrupt supersedes
+the driver's interrupt, adding or removing an alarm may cause unpredictable behavior of the driver.
+
+Limitations
+-----------
+* Only years divisible by 4 are deemed a leap year, this gives a correct result between the years 1901 to 2099.
+* The driver is designed to work outside of an operating system environment, the software alarm queue is therefore processed in interrupt context which may delay execution of other interrupts.
+* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay in alarm's triggering.
+* Changing the base year or setting current date or time does not shift alarms' date and time accordingly or expires alarms.
+
+Knows issues and workarounds
+----------------------------
+Not applicable
diff --git a/Smol Watch Project/My Project/hal/documentation/ext_irq.rst b/Smol Watch Project/My Project/hal/documentation/ext_irq.rst
new file mode 100644
index 0000000..7dcdc7c
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/ext_irq.rst	
@@ -0,0 +1,39 @@
+==============
+EXT IRQ driver
+==============
+
+The External Interrupt driver allows external pins to be
+configured as interrupt lines. Each interrupt line can be
+individually masked and can generate an interrupt on rising,
+falling or both edges, or on high or low levels. Some of
+external pin can also be configured to wake up the device
+from sleep modes where all clocks have been disabled.
+External pins can also generate an event.
+
+Features
+--------
+* Initialization and de-initialization
+* Enabling and disabling
+* Detect external pins interrupt
+
+Applications
+------------
+* Generate an interrupt on rising, falling or both edges,
+  or on high or low levels.
+
+Dependencies
+------------
+* GPIO hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+
diff --git a/Smol Watch Project/My Project/hal/documentation/i2c_master_sync.rst b/Smol Watch Project/My Project/hal/documentation/i2c_master_sync.rst
new file mode 100644
index 0000000..77b4f6e
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/i2c_master_sync.rst	
@@ -0,0 +1,87 @@
+=============================
+I2C Master synchronous driver
+=============================
+
+I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
+for on-board low-speed bi-directional communication between controllers and
+peripherals. The master device is responsible for initiating and controlling
+all transfers on the I2C bus. Only one master device can be active on the I2C
+bus at the time, but the master role can be transferred between devices on the
+same I2C bus. I2C uses only two bidirectional open-drain lines, usually
+designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
+resistors.
+
+The stop condition is automatically controlled by the driver if the I/O write and
+read functions are used, but can be manually controlled by using the
+i2c_m_sync_transfer function.
+
+Often a master accesses different information in the slave by accessing
+different registers in the slave. This is done by first sending a message to
+the target slave containing the register address, followed by a repeated start
+condition (no stop condition between) ending with transferring register data.
+This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
+function, but limited to 8-bit register addresses.
+
+I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
+Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
+stick within the SCL clock frequency range supported by the selected mode.
+The requested SCL clock frequency is not validated by the
+i2c_m_sync_set_baudrate function against the selected I2C mode.
+
+Features
+--------
+
+	* I2C Master support
+	* Initialization and de-initialization
+	* Enabling and disabling
+	* Run-time bus speed configuration
+	* Write and read I2C messages
+	* Slave register access functions (limited to 8-bit address)
+	* Manual or automatic stop condition generation
+	* 10- and 7- bit addressing
+	* I2C Modes supported
+	       +----------------------+-------------------+
+	       |* Standard/Fast mode  | (SCL: 1 - 400kHz) |
+	       +----------------------+-------------------+
+	       |* Fastmode+           | (SCL: 1 - 1000kHz)|
+	       +----------------------+-------------------+
+	       |* Highspeed mode      | (SCL: 1 - 3400kHz)|
+	       +----------------------+-------------------+
+
+Applications
+------------
+
+* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
+* Data communication between micro controllers
+* Controlling displays
+
+Dependencies
+------------
+
+* I2C Master capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+General
+^^^^^^^
+
+	* System Managmenet Bus (SMBus) not supported.
+	* Power Management Bus (PMBus) not supported.
+
+Clock considerations
+^^^^^^^^^^^^^^^^^^^^
+
+The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
+
diff --git a/Smol Watch Project/My Project/hal/documentation/pwm.rst b/Smol Watch Project/My Project/hal/documentation/pwm.rst
new file mode 100644
index 0000000..71785c6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/pwm.rst	
@@ -0,0 +1,53 @@
+The PWM Driver(bare-bone)
+=========================
+
+Pulse-width modulation (PWM) is used to create an analog behavior
+digitally by controlling the amount of power transferred to the
+connected peripheral. This is achieved by controlling the high period
+(duty-cycle) of a periodic signal.
+
+User can change the period or duty cycle whenever PWM is running. The
+function pwm_set_parameters is used to configure these two parameters.
+Note these are raw register values and the parameter duty_cycle means
+the period of first half during one cycle, which should be not beyond
+total period value.
+
+In addition, user can also get multi PWM channels output from different
+peripherals at the same time, which is implemented more flexible by the
+function pointers.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Run-time control of PWM duty-cycle and period
+* Notifications about errors and one PWM cycle is done
+
+Applications
+------------
+
+Motor control, ballast, LED, H-bridge, power converters, and
+other types of power control applications.
+
+Dependencies
+------------
+
+The peripheral which can perform waveform generation like frequency
+generation and pulse-width modulation, such as Timer/Counter.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+The current driver doesn't support the features like recoverable,
+non-recoverable faults, dithering, dead-time insertion.
+
+Known issues and workarounds
+----------------------------
+
+N/A
diff --git a/Smol Watch Project/My Project/hal/documentation/slcd_sync.rst b/Smol Watch Project/My Project/hal/documentation/slcd_sync.rst
new file mode 100644
index 0000000..e18aa9d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/documentation/slcd_sync.rst	
@@ -0,0 +1,82 @@
+
+SLCD Synchronous driver
+=======================
+
+An LCD display is made of several segments (pixels or complete symbols) which
+can be block light or let light through. In each segment is one electrode
+connected to the common terminal (COM pin) and one is connected to the segment
+terminal (SEG pin). When a voltage above a certain threshold level is applied
+across the liquid crystal, it will change orientation and either let light
+through or block it.
+
+The driver supports segment on/off/blink, animation and character display.
+
+Each segment has a unique int32 segment id which is used by the driver. The id is
+combined by common number(COM) and segment number(SEG), the COM and SEG start from 0.
+The unique segment id is calculated by this formula: (COM << 16) | SEG
+For example a 8(coms)*8(segments)SLCD, the unique segment id for segment should be
+
+    +-----+-----+---------+
+    | COM | SEG |   ID    |
+    +-----+-----+---------+
+    |  0  |  0  | 0x00000 |
+    +-----+-----+---------+
+    |  1  |  0  | 0x10000 |
+    +-----+-----+---------+
+    |  7  |  7  | 0x70007 |
+    +-----+-----+---------+
+
+Segment ID can be calculated using the pre-defined macro SLCD_SEGID(com, seg).
+
+For character display, the "segment character mapping table" and "character mapping table"
+should be setup in configuration. The driver have no API to setup/change those
+mapping setting.
+There are two pre-defined "segment character mapping table" in this driver, 7 segments
+and 14 segments. The 7 segment character mapping can display 0-9 and a-f, the 14
+segments character mapping can display 0-9, A-Z and some special ASCII, for more
+details please refer to hpl_slcd_cm_7_seg_mapping.h and hpl_slcd_cm_14_seg_mapping.h.
+Application can also adjust this mapping table in the configuration header file,
+to add more character mapping or remove some unused character.
+
+The "character mapping" is used to setup each character in SLCD display screen.
+The driver supports multiple character mapping, the max number varies on different
+MCU/MPU. For example if an LCD display screen has five "7-segments character" and
+eight "14-segments character", and the MCU support max 44 characters setting, then
+the 13 character should be setup in configuration. Application can select any
+position from those 44 characters setting to save those 13 character.
+The index of character setting will be used in the driver API. For example:
+five "7-segments character" setting to 0 to 4 and eight "14-segments character" setting
+to 10 to 17. Then the application can use index from 0 to 4 to display the
+"7-segments character" and use index from 10 to 14 to display "14-segments character".
+
+Features
+--------
+
+* Initialization and de-initialization
+* Enabling and Disabling
+* Switching segment on/off
+* Set segment blink
+* Autonomous animation
+* Character display
+
+Applications
+------------
+* SLCD display control, segment on/off/blink
+* Play battery animation, running wheel, wifi signal, etc.
+* Display Time Clock by 7 segments character mapping
+* Display ASCII character by 14 segments character mapping
+
+Dependencies
+------------
+* SLCD capable hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+
+Known issues and workarounds
+----------------------------
+N/A
diff --git a/Smol Watch Project/My Project/hal/include/hal_adc_sync.h b/Smol Watch Project/My Project/hal/include/hal_adc_sync.h
new file mode 100644
index 0000000..1b66e3d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_adc_sync.h	
@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ADC_SYNC_H_INCLUDED
+#define _HAL_ADC_SYNC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_adc_sync
+ *
+ * @{
+ */
+
+/**
+ * \brief ADC descriptor
+ *
+ * The ADC descriptor forward declaration.
+ */
+struct adc_sync_descriptor;
+
+/**
+ * \brief ADC descriptor
+ */
+struct adc_sync_descriptor {
+	/** ADC device */
+	struct _adc_sync_device device;
+};
+
+/**
+ * \brief Initialize ADC
+ *
+ * This function initializes the given ADC descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr An ADC descriptor to initialize
+ * \param[in] hw     The pointer to hardware instance
+ * \param[in] func   The pointer to a set of functions pointers
+ *
+ * \return Initialization status.
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * This function deinitializes the given ADC descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr An ADC descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
+
+/**
+ * \brief Enable ADC
+ *
+ * Use this function to set the ADC peripheral to enabled state.
+ *
+ * \param[in] descr    Pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * Use this function to set the ADC peripheral to disabled state.
+ *
+ * \param[in] descr   Pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Read data from ADC
+ *
+ * \param[in] descr    The pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ * \param[in] buf      A buffer to read data to
+ * \param[in] length   The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length);
+
+/**
+ * \brief Set ADC reference source
+ *
+ * This function sets ADC reference source.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] reference A reference source to set
+ *
+ * \return Status of the ADC reference source setting.
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
+
+/**
+ * \brief Set ADC resolution
+ *
+ * This function sets ADC resolution.
+ *
+ * \param[in] descr      The pointer to the ADC descriptor
+ * \param[in] resolution A resolution to set
+ *
+ * \return Status of the ADC resolution setting.
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * This function sets ADC positive and negative input sources.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ *
+ * \return Status of the ADC channels setting.
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set ADC conversion mode
+ *
+ * This function sets ADC conversion mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A conversion mode to set
+ *
+ * \return Status of the ADC conversion mode setting.
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set ADC differential mode
+ *
+ * This function sets ADC differential mode.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ *
+ * \return Status of the ADC differential mode setting.
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode);
+
+/**
+ * \brief Set ADC channel gain
+ *
+ * This function sets ADC channel gain.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ *
+ * \return Status of the ADC gain setting.
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                  const adc_gain_t gain);
+
+/**
+ * \brief Set ADC window mode
+ *
+ * This function sets ADC window mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A window mode to set
+ *
+ * \return Status of the ADC window mode setting.
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
+
+/**
+ * \brief Set ADC thresholds
+ *
+ * This function sets ADC positive and negative thresholds.
+ *
+ * \param[in] descr         The pointer to the ADC descriptor
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ *
+ * \return Status of the ADC thresholds setting.
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * This function retrieves ADC threshold state.
+ *
+ * \param[in] descr  The pointer to the ADC descriptor
+ * \param[out] state The threshold state
+ *
+ * \return The state of ADC thresholds state retrieving.
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
+                                     adc_threshold_status_t *const           state);
+
+/**
+ * \brief Check if conversion is complete
+ *
+ * This function checks if the ADC has finished the conversion.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return The status of ADC conversion completion checking.
+ * \retval 1 The conversion is complete
+ * \retval 0 The conversion is not complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t adc_sync_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <hpl_missing_features.h>
+
+#endif /* _HAL_ADC_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_atomic.h b/Smol Watch Project/My Project/hal/include/hal_atomic.h
new file mode 100644
index 0000000..82151fc
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_atomic.h	
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ATOMIC_H_INCLUDED
+#define _HAL_ATOMIC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_atomic
+ *
+ *@{
+ */
+
+/**
+ * \brief Type for the register holding global interrupt enable flag
+ */
+typedef uint32_t hal_atomic_t;
+
+/**
+ * \brief Helper macro for entering critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_enterCritical() function to enter critical
+ * sections. No semicolon is required after the macro.
+ *
+ * \section atomic_usage Usage Example
+ * \code
+ * CRITICAL_SECTION_ENTER()
+ * Critical code
+ * CRITICAL_SECTION_LEAVE()
+ * \endcode
+ */
+#define CRITICAL_SECTION_ENTER()                                                                                       \
+	{                                                                                                                  \
+		volatile hal_atomic_t __atomic;                                                                                \
+		atomic_enter_critical(&__atomic);
+
+/**
+ * \brief Helper macro for leaving critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_leaveCritical() function to leave critical
+ * sections. No semicolon is required after the macro.
+ */
+#define CRITICAL_SECTION_LEAVE()                                                                                       \
+	atomic_leave_critical(&__atomic);                                                                                  \
+	}
+
+/**
+ * \brief Disable interrupts, enter critical section
+ *
+ * Disables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[out] atomic The pointer to a variable to store the value of global
+ * interrupt enable flag
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Exit atomic section
+ *
+ * Enables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[in] atomic The pointer to a variable, which stores the latest stored
+ * value of the global interrupt enable flag
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t atomic_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_ATOMIC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_calendar.h b/Smol Watch Project/My Project/hal/include/hal_calendar.h
new file mode 100644
index 0000000..26949a5
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_calendar.h	
@@ -0,0 +1,159 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_CALENDER_H_INCLUDED
+#define _HAL_CALENDER_H_INCLUDED
+
+#include "hpl_calendar.h"
+#include <utils_list.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_calendar_async
+ *
+ *@{
+ */
+
+/** \brief Prototype of callback on alarm match
+ *  \param calendar Pointer to the HAL Calendar instance.
+ */
+typedef void (*calendar_cb_alarm_t)(struct calendar_descriptor *const calendar);
+
+/** \brief Struct for alarm time
+ */
+struct calendar_alarm {
+	struct list_element    elem;
+	struct _calendar_alarm cal_alarm;
+	calendar_cb_alarm_t    callback;
+};
+
+/** \brief Initialize the Calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param hw       Pointer to the hardware instance.
+ *  \return Operation status of init
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw);
+
+/** \brief Reset the Calendar HAL instance and hardware
+ *
+ *  Reset Calendar instance to hardware defaults.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of reset.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_deinit(struct calendar_descriptor *const calendar);
+
+/** \brief Enable the Calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of init
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar);
+
+/** \brief Disable the Calendar HAL instance and hardware
+ *
+ *  Disable Calendar instance to hardware defaults.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \return Operation status of reset.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_disable(struct calendar_descriptor *const calendar);
+
+/** \brief Configure the base year for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_base_year The desired base year.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year);
+
+/** \brief Configure the time for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_calendar_time Pointer to the time configuration.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time);
+
+/** \brief Configure the date for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param p_calendar_date Pointer to the date configuration.
+ *  \return Operation status of time set.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date);
+
+/** \brief Get the time for calendar HAL instance and hardware
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param date_time Pointer to the value that will be filled with the current time.
+ *  \return Operation status of time retrieve.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time);
+
+/** \brief Config the alarm time for calendar HAL instance and hardware
+ *
+ *  Set the alarm time to calendar instance. If the callback is NULL, remove
+ *  the alarm if the alarm is already added, otherwise, ignore the alarm.
+ *
+ *  \param calendar Pointer to the HAL Calendar instance.
+ *  \param alarm Pointer to the configuration.
+ *  \param callback Pointer to the callback function.
+ *  \return Operation status of alarm time set.
+ *  \retval 0       Completed successfully.
+ */
+int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
+                           calendar_cb_alarm_t callback);
+
+/** \brief Retrieve the current driver version
+ *  \return Current driver version.
+ */
+uint32_t calendar_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_CALENDER_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_delay.h b/Smol Watch Project/My Project/hal/include/hal_delay.h
new file mode 100644
index 0000000..9d4aa5c
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_delay.h	
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief HAL delay related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+
+#ifndef _HAL_DELAY_H_INCLUDED
+#define _HAL_DELAY_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_delay Delay Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize Delay driver
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void delay_init(void *const hw);
+
+/**
+ * \brief Perform delay in us
+ *
+ * This function performs delay for the given amount of microseconds.
+ *
+ * \param[in] us The amount delay in us
+ */
+void delay_us(const uint16_t us);
+
+/**
+ * \brief Perform delay in ms
+ *
+ * This function performs delay for the given amount of milliseconds.
+ *
+ * \param[in] ms The amount delay in ms
+ */
+void delay_ms(const uint16_t ms);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t delay_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_DELAY_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_ext_irq.h b/Smol Watch Project/My Project/hal/include/hal_ext_irq.h
new file mode 100644
index 0000000..a7c2600
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_ext_irq.h	
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief External interrupt functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_EXT_IRQ_H_INCLUDED
+#define _HAL_EXT_IRQ_H_INCLUDED
+
+#include <hpl_ext_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_ext_irq
+ *
+ * @{
+ */
+
+/**
+ * \brief External IRQ callback type
+ */
+typedef void (*ext_irq_cb_t)(void);
+
+/**
+ * \brief Initialize external IRQ component, if any
+ *
+ * \return Initialization status.
+ * \retval -1 External IRQ module is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t ext_irq_init(void);
+
+/**
+ * \brief Deinitialize external IRQ, if any
+ *
+ * \return De-initialization status.
+ * \retval -1 External IRQ module is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t ext_irq_deinit(void);
+
+/**
+ * \brief Register callback for the given external interrupt
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ * \param[in] cb Callback function
+ *
+ * \return Registration status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The callback registration is completed successfully
+ */
+int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
+
+/**
+ * \brief Enable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Enabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The enabling is completed successfully
+ */
+int32_t ext_irq_enable(const uint32_t pin);
+
+/**
+ * \brief Disable external IRQ
+ *
+ * \param[in] pin Pin to enable external IRQ on
+ *
+ * \return Disabling status.
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The disabling is completed successfully
+ */
+int32_t ext_irq_disable(const uint32_t pin);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t ext_irq_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_EXT_IRQ_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_gpio.h b/Smol Watch Project/My Project/hal/include/hal_gpio.h
new file mode 100644
index 0000000..fbfa2d4
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_gpio.h	
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+#ifndef _HAL_GPIO_INCLUDED_
+#define _HAL_GPIO_INCLUDED_
+
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Set gpio pull mode
+ *
+ * Set pin pull mode, non existing pull modes throws an fatal assert
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
+ *                      GPIO_PULL_UP   = Pull pin high with internal resistor
+ *                      GPIO_PULL_OFF  = Disable pin pull mode
+ */
+static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
+{
+	_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
+}
+
+/**
+ * \brief Set pin function
+ *
+ * Select which function a pin will be used for
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] function  The pin function is given by a 32-bit wide bitfield
+ *                      found in the header files for the device
+ *
+ */
+static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
+{
+	_gpio_set_pin_function(pin, function);
+}
+
+/**
+ * \brief Set port data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
+                                           const enum gpio_direction direction)
+{
+	_gpio_set_direction(port, mask, direction);
+}
+
+/**
+ * \brief Set gpio data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
+{
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+}
+
+/**
+ * \brief Set port level
+ *
+ * Sets output level on the pins defined by the bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply port level to the corresponding
+ *                  pin
+ * \param[in] level true  = Pin levels set to "high" state
+ *                  false = Pin levels set to "low" state
+ */
+static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	_gpio_set_level(port, mask, level);
+}
+
+/**
+ * \brief Set gpio level
+ *
+ * Sets output level on a pin
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] level true  = Pin level set to "high" state
+ *                  false = Pin level set to "low" state
+ */
+static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
+{
+	_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
+}
+
+/**
+ * \brief Toggle out level on pins
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means toggle pin level to the corresponding
+ *                  pin
+ */
+static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
+{
+	_gpio_toggle_level(port, mask);
+}
+
+/**
+ * \brief Toggle output level on pin
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline void gpio_toggle_pin_level(const uint8_t pin)
+{
+	_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
+}
+
+/**
+ * \brief Get input level on pins
+ *
+ * Read the input level on pins connected to a port
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t gpio_get_port_level(const enum gpio_port port)
+{
+	return _gpio_get_level(port);
+}
+
+/**
+ * \brief Get level on pin
+ *
+ * Reads the level on pins connected to a port
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline bool gpio_get_pin_level(const uint8_t pin)
+{
+	return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
+}
+/**
+ * \brief Get current driver version
+ */
+uint32_t gpio_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hal_i2c_m_sync.h b/Smol Watch Project/My Project/hal/include/hal_i2c_m_sync.h
new file mode 100644
index 0000000..24afd63
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_i2c_m_sync.h	
@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
+#define _HAL_I2C_M_SYNC_H_INCLUDED
+
+#include <hpl_i2c_m_sync.h>
+#include <hal_io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_i2c_master_sync
+ *
+ * @{
+ */
+
+#define I2C_M_MAX_RETRY 1
+
+/**
+ * \brief I2C descriptor structure, embed i2c_device & i2c_interface
+ */
+struct i2c_m_sync_desc {
+	struct _i2c_m_sync_device device;
+	struct io_descriptor      io;
+	uint16_t                  slave_addr;
+};
+
+/**
+ * \brief Initialize synchronous I2C interface
+ *
+ * This function initializes the given I/O descriptor to be used as a
+ * synchronous I2C interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
+
+/**
+ * \brief Deinitialize I2C interface
+ *
+ * This function deinitializes the given I/O descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Uninitialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Set the slave device address
+ *
+ * This function sets the next transfer target slave I2C device address.
+ * It takes no effect to any already started access.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] addr The slave address to access
+ * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
+ *
+ * \return Masked slave address. The mask is a maximum 10-bit address, and 10th
+ *         bit is set if a 10-bit address is used
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
+
+/**
+ * \brief Set baudrate
+ *
+ * This function sets the I2C device to the specified baudrate.
+ * It only takes effect when the hardware is disabled.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] clkrate Unused parameter. Should always be 0
+ * \param[in] baudrate The baudrate value set to master
+ *
+ * \return Whether successfully set the baudrate
+ * \retval -1 The passed parameters were invalid or the device is already enabled
+ * \retval 0 The baudrate set is completed successfully
+ */
+int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Sync version of enable hardware
+ *
+ * This function enables the I2C device, and then waits for this enabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully enable the device
+ * \retval -1 The passed parameters were invalid or the device enable failed
+ * \retval 0 The hardware enabling is completed successfully
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of disable hardware
+ *
+ * This function disables the I2C device and then waits for this disabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully disable the device
+ * \retval -1 The passed parameters were invalid or the device disable failed
+ * \retval 0 The hardware disabling is completed successfully
+ */
+int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of write command to I2C slave
+ *
+ * This function will write the value to a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer holding data to write to the I2C slave device
+ * \param[in] length The length (in bytes) to write to the I2C slave device
+ *
+ * \return Whether successfully write to the device
+ * \retval <0 The passed parameters were invalid or write fail
+ * \retval 0 Writing to register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of read register value from I2C slave
+ *
+ * This function will read a byte value from a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer to hold the read data from the I2C slave device
+ * \param[in] length The length (in bytes) to read from the I2C slave device
+ *
+ * \return Whether successfully read from the device
+ * \retval <0 The passed parameters were invalid or read fail
+ * \retval 0 Reading from register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of transfer message to/from the I2C slave
+ *
+ * This function will transfer a message between the I2C slave and the master. This function will wait for the operation
+ * to be done.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] msg  An i2c_m_msg struct
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Sync version of send stop condition on the i2c bus
+ *
+ * This function will create a stop condition on the i2c bus to release the bus
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
+
+/**
+ * \brief Return I/O descriptor for this I2C instance
+ *
+ * This function will return a I/O instance for this I2C driver instance
+ *
+ * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
+ * \param[in] io_descriptor A pointer to an I/O descriptor pointer type
+ *
+ * \return Error code
+ * \retval 0 No error detected
+ * \retval <0 Error code
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t i2c_m_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hal_init.h b/Smol Watch Project/My Project/hal/include/hal_init.h
new file mode 100644
index 0000000..d7bc6fe
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_init.h	
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_INIT_H_INCLUDED
+#define _HAL_INIT_H_INCLUDED
+
+#include <hpl_init.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_init Init Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ *
+ * This function calls the various initialization functions.
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+	_init_chip();
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t init_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_INIT_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_io.h b/Smol Watch Project/My Project/hal/include/hal_io.h
new file mode 100644
index 0000000..f50401d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_io.h	
@@ -0,0 +1,110 @@
+/**
+ * \file
+ *
+ * \brief I/O related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_IO_INCLUDED
+#define _HAL_IO_INCLUDED
+
+/**
+ * \addtogroup doc_driver_hal_helper_io I/O Driver
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief I/O descriptor
+ *
+ * The I/O descriptor forward declaration.
+ */
+struct io_descriptor;
+
+/**
+ * \brief I/O write function pointer type
+ */
+typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read function pointer type
+ */
+typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O descriptor
+ */
+struct io_descriptor {
+	io_write_t write; /*! The write function pointer. */
+	io_read_t  read;  /*! The read function pointer. */
+};
+
+/**
+ * \brief I/O write interface
+ *
+ * This function writes up to \p length of bytes to a given I/O descriptor.
+ * It returns the number of bytes actually write.
+ *
+ * \param[in] descr  An I/O descriptor to write
+ * \param[in] buf    The buffer pointer to story the write data
+ * \param[in] length The number of bytes to write
+ *
+ * \return The number of bytes written
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read interface
+ *
+ * This function reads up to \p length bytes from a given I/O descriptor, and
+ * stores it in the buffer pointed to by \p buf. It returns the number of bytes
+ * actually read.
+ *
+ * \param[in] descr  An I/O descriptor to read
+ * \param[in] buf    The buffer pointer to story the read data
+ * \param[in] length The number of bytes to read
+ *
+ * \return The number of bytes actually read. This number can be less than the
+ *         requested length. E.g., in a driver that uses ring buffer for
+ *         reception, it may depend on the availability of data in the
+ *         ring buffer.
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HAL_IO_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_pwm.h b/Smol Watch Project/My Project/hal/include/hal_pwm.h
new file mode 100644
index 0000000..d55f7e6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_pwm.h	
@@ -0,0 +1,153 @@
+/**
+ * \file
+ *
+ * \brief PWM functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HAL_PWM_H_INCLUDED
+#define HAL_PWM_H_INCLUDED
+
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_pwm_async
+ *
+ *@{
+ */
+
+/**
+ * \brief PWM descriptor
+ *
+ * The PWM descriptor forward declaration.
+ */
+struct pwm_descriptor;
+
+/**
+ * \brief PWM callback type
+ */
+typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
+
+/**
+ * \brief PWM callback types
+ */
+enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
+
+/**
+ * \brief PWM callbacks
+ */
+struct pwm_callbacks {
+	pwm_cb_t period;
+	pwm_cb_t error;
+};
+
+/** \brief PWM descriptor
+ */
+struct pwm_descriptor {
+	/** PWM device */
+	struct _pwm_device device;
+	/** PWM callback structure */
+	struct pwm_callbacks pwm_cb;
+	/** PWM HPL interface pointer */
+	struct _pwm_hpl_interface *func;
+};
+
+/** \brief Initialize the PWM HAL instance and hardware
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] hw The pointer to hardware instance
+ *  \param[in] func The pointer to a set of functions pointers
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
+
+/** \brief Deinitialize the PWM HAL instance and hardware
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_deinit(struct pwm_descriptor *const descr);
+
+/** \brief PWM output start
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_enable(struct pwm_descriptor *const descr);
+
+/** \brief PWM output stop
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_disable(struct pwm_descriptor *const descr);
+
+/** \brief Register PWM callback
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] type Callback type
+ *  \param[in] cb A callback function, passing NULL de-registers callback
+ *
+ *  \return Operation status.
+ *  \retval 0 Success
+ *  \retval -1 Error
+ */
+int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
+
+/** \brief Change PWM parameter
+ *
+ *  \param[in] descr Pointer to the HAL PWM descriptor
+ *  \param[in] period Total period of one PWM cycle
+ *  \param[in] duty_cycle Period of PWM first half during one cycle
+ *
+ *  \return Operation status.
+ */
+int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
+                           const pwm_period_t duty_cycle);
+
+/** \brief Get PWM driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t pwm_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_PWM;_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hal_slcd_sync.h b/Smol Watch Project/My Project/hal/include/hal_slcd_sync.h
new file mode 100644
index 0000000..84c4e1f
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_slcd_sync.h	
@@ -0,0 +1,168 @@
+/**
+ * \file
+ *
+ * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
+ *        declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HAL_SLCD_SYNC_H_INCLUDED
+#define HAL_SLCD_SYNC_H_INCLUDED
+
+#include <hpl_slcd_sync.h>
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_slcd_sync
+ *
+ *@{
+ */
+
+struct slcd_sync_descriptor {
+	struct _slcd_sync_device dev; /*!< SLCD HPL device descriptor */
+};
+
+/**
+ * \brief               Initialize SLCD Descriptor
+ *
+ * \param[in] descr     SLCD descriptor to be initialized
+ * \param[in] hw        The pointer to hardware instance
+ */
+int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw);
+
+/**
+ * \brief               Deinitialize SLCD Descriptor
+ *
+ * \param[in] descr      SLCD descriptor to be deinitialized
+ */
+int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr);
+
+/**
+ * \brief               Enable SLCD driver
+ *
+ * \param[in] descr     SLCD descriptor to be initialized
+ */
+int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr);
+
+/**
+ * \brief               Disable SLCD driver
+ *
+ * \param[in] descr     SLCD descriptor to be disabled
+ */
+int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr);
+
+/**
+ * \brief               Turn on a Segment
+ *
+ * \param[in] descr     SLCD descriptor to be enabled
+ * \param[in] seg       Segment index. The segment index is by the combination
+ *                      of common and segment terminal index. The
+ *                      SLCD_SEGID(com, seg) macro can generate the index.
+ */
+int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg);
+
+/**
+ * \brief               Turn off a Segment
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] seg       Segment index
+ *                      value is "(common terminals << 16 | segment terminal)"
+ */
+int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg);
+
+/**
+ * \brief               Blink a Segment
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] seg       Segment index
+ *                      value is "(common terminals << 16 | segment terminal)"
+ * \param[in] period    Blink period, unit is millisecond
+ */
+int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period);
+
+/**
+ * \brief               Displays a character
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] character Character to be displayed
+ * \param[in] index     Index of the character Mapping Group
+ */
+int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index);
+
+/**
+ * \brief               Displays character string string
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] str       String to be displayed, 0 will turn off the
+ *                      corresponding char to display
+ * \param[in] len       Length of the string array
+ * \param[in] index     Index of the character Mapping Group
+ */
+int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len,
+                               uint32_t index);
+
+/**
+ * \brief               Start animation play by a segment array
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] segs      Segment array
+ * \param[in] len       Length of the segment array
+ * \param[in] period    Period (milliseconds) of each segment to animation
+ */
+int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len,
+                                  const uint32_t period);
+
+/**
+ * \brief               Stop animation play by a segment array
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] segs      Segment array
+ * \param[in] len       Length of the segment array
+ */
+int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len);
+
+/**
+ * \brief               Set animation Frequency
+ *
+ * \param[in] descr     SLCD descriptor
+ * \param[in] period    Period (million second) of each segment to animation
+ */
+int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hal_sleep.h b/Smol Watch Project/My Project/hal/include/hal_sleep.h
new file mode 100644
index 0000000..b90ef6a
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hal_sleep.h	
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_SLEEP_H_INCLUDED
+#define _HAL_SLEEP_H_INCLUDED
+
+#include <hpl_sleep.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_sleep
+ *
+ *@{
+ */
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t sleep_get_version(void);
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_SLEEP_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_adc_async.h b/Smol Watch Project/My Project/hal/include/hpl_adc_async.h
new file mode 100644
index 0000000..1aa4162
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_adc_async.h	
@@ -0,0 +1,264 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_ASYNC_H_INCLUDED
+#define _HPL_ADC_ASYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_async_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_adc_sync.h"
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_async_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_async_callbacks {
+	void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
+	void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
+};
+
+/**
+ * \brief ADC channel interrupt callbacks
+ */
+struct _adc_async_ch_callbacks {
+	void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_async_device {
+	struct _adc_async_callbacks    adc_async_cb;
+	struct _adc_async_ch_callbacks adc_async_ch_cb;
+	struct _irq_descriptor         irq;
+	void *                         hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_deinit(struct _adc_async_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_convert(struct _adc_async_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * The result value
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set lower threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] type     The type of interrupt to disable/enable if applicable
+ * \param[in] state    Enable or disable
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_adc_dma.h b/Smol Watch Project/My Project/hal/include/hpl_adc_dma.h
new file mode 100644
index 0000000..bb3a054
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_adc_dma.h	
@@ -0,0 +1,243 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_DMA_H_INCLUDED
+#define _HPL_ADC_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_dma_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <hpl_adc_sync.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_dma_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_dma_callbacks {
+	void (*complete)(struct _adc_dma_device *device, const uint16_t data);
+	void (*error)(struct _adc_dma_device *device);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_dma_device {
+	struct _adc_dma_callbacks adc_dma_cb;
+	struct _irq_descriptor    irq;
+	void *                    hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Return address of ADC DMA source
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return ADC DMA source address
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A mode to set
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set thresholds
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_DMA_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_adc_sync.h b/Smol Watch Project/My Project/hal/include/hpl_adc_sync.h
new file mode 100644
index 0000000..3bfbc61
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_adc_sync.h	
@@ -0,0 +1,271 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_SYNC_H_INCLUDED
+#define _HPL_ADC_SYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_adc_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC reference source
+ */
+typedef uint8_t adc_reference_t;
+
+/**
+ * \brief ADC resolution
+ */
+typedef uint8_t adc_resolution_t;
+
+/**
+ * \brief ADC positive input for channel
+ */
+typedef uint8_t adc_pos_input_t;
+
+/**
+ * \brief ADC negative input for channel
+ */
+typedef uint8_t adc_neg_input_t;
+
+/**
+ * \brief ADC threshold
+ */
+typedef uint16_t adc_threshold_t;
+
+/**
+ * \brief ADC gain
+ */
+typedef uint8_t adc_gain_t;
+
+/**
+ * \brief ADC conversion mode
+ */
+enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
+
+/**
+ * \brief ADC differential mode
+ */
+enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
+
+/**
+ * \brief ADC window mode
+ */
+typedef uint8_t adc_window_mode_t;
+
+/**
+ * \brief ADC threshold status
+ */
+typedef bool adc_threshold_status_t;
+
+/**
+ * \brief ADC sync descriptor device structure
+ */
+struct _adc_sync_device {
+	void *hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device);
+
+/**
+ * \brief Enable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The result value of channel
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_calendar.h b/Smol Watch Project/My Project/hal/include/hpl_calendar.h
new file mode 100644
index 0000000..16601d3
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_calendar.h	
@@ -0,0 +1,318 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_CALENDER_H_INCLUDED
+#define _HPL_CALENDER_H_INCLUDED
+
+#include <compiler.h>
+#include <utils_list.h>
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Calendar structure
+ *
+ * The Calendar structure forward declaration.
+ */
+struct calendar_dev;
+
+/**
+ * \brief Available mask options for alarms.
+ *
+ * Available mask options for alarms.
+ */
+enum calendar_alarm_option {
+	/** Alarm disabled. */
+	CALENDAR_ALARM_MATCH_DISABLED = 0,
+	/** Alarm match on second. */
+	CALENDAR_ALARM_MATCH_SEC,
+	/** Alarm match on second and minute. */
+	CALENDAR_ALARM_MATCH_MIN,
+	/** Alarm match on second, minute, and hour. */
+	CALENDAR_ALARM_MATCH_HOUR,
+	/** Alarm match on second, minute, hour, and day. */
+	CALENDAR_ALARM_MATCH_DAY,
+	/** Alarm match on second, minute, hour, day, and month. */
+	CALENDAR_ALARM_MATCH_MONTH,
+	/** Alarm match on second, minute, hour, day, month and year. */
+	CALENDAR_ALARM_MATCH_YEAR
+};
+
+/**
+ * \brief Available mode for alarms.
+ */
+enum calendar_alarm_mode { ONESHOT = 1, REPEAT };
+/**
+ * \brief Prototype of callback on alarm match
+ */
+typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev);
+
+/**
+ * \brief Prototype of callback on tamper detect
+ */
+typedef void (*tamper_drv_cb_t)(struct calendar_dev *const dev);
+
+/**
+ * \brief Structure of Calendar instance
+ */
+struct calendar_dev {
+	/** Pointer to the hardware base */
+	void *hw;
+	/** Alarm match callback */
+	calendar_drv_cb_alarm_t callback;
+	/** Tamper callback */
+	tamper_drv_cb_t callback_tamper;
+	/** IRQ struct */
+	struct _irq_descriptor irq;
+};
+/**
+ * \brief Time struct for calendar
+ */
+struct calendar_time {
+	/*range from 0 to 59*/
+	uint8_t sec;
+	/*range from 0 to 59*/
+	uint8_t min;
+	/*range from 0 to 23*/
+	uint8_t hour;
+};
+
+/**
+ * \brief Time struct for calendar
+ */
+struct calendar_date {
+	/*range from 1 to 28/29/30/31*/
+	uint8_t day;
+	/*range from 1 to 12*/
+	uint8_t month;
+	/*absolute year>= 1970(such as 2000)*/
+	uint16_t year;
+};
+
+/** \brief Calendar driver struct
+ *
+ */
+struct calendar_descriptor {
+	struct calendar_dev    device;
+	struct list_descriptor alarms;
+	/*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/
+	uint32_t base_year;
+	uint8_t  flags;
+};
+
+/** \brief Date&Time struct for calendar
+ */
+struct calendar_date_time {
+	struct calendar_time time;
+	struct calendar_date date;
+};
+
+/** \brief struct for alarm time
+ */
+struct _calendar_alarm {
+	struct calendar_date_time  datetime;
+	uint32_t                   timestamp;
+	enum calendar_alarm_option option;
+	enum calendar_alarm_mode   mode;
+};
+
+/** \enum for tamper detection mode
+ */
+enum tamper_detection_mode { TAMPER_MODE_OFF = 0U, TAMPER_MODE_WAKE, TAMPER_MODE_CAPTURE, TAMPER_MODE_ACTL };
+
+/** \enum for tamper detection mode
+ */
+enum tamper_id { TAMPID0 = 0U, TAMPID1, TAMPID2, TAMPID3, TAMPID4 };
+/**
+ * \brief Initialize Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_init(struct calendar_dev *const dev);
+
+/**
+ * \brief Deinitialize Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_deinit(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_enable(struct calendar_dev *const dev);
+
+/**
+ * \brief Disable Calendar instance
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_disable(struct calendar_dev *const dev);
+/**
+ * \brief Set counter for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] counter The counter for set
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_set_counter(struct calendar_dev *const dev, const uint32_t counter);
+
+/**
+ * \brief Get counter for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return return current counter value
+ */
+uint32_t _calendar_get_counter(struct calendar_dev *const dev);
+
+/**
+ * \brief Set compare value for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] comp The compare value for set
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_set_comp(struct calendar_dev *const dev, const uint32_t comp);
+
+/**
+ * \brief Get compare value for calendar
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return return current compare value
+ */
+uint32_t _calendar_get_comp(struct calendar_dev *const dev);
+
+/**
+ * \brief Register callback for calendar alarm
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] callback The pointer to callback function
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback);
+
+/**
+ * \brief Set calendar IRQ
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+void _calendar_set_irq(struct calendar_dev *const dev);
+
+/**
+ * \brief Register callback for tamper detection
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] callback The pointer to callback function
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper);
+
+/**
+ * \brief Find tamper is detected on specified pin
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] enum Tamper ID number
+ *
+ * \return true on detection success and false on failure.
+ */
+bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
+
+/**
+ * \brief brief Clear the Tamper ID flag
+ *
+ * \param[in] dev The pointer to calendar device struct
+ * \param[in] enum Tamper ID number
+ *
+ * \return ERR_NONE
+ */
+int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
+
+/**
+ * \brief Enable Debounce Asynchronous Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev);
+
+/**
+ * \brief Disable Tamper Debounce Asynchronous Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev);
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ *
+ * \param[in] dev The pointer to calendar device struct
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_RTC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_core.h b/Smol Watch Project/My Project/hal/include/hpl_core.h
new file mode 100644
index 0000000..9324c43
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_core.h	
@@ -0,0 +1,56 @@
+/**
+ * \file
+ *
+ * \brief CPU core related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_H_INCLUDED
+#define _HPL_CORE_H_INCLUDED
+
+/**
+ * \addtogroup HPL Core
+ *
+ * \section hpl_core_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_core_port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_CORE_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_delay.h b/Smol Watch Project/My Project/hal/include/hpl_delay.h
new file mode 100644
index 0000000..a0f1ac8
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_delay.h	
@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief Delay related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_DELAY_H_INCLUDED
+#define _HPL_DELAY_H_INCLUDED
+
+/**
+ * \addtogroup HPL Delay
+ *
+ * \section hpl_delay_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Initialize delay functionality
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+void _delay_init(void *const hw);
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ *
+ * \param[in] us The amount of us to delay for
+ *
+ * \return The amount of cycles
+ */
+uint32_t _get_cycles_for_us(const uint16_t us);
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ *
+ * \param[in] ms The amount of ms to delay for
+ *
+ * \return The amount of cycles
+ */
+uint32_t _get_cycles_for_ms(const uint16_t ms);
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] cycles The amount of cycles to delay for
+ */
+void _delay_cycles(void *const hw, uint32_t cycles);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_DELAY_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_dma.h b/Smol Watch Project/My Project/hal/include/hpl_dma.h
new file mode 100644
index 0000000..1e08434
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_dma.h	
@@ -0,0 +1,176 @@
+/**
+ * \file
+ *
+ * \brief DMA related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_DMA_H_INCLUDED
+#define _HPL_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL DMA
+ *
+ * \section hpl_dma_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct _dma_resource;
+
+/**
+ * \brief DMA callback types
+ */
+enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
+
+/**
+ * \brief DMA interrupt callbacks
+ */
+struct _dma_callbacks {
+	void (*transfer_done)(struct _dma_resource *resource);
+	void (*error)(struct _dma_resource *resource);
+};
+
+/**
+ * \brief DMA resource structure
+ */
+struct _dma_resource {
+	struct _dma_callbacks dma_cb;
+	void *                back;
+};
+
+/**
+ * \brief Initialize DMA
+ *
+ * This function does low level DMA configuration.
+ *
+ * \return initialize status
+ */
+int32_t _dma_init(void);
+
+/**
+ * \brief Set destination address
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] dst Destination address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
+
+/**
+ * \brief Set source address
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] src Source address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
+
+/**
+ * \brief Set next descriptor address
+ *
+ * \param[in] current_channel Current DMA channel to set next descriptor address
+ * \param[in] next_channel Next DMA channel used as next descriptor
+ *
+ * \return setting status
+ */
+int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
+
+/**
+ * \brief Enable/disable source address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
+
+/**
+ * \brief Enable/disable Destination address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
+/**
+ * \brief Set the amount of data to be transfered per transaction
+ *
+ * \param[in] channel DMA channel to set data amount for
+ * \param[in] amount Data amount
+ *
+ * \return status of operation
+ */
+int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
+
+/**
+ * \brief Trigger DMA transaction on the given channel
+ *
+ * \param[in] channel DMA channel to trigger transaction on
+ *
+ * \return status of operation
+ */
+int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
+
+/**
+ * \brief Retrieves DMA resource structure
+ *
+ * \param[out] resource The resource to be retrieved
+ * \param[in] channel DMA channel to retrieve structure for
+ *
+ * \return status of operation
+ */
+int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
+
+/**
+ * \brief Enable/disable DMA interrupt
+ *
+ * \param[in] channel DMA channel to enable/disable interrupt for
+ * \param[in] type The type of interrupt to disable/enable if applicable
+ * \param[in] state Enable or disable
+ */
+void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HPL_DMA_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_ext_irq.h b/Smol Watch Project/My Project/hal/include/hpl_ext_irq.h
new file mode 100644
index 0000000..3a169b6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_ext_irq.h	
@@ -0,0 +1,95 @@
+/**
+ * \file
+ *
+ * \brief External IRQ related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_EXT_IRQ_H_INCLUDED
+#define _HPL_EXT_IRQ_H_INCLUDED
+
+/**
+ * \addtogroup HPL EXT IRQ
+ *
+ * \section hpl_ext_irq_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize external interrupt module
+ *
+ * This function does low level external interrupt configuration.
+ *
+ * \param[in] cb The pointer to callback function from external interrupt
+ *
+ * \return Initialization status.
+ * \retval -1 External irq module is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
+
+/**
+ * \brief Deinitialize external interrupt module
+ *
+ * \return Initialization status.
+ * \retval -1 External irq module is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t _ext_irq_deinit(void);
+
+/**
+ * \brief Enable / disable external irq
+ *
+ * \param[in] pin Pin to enable external irq on
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return Status of external irq enabling / disabling
+ * \retval -1 External irq module can't be enabled / disabled
+ * \retval 0 External irq module is enabled / disabled successfully
+ */
+int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_EXT_IRQ_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_gpio.h b/Smol Watch Project/My Project/hal/include/hpl_gpio.h
new file mode 100644
index 0000000..5cdd387
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_gpio.h	
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief Port related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GPIO_H_INCLUDED
+#define _HPL_GPIO_H_INCLUDED
+
+/**
+ * \addtogroup HPL Port
+ *
+ * \section hpl_port_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * \brief Macros for the pin and port group, lower 5
+ * bits stands for pin number in the group, higher 3
+ * bits stands for port group
+ */
+#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
+#define GPIO_PORT(n) ((n) >> 5)
+#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
+#define GPIO_PIN_FUNCTION_OFF 0xffffffff
+
+/**
+ * \brief PORT pull mode settings
+ */
+enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
+
+/**
+ * \brief PORT direction settins
+ */
+enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
+
+/**
+ * \brief PORT group abstraction
+ */
+
+enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Port initialization function
+ *
+ * Port initialization function should setup the port module based
+ * on a static configuration file, this function should normally
+ * not be called directly, but is a part of hal_init()
+ */
+void _gpio_init(void);
+
+/**
+ * \brief Set direction on port with mask
+ *
+ * Set data direction for each pin, or disable the pin
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_OFF  = set pin direction to input
+ *                      and disable input buffer to disable the pin
+ *                      GPIO_DIRECTION_IN   = set pin direction to input
+ *                      and enable input buffer to enable the pin
+ *                      GPIO_DIRECTION_OUT  = set pin direction to output
+ *                      and disable input buffer
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction);
+
+/**
+ * \brief Set output level on port with mask
+ *
+ * Sets output state on pin to high or low with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ * \param[in] level true  = pin level is set to 1
+ *                  false = pin level is set to 0
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
+
+/**
+ * \brief Change output level to the opposite with mask
+ *
+ * Change pin output level to the opposite with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
+
+/**
+ * \brief Get input levels on all port pins
+ *
+ * Get input level on all port pins, will read IN register if configured to
+ * input and OUT register if configured as output
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port);
+
+/**
+ * \brief Set pin pull mode
+ *
+ * Set pull mode on a single pin
+ *
+ * \notice This function will automatically change pin direction to input
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] pin       The pin in the group that pull mode should be selected
+ *                      for
+ * \param[in] pull_mode GPIO_PULL_OFF  = pull resistor on pin is disabled
+ *                      GPIO_PULL_DOWN = pull resistor on pin will pull pin
+ *                      level to ground level
+ *                      GPIO_PULL_UP   = pull resistor on pin will pull pin
+ *                      level to VCC
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode);
+
+/**
+ * \brief Set gpio function
+ *
+ * Select which function a gpio is used for
+ *
+ * \param[in] gpio     The gpio to set function for
+ * \param[in] function The gpio function is given by a 32-bit wide bitfield
+ *                     found in the header files for the device
+ *
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
+
+#include <hpl_gpio_base.h>
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_GPIO_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_i2c_m_async.h b/Smol Watch Project/My Project/hal/include/hpl_i2c_m_async.h
new file mode 100644
index 0000000..8a9491d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_i2c_m_async.h	
@@ -0,0 +1,205 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
+#define _HPL_I2C_M_ASYNC_H_INCLUDED
+
+#include "hpl_i2c_m_sync.h"
+#include "hpl_irq.h"
+#include "utils.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c master callback names
+ */
+enum _i2c_m_async_callback_type {
+	I2C_M_ASYNC_DEVICE_ERROR,
+	I2C_M_ASYNC_DEVICE_TX_COMPLETE,
+	I2C_M_ASYNC_DEVICE_RX_COMPLETE
+};
+
+struct _i2c_m_async_device;
+
+typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
+typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
+
+/**
+ * \brief i2c callback pointers structure
+ */
+struct _i2c_m_async_callback {
+	_i2c_error_cb_t    error;
+	_i2c_complete_cb_t tx_complete;
+	_i2c_complete_cb_t rx_complete;
+};
+
+/**
+ * \brief i2c device structure
+ */
+struct _i2c_m_async_device {
+	struct _i2c_m_service        service;
+	void *                       hw;
+	struct _i2c_m_async_callback cb;
+	struct _irq_descriptor       irq;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize I2C in interrupt mode
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] i2c_dev The pointer to i2c interrupt device structure
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
+
+/**
+ * \brief Deinitialize I2C in interrupt mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Transfer data by I2C
+ *
+ * This function does low level I2C data transfer.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] msg The pointer to i2c msg structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Set baud rate of I2C
+ *
+ * This function does low level I2C set baud rate.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] clkrate The clock rate(KHz) input to i2c module
+ * \param[in] baudrate The demand baud rate(KHz) of i2c module
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Register callback to I2C
+ *
+ * This function does low level I2C callback register.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] cb_type The callback type request
+ * \param[in] func The callback function pointer
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
+                                       FUNC_PTR func);
+
+/**
+ * \brief Generate stop condition on the I2C bus
+ *
+ * This function will generate a stop condition on the I2C bus
+ *
+ * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
+ *
+ * \return Operation status
+ * \retval 0 Operation executed successfully
+ * \retval <0 Operation failed
+ */
+int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Returns the number of bytes left or not used in the I2C message buffer
+ *
+ * This function will return the number of bytes left (not written to the bus) or still free
+ * (not received from the bus) in the message buffer, depending on direction of transmission.
+ *
+ * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
+ *
+ * \return Number of bytes or error code
+ * \retval >0 Positive number indicating bytes left
+ * \retval 0  Buffer is full/empty depending on direction
+ * \retval <0 Error code
+ */
+int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
+
+/**
+ * \brief Enable/disable I2C master interrupt
+ *
+ * param[in] device The pointer to I2C master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
+                                const bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hpl_i2c_m_sync.h b/Smol Watch Project/My Project/hal/include/hpl_i2c_m_sync.h
new file mode 100644
index 0000000..ce173ae
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_i2c_m_sync.h	
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief I2C Master Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
+#define _HPL_I2C_M_SYNC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c flags
+ */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_BUSY 0x0100
+#define I2C_M_TEN 0x0400   /* this is a ten bit chip address */
+#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
+#define I2C_M_FAIL 0x1000
+#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+
+/**
+ * \brief i2c Return codes
+ */
+#define I2C_OK 0                     /* Operation successful */
+#define I2C_ACK -1                   /* Received ACK from device on I2C bus */
+#define I2C_NACK -2                  /* Received NACK from device on I2C bus */
+#define I2C_ERR_ARBLOST -3           /* Arbitration lost */
+#define I2C_ERR_BAD_ADDRESS -4       /* Bad address */
+#define I2C_ERR_BUS -5               /* Bus error */
+#define I2C_ERR_BUSY -6              /* Device busy */
+#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
+
+/**
+ * \brief i2c I2C Modes
+ */
+#define I2C_STANDARD_MODE 0x00
+#define I2C_FASTMODE 0x01
+#define I2C_HIGHSPEED_MODE 0x02
+
+/**
+ * \brief i2c master message structure
+ */
+struct _i2c_m_msg {
+	uint16_t          addr;
+	volatile uint16_t flags;
+	int32_t           len;
+	uint8_t *         buffer;
+};
+
+/**
+ * \brief i2c master service
+ */
+struct _i2c_m_service {
+	struct _i2c_m_msg msg;
+	uint16_t          mode;
+	uint16_t          trise;
+};
+
+/**
+ * \brief i2c sync master device structure
+ */
+struct _i2c_m_sync_device {
+	struct _i2c_m_service service;
+	void *                hw;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize I2C
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
+
+/**
+ * \brief Deinitialize I2C
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
+
+/**
+ * \brief Transfer data by I2C
+ *
+ * This function does low level I2C data transfer.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] msg The pointer to i2c msg structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Set baud rate of I2C
+ *
+ * This function does low level I2C set baud rate.
+ *
+ * \param[in] i2c_dev The pointer to i2c device structure
+ * \param[in] clkrate The clock rate(KHz) input to i2c module
+ * \param[in] baudrate The demand baud rate(KHz) of i2c module
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Send send condition on the I2C bus
+ *
+ * This function will generate a stop condition on the I2C bus
+ *
+ * \param[in] i2c_dev The pointer to i2c device struct
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hpl_i2c_s_async.h b/Smol Watch Project/My Project/hal/include/hpl_i2c_s_async.h
new file mode 100644
index 0000000..92a5765
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_i2c_s_async.h	
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
+#define _HPL_I2C_S_ASYNC_H_INCLUDED
+
+#include "hpl_i2c_s_sync.h"
+#include "hpl_irq.h"
+#include "utils.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief i2c callback types
+ */
+enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
+
+/**
+ * \brief Forward declaration of I2C Slave device
+ */
+struct _i2c_s_async_device;
+
+/**
+ * \brief i2c slave callback function type
+ */
+typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
+
+/**
+ * \brief i2c slave callback pointers structure
+ */
+struct _i2c_s_async_callback {
+	void (*error)(struct _i2c_s_async_device *const device);
+	void (*tx)(struct _i2c_s_async_device *const device);
+	void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
+};
+
+/**
+ * \brief i2c slave device structure
+ */
+struct _i2c_s_async_device {
+	void *                       hw;
+	struct _i2c_s_async_callback cb;
+	struct _irq_descriptor       irq;
+};
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize asynchronous I2C slave
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] device The pointer to i2c interrupt device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize asynchronous I2C in interrupt mode
+ *
+ * \param[in] device The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Cheking status
+ * \retval 1 10-bit addressing mode is on
+ * \retval 0 10-bit addressing mode is off
+ */
+int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Set I2C slave address
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] address Address to set
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
+
+/**
+ * \brief Write a byte to the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] data Data to write
+ */
+void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
+
+/**
+ * \brief Retrieve I2C slave status
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ *\return I2C slave status
+ */
+i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Abort data transmission
+ *
+ * \param[in] device The pointer to i2c device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
+
+/**
+ * \brief Enable/disable I2C slave interrupt
+ *
+ * param[in] device The pointer to I2C slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] disable Enable or disable
+ */
+int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
+                                   const bool disable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_i2c_s_sync.h b/Smol Watch Project/My Project/hal/include/hpl_i2c_s_sync.h
new file mode 100644
index 0000000..93b5934
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_i2c_s_sync.h	
@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
+#define _HPL_I2C_S_SYNC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief I2C Slave status type
+ */
+typedef uint32_t i2c_s_status_t;
+
+/**
+ * \brief i2c slave device structure
+ */
+struct _i2c_s_sync_device {
+	void *hw;
+};
+
+#include <compiler.h>
+
+/**
+ * \name HPL functions
+ */
+
+/**
+ * \brief Initialize synchronous I2C slave
+ *
+ * This function does low level I2C configuration.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize synchronous I2C slave
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Enable I2C module
+ *
+ * This function does low level I2C enable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Disable I2C module
+ *
+ * This function does low level I2C disable.
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Cheking status
+ * \retval 1 10-bit addressing mode is on
+ * \retval 0 10-bit addressing mode is off
+ */
+int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Set I2C slave address
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] address Address to set
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
+
+/**
+ * \brief Write a byte to the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ * \param[in] data Data to write
+ */
+void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
+
+/**
+ * \brief Retrieve I2C slave status
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ *\return I2C slave status
+ */
+i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Clear the Data Ready interrupt flag
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Return 0 for success and negative value for error
+ */
+int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Read a byte from the given I2C instance
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Data received via I2C interface.
+ */
+uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if I2C is ready to send next byte
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Status of the ready check.
+ * \retval true if the I2C is ready to send next byte
+ * \retval false if the I2C is not ready to send next byte
+ */
+bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
+
+/**
+ * \brief Check if there is data received by I2C
+ *
+ * \param[in] device The pointer to i2c slave device structure
+ *
+ * \return Status of the data received check.
+ * \retval true if the I2C has received a byte
+ * \retval false if the I2C has not received a byte
+ */
+bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_init.h b/Smol Watch Project/My Project/hal/include/hpl_init.h
new file mode 100644
index 0000000..71bf49c
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_init.h	
@@ -0,0 +1,124 @@
+/**
+ * \file
+ *
+ * \brief Init related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_INIT_H_INCLUDED
+#define _HPL_INIT_H_INCLUDED
+
+/**
+ * \addtogroup HPL Init
+ *
+ * \section hpl_init_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initializes clock sources
+ */
+void _sysctrl_init_sources(void);
+
+/**
+ * \brief Initializes Power Manager
+ */
+void _pm_init(void);
+
+/**
+ * \brief Initialize generators
+ */
+void _gclk_init_generators(void);
+
+/**
+ * \brief Initialize 32 kHz clock sources
+ */
+void _osc32kctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources
+ */
+void _oscctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _sysctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _oscctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _lpmcu_misc_regs_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _pmc_init(void);
+
+/**
+ * \brief Set performance level
+ *
+ * \param[in] level The performance level to set
+ */
+void _set_performance_level(const uint8_t level);
+
+/**
+ * \brief Initialize the chip
+ */
+void _init_chip(void);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_INIT_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_irq.h b/Smol Watch Project/My Project/hal/include/hpl_irq.h
new file mode 100644
index 0000000..2894944
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_irq.h	
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief IRQ related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_IRQ_H_INCLUDED
+#define _HPL_IRQ_H_INCLUDED
+
+/**
+ * \addtogroup HPL IRQ
+ *
+ * \section hpl_irq_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief IRQ descriptor
+ */
+struct _irq_descriptor {
+	void (*handler)(void *parameter);
+	void *parameter;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve current IRQ number
+ *
+ * \return The current IRQ number
+ */
+uint8_t _irq_get_current(void);
+
+/**
+ * \brief Disable the given IRQ
+ *
+ * \param[in] n The number of IRQ to disable
+ */
+void _irq_disable(uint8_t n);
+
+/**
+ * \brief Set the given IRQ
+ *
+ * \param[in] n The number of IRQ to set
+ */
+void _irq_set(uint8_t n);
+
+/**
+ * \brief Clear the given IRQ
+ *
+ * \param[in] n The number of IRQ to clear
+ */
+void _irq_clear(uint8_t n);
+
+/**
+ * \brief Enable the given IRQ
+ *
+ * \param[in] n The number of IRQ to enable
+ */
+void _irq_enable(uint8_t n);
+
+/**
+ * \brief Register IRQ handler
+ *
+ * \param[in] number The number registered IRQ
+ * \param[in] irq The pointer to irq handler to register
+ *
+ * \return The status of IRQ handler registering
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The registering is completed successfully
+ */
+void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_IRQ_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_missing_features.h b/Smol Watch Project/My Project/hal/include/hpl_missing_features.h
new file mode 100644
index 0000000..7071db2
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_missing_features.h	
@@ -0,0 +1,37 @@
+/**
+ * \file
+ *
+ * \brief Family-dependent missing features expected by HAL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_MISSING_FEATURES
+#define _HPL_MISSING_FEATURES
+
+#endif /* _HPL_MISSING_FEATURES */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_pwm.h b/Smol Watch Project/My Project/hal/include/hpl_pwm.h
new file mode 100644
index 0000000..ea056de
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_pwm.h	
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief PWM related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _HPL_PWM_H_INCLUDED
+#define _HPL_PWM_H_INCLUDED
+
+/**
+ * \addtogroup HPL PWM
+ *
+ * \section hpl_pwm_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief PWM callback types
+ */
+enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
+
+/**
+ * \brief PWM pulse-width period
+ */
+typedef uint32_t pwm_period_t;
+
+/**
+ * \brief PWM device structure
+ *
+ * The PWM device structure forward declaration.
+ */
+struct _pwm_device;
+
+/**
+ * \brief PWM interrupt callbacks
+ */
+struct _pwm_callback {
+	void (*pwm_period_cb)(struct _pwm_device *device);
+	void (*pwm_error_cb)(struct _pwm_device *device);
+};
+
+/**
+ * \brief PWM descriptor device structure
+ */
+struct _pwm_device {
+	struct _pwm_callback   callback;
+	struct _irq_descriptor irq;
+	void *                 hw;
+};
+
+/**
+ * \brief PWM functions, pointers to low-level functions
+ */
+struct _pwm_hpl_interface {
+	int32_t (*init)(struct _pwm_device *const device, void *const hw);
+	void (*deinit)(struct _pwm_device *const device);
+	void (*start_pwm)(struct _pwm_device *const device);
+	void (*stop_pwm)(struct _pwm_device *const device);
+	void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
+	bool (*is_pwm_enabled)(const struct _pwm_device *const device);
+	pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
+	uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
+	void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
+};
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_PWM_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_reset.h b/Smol Watch Project/My Project/hal/include/hpl_reset.h
new file mode 100644
index 0000000..75738b6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_reset.h	
@@ -0,0 +1,92 @@
+/**
+ * \file
+ *
+ * \brief Reset related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_RESET_H_INCLUDED
+#define _HPL_RESET_H_INCLUDED
+
+/**
+ * \addtogroup HPL Reset
+ *
+ * \section hpl_reset_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Reset reason enumeration
+ *
+ * The list of possible reset reasons.
+ */
+enum reset_reason {
+	RESET_REASON_POR    = 1,
+	RESET_REASON_BOD12  = 2,
+	RESET_REASON_BOD33  = 4,
+	RESET_REASON_EXT    = 16,
+	RESET_REASON_WDT    = 32,
+	RESET_REASON_SYST   = 64,
+	RESET_REASON_BACKUP = 128
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve the reset reason
+ *
+ * Retrieves the reset reason of the last MCU reset.
+ *
+ *\return An enum value indicating the reason of the last reset.
+ */
+enum reset_reason _get_reset_reason(void);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_RESET_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_slcd.h b/Smol Watch Project/My Project/hal/include/hpl_slcd.h
new file mode 100644
index 0000000..f3ccbbc
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_slcd.h	
@@ -0,0 +1,49 @@
+/**
+ * \file
+ *
+ * \brief SLCD common declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HPL_SLCD_H_INCLUDED
+#define HPL_SLCD_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SLCD_SEGID(com, seg) (((com) << 16) | (seg))
+#define SLCD_COMNUM(segid) (((segid) >> 16) & 0xFF)
+#define SLCD_SEGNUM(segid) ((segid)&0xFF)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HPL_SLCD_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_slcd_sync.h b/Smol Watch Project/My Project/hal/include/hpl_slcd_sync.h
new file mode 100644
index 0000000..2f5a05d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_slcd_sync.h	
@@ -0,0 +1,154 @@
+/**
+ * \file
+ *
+ * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
+ *        declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HPL_SLCD_SYNC_H_INCLUDED
+#define HPL_SLCD_SYNC_H_INCLUDED
+
+#include <hpl_slcd.h>
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief SLCD sync device structure
+ *
+ * The SLCD device structure forward declaration.
+ */
+struct _slcd_sync_device;
+
+struct _slcd_sync_device {
+	void *hw; /*!< Hardware module instance handler */
+};
+
+/**
+ * \brief              Initialize SLCD Device Descriptor
+ *
+ * \param[in] desc     SLCD descriptor to be initialized
+ * \param[in] hw       The pointer to hardware instance
+ */
+int32_t _slcd_sync_init(struct _slcd_sync_device *const dev, void *const hw);
+
+/**
+ * \brief              Deinitialize SLCD Device Descriptor
+ *
+ * \param[in] desc     SLCD device descriptor to be deinitialized
+ */
+int32_t _slcd_sync_deinit(struct _slcd_sync_device *const dev);
+
+/**
+ * \brief              Enable SLCD driver
+ *
+ * \param[in] dev      SLCD device descriptor to be enabled
+ */
+int32_t _slcd_sync_enable(struct _slcd_sync_device *const dev);
+
+/**
+ * \brief              Disable SLCD driver
+ *
+ * \param[in] dev      SLCD Device descriptor to be disabled
+ */
+int32_t _slcd_sync_disable(struct _slcd_sync_device *const dev);
+
+/**
+ * \brief               Turn on a Segment
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] seg       Segment id
+ *                      value is (common terminals << 16 | segment terminal)
+ */
+int32_t _slcd_sync_seg_on(struct _slcd_sync_device *const dev, uint32_t seg);
+
+/**
+ * \brief               Turn off a Segment
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] seg       Segment id
+ *                      value is (common terminals << 16 | segment terminal)
+ */
+int32_t _slcd_sync_seg_off(struct _slcd_sync_device *const dev, uint32_t seg);
+
+/**
+ * \brief               Blink a Segment
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] seg       Segment index
+ *                      value is (common terminals << 16 | segment terminal)
+ * \param[in] period  Blink period, unit is million second
+ */
+int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *const dev, uint32_t seg, const uint32_t period);
+
+/**
+ * \brief              Displays a character
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] character Character to be displayed
+ * \param[in] index     Index of Character Mapping Group
+ */
+int32_t _slcd_sync_write_char(struct _slcd_sync_device *const dev, const uint8_t character, uint32_t index);
+
+/**
+ * \brief               Start animation play by a segment array
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] segs      Segment array
+ * \param[in] len       Length of the segment array
+ * \param[in] period    Period(milliseconds) of the each segment to animation
+ */
+int32_t _slcd_sync_start_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len,
+                                   const uint32_t period);
+
+/**
+ * \brief               Stop animation play by a segment array
+ *
+ * \param[in] dev       SLCD device descriptor
+ * \param[in] segs      Segment array
+ * \param[in] len       Length of the segment array
+ */
+int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len);
+
+/**
+ * \brief               Set animation Frequency
+ *
+ * \param[in] dev       SLCD Device descriptor
+ * \param[in] period    Period(million second) of the each segment to animation
+ */
+int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *const dev, const uint32_t period);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/include/hpl_sleep.h b/Smol Watch Project/My Project/hal/include/hpl_sleep.h
new file mode 100644
index 0000000..6731ec3
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_sleep.h	
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SLEEP_H_INCLUDED
+#define _HPL_SLEEP_H_INCLUDED
+
+/**
+ * \addtogroup HPL Sleep
+ *
+ * \section hpl_sleep_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Set the sleep mode for the device
+ *
+ * This function sets the sleep mode for the device.
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes see datasheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return the status of a sleep request
+ * \retval -1 The requested sleep mode was invalid
+ * \retval  0 The operation completed successfully, sleep mode is set
+ */
+int32_t _set_sleep_mode(const uint8_t mode);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_SLEEP_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi.h b/Smol Watch Project/My Project/hal/include/hpl_spi.h
new file mode 100644
index 0000000..a5652e5
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi.h	
@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_H_INCLUDED
+#define _HPL_SPI_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief SPI Dummy char is used when reading data from the SPI slave
+ */
+#define SPI_DUMMY_CHAR 0x1ff
+
+/**
+ *  \brief SPI message to let driver to process
+ */
+//@{
+struct spi_msg {
+	/** Pointer to the output data buffer */
+	uint8_t *txbuf;
+	/** Pointer to the input data buffer */
+	uint8_t *rxbuf;
+	/** Size of the message data in SPI characters */
+	uint32_t size;
+};
+//@}
+
+/**
+ *  \brief SPI transfer modes
+ *  SPI transfer mode controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ */
+enum spi_transfer_mode {
+	/** Leading edge is rising edge, data sample on leading edge. */
+	SPI_MODE_0,
+	/** Leading edge is rising edge, data sample on trailing edge. */
+	SPI_MODE_1,
+	/** Leading edge is falling edge, data sample on leading edge. */
+	SPI_MODE_2,
+	/** Leading edge is falling edge, data sample on trailing edge. */
+	SPI_MODE_3
+};
+
+/**
+ *  \brief SPI character sizes
+ *  The character size influence the way the data is sent/received.
+ *  For char size <= 8 data is stored byte by byte.
+ *  For char size between 9 ~ 16 data is stored in 2-byte length.
+ *  Note that the default and recommended char size is 8 bit since it's
+ *  supported by all system.
+ */
+enum spi_char_size {
+	/** Character size is 8 bit. */
+	SPI_CHAR_SIZE_8 = 0,
+	/** Character size is 9 bit. */
+	SPI_CHAR_SIZE_9 = 1,
+	/** Character size is 10 bit. */
+	SPI_CHAR_SIZE_10 = 2,
+	/** Character size is 11 bit. */
+	SPI_CHAR_SIZE_11 = 3,
+	/** Character size is 12 bit. */
+	SPI_CHAR_SIZE_12 = 4,
+	/** Character size is 13 bit. */
+	SPI_CHAR_SIZE_13 = 5,
+	/** Character size is 14 bit. */
+	SPI_CHAR_SIZE_14 = 6,
+	/** Character size is 15 bit. */
+	SPI_CHAR_SIZE_15 = 7,
+	/** Character size is 16 bit. */
+	SPI_CHAR_SIZE_16 = 8
+};
+
+/**
+ *  \brief SPI data order
+ */
+enum spi_data_order {
+	/** MSB goes first. */
+	SPI_DATA_ORDER_MSB_1ST = 0,
+	/** LSB goes first. */
+	SPI_DATA_ORDER_LSB_1ST = 1
+};
+
+/** \brief Transfer descriptor for SPI
+ *  Transfer descriptor holds TX and RX buffers
+ */
+struct spi_xfer {
+	/** Pointer to data buffer to TX */
+	uint8_t *txbuf;
+	/** Pointer to data buffer to RX */
+	uint8_t *rxbuf;
+	/** Size of data characters to TX & RX */
+	uint32_t size;
+};
+
+/** SPI generic driver. */
+struct spi_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Reference start of sync/async variables */
+	uint32_t sync_async_misc[1];
+};
+
+/**
+ *  \brief Calculate the baudrate value for hardware to use to set baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] clk Clock frequency (Hz) for baudrate generation.
+ *  \param[in] baud Target baudrate (bps).
+ *  \return Error or baudrate value.
+ *  \retval >0 Baudrate value.
+ *  \retval ERR_INVALID_ARG Calculation fail.
+ */
+int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_async.h b/Smol Watch Project/My Project/hal/include/hpl_spi_async.h
new file mode 100644
index 0000000..8e5a848
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_async.h	
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief Common SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_ASYNC_H_INCLUDED
+#define _HPL_SPI_ASYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_irq.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  \brief Callbacks the SPI driver must offer in async mode
+ */
+//@{
+/** The callback types */
+enum _spi_async_dev_cb_type {
+	/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
+	SPI_DEV_CB_TX,
+	/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
+	SPI_DEV_CB_RX,
+	/** Callback type for \ref _spi_async_dev_cb_complete_t. */
+	SPI_DEV_CB_COMPLETE,
+	/** Callback type for error */
+	SPI_DEV_CB_ERROR,
+	/** Number of callbacks. */
+	SPI_DEV_CB_N
+};
+
+struct _spi_async_dev;
+
+/** \brief The prototype for callback on SPI transfer error.
+ *  If status code is zero, it indicates the normal completion, that is,
+ *  SS deactivation.
+ *  If status code belows zero, it indicates complete.
+ */
+typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
+
+/** \brief The prototype for callback on SPI transmit/receive event
+ *  For TX, the callback is invoked when transmit is done or ready to start
+ *  transmit.
+ *  For RX, the callback is invoked when receive is done or ready to read data,
+ *  see \ref _spi_async_dev_read_one_t on data reading.
+ *  Without DMA enabled, the callback is invoked on each character event.
+ *  With DMA enabled, the callback is invoked on DMA buffer done.
+ */
+typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
+
+/**
+ *  \brief The callbacks offered by SPI driver
+ */
+struct _spi_async_dev_callbacks {
+	/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
+	_spi_async_dev_cb_xfer_t tx;
+	/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
+	_spi_async_dev_cb_xfer_t rx;
+	/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
+	_spi_async_dev_cb_xfer_t complete;
+	/** Error callback, see \ref */
+	_spi_async_dev_cb_error_t err;
+};
+//@}
+
+/**
+ *  \brief SPI async driver
+ */
+//@{
+
+/** SPI driver to support async HAL */
+struct _spi_async_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Data size, number of bytes for each character */
+	uint8_t char_size;
+	/** Dummy byte used in master mode when reading the slave */
+	uint16_t dummy_byte;
+
+	/** \brief Pointer to callback functions, ignored for polling mode
+	 *  Pointer to the callback functions so that initialize the driver to
+	 *  handle interrupts.
+	 */
+	struct _spi_async_dev_callbacks callbacks;
+	/** IRQ instance for SPI device. */
+	struct _irq_descriptor irq;
+};
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_m_async.h b/Smol Watch Project/My Project/hal/include/hpl_spi_m_async.h
new file mode 100644
index 0000000..8d3555e
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_m_async.h	
@@ -0,0 +1,243 @@
+/**
+ * \file
+ *
+ * \brief SPI Slave Async related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
+#define _HPL_SPI_M_ASYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_async.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI async device driver. */
+#define _spi_m_async_dev _spi_async_dev
+
+#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
+
+/** Uses common SPI async device driver complete callback type. */
+#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
+
+/** Uses common SPI async device driver transfer callback type. */
+#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on after data transmission complate
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func);
+
+/**
+ * \brief Enable/disable SPI master interrupt
+ *
+ * param[in] device The pointer to SPI master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_m_dma.h b/Smol Watch Project/My Project/hal/include/hpl_spi_m_dma.h
new file mode 100644
index 0000000..2b48300
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_m_dma.h	
@@ -0,0 +1,182 @@
+/**
+ * \file
+ *
+ * \brief SPI Master DMA related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_DMA_H_INCLUDED
+#define _HPL_SPI_M_DMA_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_dma.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI dma device driver. */
+#define _spi_m_dma_dev _spi_dma_dev
+
+#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 ERR_NONE is operation done successfully.
+ */
+int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
+
+/** \brief Do SPI data transfer (TX & RX) with DMA
+ *  Log the TX & RX buffers and transfer them in background. It never blocks.
+ *
+ *  \param[in] dev Pointer to the SPI device instance.
+ *  \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
+ *  \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
+ *  \param[in] length spi transfer data length.
+ *
+ *  \return Operation status.
+ *  \retval ERR_NONE Success.
+ *  \retval ERR_BUSY Busy.
+ */
+int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
+                            const uint16_t length);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_m_sync.h b/Smol Watch Project/My Project/hal/include/hpl_spi_m_sync.h
new file mode 100644
index 0000000..38df15b
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_m_sync.h	
@@ -0,0 +1,166 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
+#define _HPL_SPI_M_SYNC_H_INCLUDED
+
+#include <hpl_spi.h>
+#include <hpl_spi_sync.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI sync device driver. */
+#define _spi_m_sync_dev _spi_sync_dev
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
+
+/**
+ *  \brief Deinitialize SPI
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Enable SPI for access without interrupts
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
+ *                  how it's generated.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
+
+/**
+ *  \brief Set SPI char size
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
+
+/**
+ *  \brief Transfer the whole message without interrupt
+ *  Transfer the message, it will keep waiting until the message finish or
+ *  error.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] msg Pointer to the message instance to process.
+ *  \return Error or number of characters transferred.
+ *  \retval ERR_BUSY SPI hardware is not ready to start transfer (not
+ *                   enabled, busy applying settings, ...).
+ *  \retval SPI_ERR_OVERFLOW Overflow error.
+ *  \retval >=0 Number of characters transferred.
+ */
+int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_s_async.h b/Smol Watch Project/My Project/hal/include/hpl_spi_s_async.h
new file mode 100644
index 0000000..5647243
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_s_async.h	
@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SPI Slave Async related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
+#define _HPL_SPI_S_ASYNC_H_INCLUDED
+
+#include <hpl_spi_async.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI async device driver. */
+#define _spi_s_async_dev _spi_async_dev
+
+#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
+
+/** Uses common SPI async device driver complete callback type. */
+#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
+
+/** Uses common SPI async device driver transfer callback type. */
+#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Enable SPI for access with interrupts
+ *  Enable the SPI and enable callback generation of receive and error
+ *  interrupts.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI and interrupts. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on Slave Select (SS) rising
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retvat 0 OK Status
+ */
+int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
+
+/**
+ *  \brief Register the SPI device callback
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] cb_type The callback type.
+ *  \param[in] func The callback function to register. NULL to disable callback.
+ *  \return Always 0.
+ */
+int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func);
+
+/**
+ * \brief Enable/disable SPI slave interrupt
+ *
+ * param[in] device The pointer to SPI slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_s_sync.h b/Smol Watch Project/My Project/hal/include/hpl_spi_s_sync.h
new file mode 100644
index 0000000..ff4c811
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_s_sync.h	
@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
+#define _HPL_SPI_S_SYNC_H_INCLUDED
+
+#include <hpl_spi_sync.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Uses common SPI sync device driver. */
+#define _spi_s_sync_dev _spi_sync_dev
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ *  \brief Initialize SPI for access without interrupts
+ *  It will load default hardware configuration and software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] hw Pointer to the hardware base.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG Input parameter problem.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval ERR_DENIED SPI has been enabled.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
+
+/**
+ *  \brief Initialize SPI for access with interrupts
+ *  Disable, reset the hardware and the software struct.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Enable SPI for access without interrupts
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI hardware not ready (resetting).
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Disable SPI for access without interrupts
+ *  Disable SPI. Deactivate all CS pins if works as master.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \return Operation status.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Set SPI transfer mode
+ *  Set SPI transfer mode (\ref spi_transfer_mode),
+ *  which controls clock polarity and clock phase.
+ *  Mode 0: leading edge is rising edge, data sample on leading edge.
+ *  Mode 1: leading edge is rising edge, data sample on trailing edge.
+ *  Mode 2: leading edge is falling edge, data sample on leading edge.
+ *  Mode 3: leading edge is falling edge, data sample on trailing edge.
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] mode The SPI transfer mode.
+ *  \return Operation status.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
+
+/**
+ *  \brief Set SPI baudrate
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] char_size The character size, see \ref spi_char_size.
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
+
+/**
+ *  \brief Set SPI data order
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] dord SPI data order (LSB/MSB first).
+ *  \return Operation status.
+ *  \retval ERR_INVALID_ARG The character size is not supported.
+ *  \retval ERR_BUSY SPI is not ready to accept new setting.
+ *  \retval 0 Operation done successfully.
+ */
+int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
+
+/**
+ * \brief Enable interrupt on character output
+ *
+ * Enable interrupt when a new character can be written
+ * to the SPI device.
+ *
+ * \param[in] dev   Pointer to the SPI device instance
+ * \param[in] state true  = enable output interrupt
+ *                  false = disable output interrupt
+ *
+ * \return Status code
+ * \retval 0 Ok status
+ */
+int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
+
+/**
+ * \brief Enable interrupt on character input
+ *
+ * Enable interrupt when a new character is ready to be
+ * read from the SPI device.
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ * \param[in] state true  = enable input interrupts
+ *                  false = disable input interrupt
+ *
+ * \return Status code
+ * \retval 0 OK Status
+ */
+int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
+
+/**
+ *  \brief Read one character to SPI device instance
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *
+ *  \return Character read from SPI module
+ */
+uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
+
+/**
+ *  \brief Write one character to assigned buffer
+ *  \param[in, out] dev Pointer to the SPI device instance.
+ *  \param[in] data
+ *
+ *  \return Status code of write operation
+ *  \retval 0 Write operation OK
+ */
+int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
+
+/**
+ * \brief Check if TX ready
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return TX ready state
+ * \retval true TX ready
+ * \retval false TX not ready
+ */
+bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if RX character ready
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return RX character ready state
+ * \retval true RX character ready
+ * \retval false RX character not ready
+ */
+bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if SS deactiviation detected
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return SS deactiviation state
+ * \retval true SS deactiviation detected
+ * \retval false SS deactiviation not detected
+ */
+bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
+
+/**
+ * \brief Check if error is detected
+ *
+ * \param[in] dev  Pointer to the SPI device instance
+ *
+ * \return Error detection state
+ * \retval true Error detected
+ * \retval false Error not detected
+ */
+bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_spi_sync.h b/Smol Watch Project/My Project/hal/include/hpl_spi_sync.h
new file mode 100644
index 0000000..dc88648
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_spi_sync.h	
@@ -0,0 +1,70 @@
+/**
+ * \file
+ *
+ * \brief Common SPI related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SPI_SYNC_H_INCLUDED
+#define _HPL_SPI_SYNC_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+#include <hpl_spi.h>
+
+/**
+ * \addtogroup hpl_spi HPL SPI
+ *
+ * \section hpl_spi_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI driver to support sync HAL */
+struct _spi_sync_dev {
+	/** Pointer to the hardware base or private data for special device. */
+	void *prvt;
+	/** Data size, number of bytes for each character */
+	uint8_t char_size;
+	/** Dummy byte used in master mode when reading the slave */
+	uint16_t dummy_byte;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_time_measure.h b/Smol Watch Project/My Project/hal/include/hpl_time_measure.h
new file mode 100644
index 0000000..5d688df
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_time_measure.h	
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Time measure related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_TIME_MEASURE_H_INCLUDED
+#define _HPL_TIME_MEASURE_H_INCLUDED
+
+/**
+ * \addtogroup HPL Time measure
+ *
+ * \section hpl_time_measure_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief System time type
+ */
+typedef uint32_t system_time_t;
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize system time module
+ *
+ * \param[in] hw The pointer to hardware instance to initialize
+ */
+void _system_time_init(void *const hw);
+
+/**
+ * \brief Deinitialize system time module
+ *
+ * \param[in] hw The pointer to hardware instance to initialize
+ */
+void _system_time_deinit(void *const hw);
+
+/**
+ * \brief Get system time
+ *
+ * \param[in] hw The pointer to hardware instance to initialize
+ */
+system_time_t _system_time_get(const void *const hw);
+
+/**
+ * \brief Get maximum possible system time
+ *
+ * \param[in] hw The pointer to hardware instance to initialize
+ */
+system_time_t _system_time_get_max_time_value(const void *const hw);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_TIME_MEASURE_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_timer.h b/Smol Watch Project/My Project/hal/include/hpl_timer.h
new file mode 100644
index 0000000..9bdfbb7
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_timer.h	
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Timer related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_TIMER_H_INCLUDED
+#define _HPL_TIMER_H_INCLUDED
+
+/**
+ * \addtogroup HPL Timer
+ *
+ * \section hpl_timer_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Timer device structure
+ *
+ * The Timer device structure forward declaration.
+ */
+struct _timer_device;
+
+/**
+ * \brief Timer interrupt callbacks
+ */
+struct _timer_callbacks {
+	void (*period_expired)(struct _timer_device *device);
+};
+
+/**
+ * \brief Timer device structure
+ */
+struct _timer_device {
+	struct _timer_callbacks timer_cb;
+	struct _irq_descriptor  irq;
+	void *                  hw;
+};
+
+/**
+ * \brief Timer functions, pointers to low-level functions
+ */
+struct _timer_hpl_interface {
+	int32_t (*init)(struct _timer_device *const device, void *const hw);
+	void (*deinit)(struct _timer_device *const device);
+	void (*start_timer)(struct _timer_device *const device);
+	void (*stop_timer)(struct _timer_device *const device);
+	void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
+	uint32_t (*get_period)(const struct _timer_device *const device);
+	bool (*is_timer_started)(const struct _timer_device *const device);
+	void (*set_timer_irq)(struct _timer_device *const device);
+};
+/**
+ * \brief Initialize TCC
+ *
+ * This function does low level TCC configuration.
+ *
+ * \param[in] device The pointer to timer device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _timer_init(struct _timer_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize TCC
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_deinit(struct _timer_device *const device);
+
+/**
+ * \brief Start hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_start(struct _timer_device *const device);
+
+/**
+ * \brief Stop hardware timer
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_stop(struct _timer_device *const device);
+
+/**
+ * \brief Set timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
+
+/**
+ * \brief Retrieve timer period
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Timer period
+ */
+uint32_t _timer_get_period(const struct _timer_device *const device);
+
+/**
+ * \brief Check if timer is running
+ *
+ * \param[in] device The pointer to timer device instance
+ *
+ * \return Check status.
+ * \retval true The given timer is running
+ * \retval false The given timer is not running
+ */
+bool _timer_is_started(const struct _timer_device *const device);
+
+/**
+ * \brief Set timer IRQ
+ *
+ * \param[in] device The pointer to timer device instance
+ */
+void _timer_set_irq(struct _timer_device *const device);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_TIMER_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_usart.h b/Smol Watch Project/My Project/hal/include/hpl_usart.h
new file mode 100644
index 0000000..0e09501
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_usart.h	
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USART_H_INCLUDED
+#define _HPL_USART_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART SYNC
+ *
+ * \section hpl_usart_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART flow control state
+ */
+union usart_flow_control_state {
+	struct {
+		uint8_t cts : 1;
+		uint8_t rts : 1;
+		uint8_t unavailable : 1;
+		uint8_t reserved : 5;
+	} bit;
+	uint8_t value;
+};
+
+/**
+ * \brief USART baud rate mode
+ */
+enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
+
+/**
+ * \brief USART data order
+ */
+enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
+
+/**
+ * \brief USART mode
+ */
+enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
+
+/**
+ * \brief USART parity
+ */
+enum usart_parity {
+	USART_PARITY_EVEN  = 0,
+	USART_PARITY_ODD   = 1,
+	USART_PARITY_NONE  = 2,
+	USART_PARITY_SPACE = 3,
+	USART_PARITY_MARK  = 4
+};
+
+/**
+ * \brief USART stop bits mode
+ */
+enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
+
+/**
+ * \brief USART character size
+ */
+enum usart_character_size {
+	USART_CHARACTER_SIZE_8BITS = 0,
+	USART_CHARACTER_SIZE_9BITS = 1,
+	USART_CHARACTER_SIZE_5BITS = 5,
+	USART_CHARACTER_SIZE_6BITS = 6,
+	USART_CHARACTER_SIZE_7BITS = 7
+};
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_usart_async.h b/Smol Watch Project/My Project/hal/include/hpl_usart_async.h
new file mode 100644
index 0000000..3f833d1
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_usart_async.h	
@@ -0,0 +1,270 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USART_ASYNC_H_INCLUDED
+#define _HPL_USART_ASYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART
+ *
+ * \section hpl_usart_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_usart.h"
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART callback types
+ */
+enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
+
+/**
+ * \brief USART device structure
+ *
+ * The USART device structure forward declaration.
+ */
+struct _usart_async_device;
+
+/**
+ * \brief USART interrupt callbacks
+ */
+struct _usart_async_callbacks {
+	void (*tx_byte_sent)(struct _usart_async_device *device);
+	void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
+	void (*tx_done_cb)(struct _usart_async_device *device);
+	void (*error_cb)(struct _usart_async_device *device);
+};
+
+/**
+ * \brief USART descriptor device structure
+ */
+struct _usart_async_device {
+	struct _usart_async_callbacks usart_cb;
+	struct _irq_descriptor        irq;
+	void *                        hw;
+};
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize asynchronous USART
+ *
+ * This function does low level USART configuration.
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize USART
+ *
+ * This function closes the given USART by disabling its clock.
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_deinit(struct _usart_async_device *const device);
+
+/**
+ * \brief Enable usart module
+ *
+ * This function will enable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable(struct _usart_async_device *const device);
+
+/**
+ * \brief Disable usart module
+ *
+ * This function will disable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_disable(struct _usart_async_device *const device);
+
+/**
+ * \brief Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                          const enum usart_baud_rate_mode mode, const uint8_t fraction);
+
+/**
+ * \brief Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
+
+/**
+ * \brief Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
+
+/**
+ * \brief Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
+
+/**
+ * \brief Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
+
+/**
+ * \brief Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
+
+/**
+ * \brief Retrieve usart status
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
+
+/**
+ * \brief Write a byte to the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ */
+void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
+
+/**
+ * \brief Check if USART is ready to send next byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART is ready to send next byte
+ * \retval false if the USART is not ready to send next byte
+ */
+bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
+
+/**
+ * \brief Set the state of flow control pins
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] state - A state of flow control pins to set
+ */
+void _usart_async_set_flow_control_state(struct _usart_async_device *const    device,
+                                         const union usart_flow_control_state state);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the of flow control pins.
+ *
+ * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
+ */
+union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
+
+/**
+ * \brief Enable data register empty interrupt
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
+
+/**
+ * \brief Enable transmission complete interrupt
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
+
+/**
+ * \brief Retrieve ordinal number of the given USART hardware instance
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return The ordinal number of the given USART hardware instance
+ */
+uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
+
+/**
+ * \brief Enable/disable USART interrupt
+ *
+ * param[in] device The pointer to USART device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
+                                const bool state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_ASYNC_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/include/hpl_usart_sync.h b/Smol Watch Project/My Project/hal/include/hpl_usart_sync.h
new file mode 100644
index 0000000..abc7264
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/include/hpl_usart_sync.h	
@@ -0,0 +1,254 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SYNC_USART_H_INCLUDED
+#define _HPL_SYNC_USART_H_INCLUDED
+
+/**
+ * \addtogroup HPL USART SYNC
+ *
+ * \section hpl_usart_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <hpl_usart.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART descriptor device structure
+ */
+struct _usart_sync_device {
+	void *hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous USART
+ *
+ * This function does low level USART configuration.
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize USART
+ *
+ * This function closes the given USART by disabling its clock.
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_deinit(struct _usart_sync_device *const device);
+
+/**
+ * \brief Enable usart module
+ *
+ * This function will enable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_enable(struct _usart_sync_device *const device);
+
+/**
+ * \brief Disable usart module
+ *
+ * This function will disable the usart module
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+void _usart_sync_disable(struct _usart_sync_device *const device);
+
+/**
+ * \brief Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                         const enum usart_baud_rate_mode mode, const uint8_t fraction);
+
+/**
+ * \brief Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
+
+/**
+ * \brief Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
+
+/**
+ * \brief Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
+
+/**
+ * \brief Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
+
+/**
+ * \brief Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
+
+/**
+ * \brief Retrieve usart status
+ *
+ * \param[in] device The pointer to USART device instance
+ */
+uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Write a byte to the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ */
+void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
+
+/**
+ * \brief Read a byte from the given USART instance
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] data Data to write
+ *
+ * \return Data received via USART interface.
+ */
+uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if USART is ready to send next byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART is ready to send next byte
+ * \retval false if the USART is not ready to send next byte
+ */
+bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if USART transmitter has sent the byte
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the ready check.
+ * \retval true if the USART transmitter has sent the byte
+ * \retval false if the USART transmitter has not send the byte
+ */
+bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Check if there is data received by USART
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return Status of the data received check.
+ * \retval true if the USART has received a byte
+ * \retval false if the USART has not received a byte
+ */
+bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Set the state of flow control pins
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] state - A state of flow control pins to set
+ */
+void _usart_sync_set_flow_control_state(struct _usart_sync_device *const     device,
+                                        const union usart_flow_control_state state);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the of flow control pins.
+ *
+ * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
+ */
+union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
+
+/**
+ * \brief Retrieve ordinal number of the given USART hardware instance
+ *
+ * \param[in] device The pointer to USART device instance
+ *
+ * \return The ordinal number of the given USART hardware instance
+ */
+uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_SYNC_USART_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/src/hal_adc_sync.c b/Smol Watch Project/My Project/hal/src/hal_adc_sync.c
new file mode 100644
index 0000000..33e0d92
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_adc_sync.c	
@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \brief Indicates HAL being compiled. Must be defined before including.
+ */
+#define _COMPILING_HAL
+
+#include "hal_adc_sync.h"
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Maximum amount of ADC interface instances
+ */
+#define MAX_ADC_AMOUNT ADC_INST_NUM
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
+{
+	ASSERT(descr && hw);
+
+	return _adc_sync_init(&descr->device, hw);
+}
+
+/**
+ * \brief Deinitialize ADC
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	_adc_sync_deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable ADC
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_enable_channel(&descr->device, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable ADC
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_disable_channel(&descr->device, channel);
+	return ERR_NONE;
+}
+
+/*
+ * \brief Read data from ADC
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length)
+{
+	uint8_t  data_size;
+	uint16_t offset = 0;
+
+	ASSERT(descr && buffer && length);
+	data_size = _adc_sync_get_data_size(&descr->device);
+	ASSERT(!(length % data_size));
+
+	do {
+		uint16_t result;
+		_adc_sync_convert(&descr->device);
+
+		while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
+			;
+
+		result         = _adc_sync_read_channel_data(&descr->device, channel);
+		buffer[offset] = result;
+		if (1 < data_size) {
+			buffer[offset + 1] = result >> 8;
+		}
+		offset += data_size;
+	} while (offset < length);
+
+	return offset;
+}
+
+/**
+ * \brief Set ADC reference source
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
+{
+	ASSERT(descr);
+	_adc_sync_set_reference_source(&descr->device, reference);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC resolution
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
+{
+	ASSERT(descr);
+	_adc_sync_set_resolution(&descr->device, resolution);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC input source of a channel
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC thresholds
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold)
+{
+	ASSERT(descr);
+	_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC gain
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_gain(&descr->device, channel, gain);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC conversion mode
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_conversion_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC differential mode
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC window mode
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_window_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
+{
+	ASSERT(descr && state);
+	_adc_sync_get_threshold_state(&descr->device, state);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if conversion is complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	return _adc_sync_is_channel_conversion_done(&descr->device, channel);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t adc_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+//@}
diff --git a/Smol Watch Project/My Project/hal/src/hal_atomic.c b/Smol Watch Project/My Project/hal/src/hal_atomic.c
new file mode 100644
index 0000000..f56418e
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_atomic.c	
@@ -0,0 +1,66 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_atomic.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Disable interrupts, enter critical section
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic)
+{
+	*atomic = __get_PRIMASK();
+	__disable_irq();
+	__DMB();
+}
+
+/**
+ * \brief Exit atomic section
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic)
+{
+	__DMB();
+	__set_PRIMASK(*atomic);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t atomic_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_calendar.c b/Smol Watch Project/My Project/hal/src/hal_calendar.c
new file mode 100644
index 0000000..842cfb8
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_calendar.c	
@@ -0,0 +1,643 @@
+/**
+ * \file
+ *
+ * \brief Generic CALENDAR functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_calendar.h"
+#include <utils.h>
+#include <utils_assert.h>
+#include <hal_atomic.h>
+
+#define CALENDAR_VERSION 0x00000001u
+#define SECS_IN_LEAP_YEAR 31622400
+#define SECS_IN_NON_LEAP_YEAR 31536000
+#define SECS_IN_31DAYS 2678400
+#define SECS_IN_30DAYS 2592000
+#define SECS_IN_29DAYS 2505600
+#define SECS_IN_28DAYS 2419200
+#define SECS_IN_DAY 86400
+#define SECS_IN_HOUR 3600
+#define SECS_IN_MINUTE 60
+#define DEFAULT_BASE_YEAR 1970
+
+#define SET_ALARM_BUSY 1
+#define PROCESS_ALARM_BUSY 2
+
+/** \brief leap year check
+ *  \retval false  not leap year.
+ *  \retval true  leap year.
+ */
+static bool leap_year(uint16_t year)
+{
+	if (year & 3) {
+		return false;
+	} else {
+		return true;
+	}
+}
+
+/** \brief calculate the seconds in specified year/month
+ *  \retval 0  month error.
+ */
+static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
+{
+	uint32_t sec_in_month = 0;
+
+	if (leap_year(year)) {
+		switch (month) {
+		case 1:
+		case 3:
+		case 5:
+		case 7:
+		case 8:
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_29DAYS;
+			break;
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+			break;
+		default:
+			break;
+		}
+	} else {
+		switch (month) {
+		case 1:
+		case 3:
+		case 5:
+		case 7:
+		case 8:
+		case 10:
+		case 12:
+			sec_in_month = SECS_IN_31DAYS;
+			break;
+		case 2:
+			sec_in_month = SECS_IN_28DAYS;
+			break;
+		case 4:
+		case 6:
+		case 9:
+		case 11:
+			sec_in_month = SECS_IN_30DAYS;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return sec_in_month;
+}
+
+/** \brief convert timestamp to date/time
+ */
+static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
+                                             struct calendar_date_time *dt)
+{
+	uint32_t tmp, sec_in_year, sec_in_month;
+	uint32_t tmp_year    = calendar->base_year;
+	uint8_t  tmp_month   = 1;
+	uint8_t  tmp_day     = 1;
+	uint8_t  tmp_hour    = 0;
+	uint8_t  tmp_minutes = 0;
+
+	tmp = ts;
+
+	/* Find year */
+	while (true) {
+		sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+
+		if (tmp >= sec_in_year) {
+			tmp -= sec_in_year;
+			tmp_year++;
+		} else {
+			break;
+		}
+	}
+	/* Find month of year */
+	while (true) {
+		sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+
+		if (tmp >= sec_in_month) {
+			tmp -= sec_in_month;
+			tmp_month++;
+		} else {
+			break;
+		}
+	}
+	/* Find day of month */
+	while (true) {
+		if (tmp >= SECS_IN_DAY) {
+			tmp -= SECS_IN_DAY;
+			tmp_day++;
+		} else {
+			break;
+		}
+	}
+	/* Find hour of day */
+	while (true) {
+		if (tmp >= SECS_IN_HOUR) {
+			tmp -= SECS_IN_HOUR;
+			tmp_hour++;
+		} else {
+			break;
+		}
+	}
+	/* Find minute in hour */
+	while (true) {
+		if (tmp >= SECS_IN_MINUTE) {
+			tmp -= SECS_IN_MINUTE;
+			tmp_minutes++;
+		} else {
+			break;
+		}
+	}
+
+	dt->date.year  = tmp_year;
+	dt->date.month = tmp_month;
+	dt->date.day   = tmp_day;
+	dt->time.hour  = tmp_hour;
+	dt->time.min   = tmp_minutes;
+	dt->time.sec   = tmp;
+
+	return ERR_NONE;
+}
+
+/** \brief convert date/time to timestamp
+ *  \return timestamp
+ */
+static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
+{
+	uint32_t tmp = 0;
+	uint32_t i   = 0;
+	uint8_t  year, month, day, hour, minutes, seconds;
+
+	year    = dt->date.year - calendar->base_year;
+	month   = dt->date.month;
+	day     = dt->date.day;
+	hour    = dt->time.hour;
+	minutes = dt->time.min;
+	seconds = dt->time.sec;
+
+	/* tot up year field */
+	for (i = 0; i < year; ++i) {
+		if (leap_year(calendar->base_year + i)) {
+			tmp += SECS_IN_LEAP_YEAR;
+		} else {
+			tmp += SECS_IN_NON_LEAP_YEAR;
+		}
+	}
+
+	/* tot up month field */
+	for (i = 1; i < month; ++i) {
+		tmp += get_secs_in_month(dt->date.year, i);
+	}
+
+	/* tot up day/hour/minute/second fields */
+	tmp += (day - 1) * SECS_IN_DAY;
+	tmp += hour * SECS_IN_HOUR;
+	tmp += minutes * SECS_IN_MINUTE;
+	tmp += seconds;
+
+	return tmp;
+}
+
+/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
+ */
+static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
+                                struct calendar_alarm *current_dt)
+{
+	uint32_t alarm_ts;
+	uint32_t current_ts = current_dt->cal_alarm.timestamp;
+
+	alarm_ts = alarm->cal_alarm.timestamp;
+
+	/* calibrate timestamp */
+	switch (alarm->cal_alarm.option) {
+	case CALENDAR_ALARM_MATCH_SEC:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_MINUTE;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_MIN:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_HOUR;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_HOUR:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += SECS_IN_DAY;
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_DAY:
+
+		if (alarm_ts <= current_ts) {
+			alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
+			                              current_dt->cal_alarm.datetime.date.month);
+		}
+
+		break;
+	case CALENDAR_ALARM_MATCH_MONTH:
+
+		if (alarm_ts <= current_ts) {
+			if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
+				alarm_ts += SECS_IN_LEAP_YEAR;
+			} else {
+				alarm_ts += SECS_IN_NON_LEAP_YEAR;
+			}
+		}
+
+		break;
+	/* do nothing for year match */
+	case CALENDAR_ALARM_MATCH_YEAR:
+	default:
+		break;
+	}
+
+	/* desired timestamp after calibration */
+	alarm->cal_alarm.timestamp = alarm_ts;
+}
+
+/** \brief complete alarm to absolute date/time, then fill up the timestamp
+ */
+static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
+{
+	struct calendar_alarm current_dt;
+	uint32_t              tmp, current_ts;
+
+	/* get current date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &current_dt.cal_alarm.datetime);
+
+	current_dt.cal_alarm.timestamp = current_ts;
+
+	/* complete alarm */
+	switch (alarm->cal_alarm.option) {
+	case CALENDAR_ALARM_MATCH_SEC:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+		alarm->cal_alarm.datetime.time.min   = current_dt.cal_alarm.datetime.time.min;
+		break;
+	case CALENDAR_ALARM_MATCH_MIN:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		alarm->cal_alarm.datetime.time.hour  = current_dt.cal_alarm.datetime.time.hour;
+		break;
+	case CALENDAR_ALARM_MATCH_HOUR:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		alarm->cal_alarm.datetime.date.day   = current_dt.cal_alarm.datetime.date.day;
+		break;
+	case CALENDAR_ALARM_MATCH_DAY:
+		alarm->cal_alarm.datetime.date.year  = current_dt.cal_alarm.datetime.date.year;
+		alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+		break;
+	case CALENDAR_ALARM_MATCH_MONTH:
+		alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+		break;
+	case CALENDAR_ALARM_MATCH_YEAR:
+		break;
+	default:
+		break;
+	}
+
+	/* fill up the timestamp */
+	tmp                        = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
+	alarm->cal_alarm.timestamp = tmp;
+
+	/* calibrate the timestamp */
+	calibrate_timestamp(calendar, alarm, &current_dt);
+	convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
+}
+
+/** \brief add new alarm into the list in ascending order
+ */
+static int32_t calendar_add_new_alarm(struct list_descriptor *list, struct calendar_alarm *alarm)
+{
+	struct calendar_descriptor *calendar = CONTAINER_OF(list, struct calendar_descriptor, alarms);
+	struct calendar_alarm *     head, *it, *prev = NULL;
+
+	/*get the head of alarms list*/
+	head = (struct calendar_alarm *)list_get_head(list);
+
+	/*if head is null, insert new alarm as head*/
+	if (!head) {
+		list_insert_as_head(list, alarm);
+		_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
+		return ERR_NONE;
+	}
+
+	/*insert the new alarm in accending order, the head will be invoked firstly */
+	for (it = head; it; it = (struct calendar_alarm *)list_get_next_element(it)) {
+		if (alarm->cal_alarm.timestamp <= it->cal_alarm.timestamp) {
+			break;
+		}
+
+		prev = it;
+	}
+
+	/*insert new alarm into the list */
+	if (it == head) {
+		list_insert_as_head(list, alarm);
+		/*get the head and set it into register*/
+		_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
+
+	} else {
+		list_insert_after(prev, alarm);
+	}
+
+	return ERR_NONE;
+}
+
+/** \brief callback for alarm
+ */
+static void calendar_alarm(struct calendar_dev *const dev)
+{
+	struct calendar_descriptor *calendar = CONTAINER_OF(dev, struct calendar_descriptor, device);
+
+	struct calendar_alarm *head, *it, current_dt;
+
+	if ((calendar->flags & SET_ALARM_BUSY) || (calendar->flags & PROCESS_ALARM_BUSY)) {
+		calendar->flags |= PROCESS_ALARM_BUSY;
+		return;
+	}
+
+	/* get current timestamp */
+	current_dt.cal_alarm.timestamp = _calendar_get_counter(dev);
+
+	/* get the head */
+	head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
+	ASSERT(head);
+
+	/* remove all alarms and invoke them*/
+	for (it = head; it; it = (struct calendar_alarm *)list_get_head(&calendar->alarms)) {
+		/* check the timestamp with current timestamp*/
+		if (it->cal_alarm.timestamp <= current_dt.cal_alarm.timestamp) {
+			list_remove_head(&calendar->alarms);
+			it->callback(calendar);
+
+			if (it->cal_alarm.mode == REPEAT) {
+				calibrate_timestamp(calendar, it, &current_dt);
+				convert_timestamp_to_datetime(calendar, it->cal_alarm.timestamp, &it->cal_alarm.datetime);
+				calendar_add_new_alarm(&calendar->alarms, it);
+			}
+		} else {
+			break;
+		}
+	}
+
+	/*if no alarm in the list, register null */
+	if (!it) {
+		_calendar_register_callback(&calendar->device, NULL);
+		return;
+	}
+
+	/*put the new head into register */
+	_calendar_set_comp(&calendar->device, it->cal_alarm.timestamp);
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+	int32_t ret = 0;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	if (calendar->device.hw == hw) {
+		/* Already initialized with current configuration */
+		return ERR_NONE;
+	} else if (calendar->device.hw != NULL) {
+		/* Initialized with another configuration */
+		return ERR_ALREADY_INITIALIZED;
+	}
+	calendar->device.hw = (void *)hw;
+	ret                 = _calendar_init(&calendar->device);
+	calendar->base_year = DEFAULT_BASE_YEAR;
+
+	return ret;
+}
+
+/** \brief Reset the Calendar
+ */
+int32_t calendar_deinit(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	if (calendar->device.hw == NULL) {
+		return ERR_NOT_INITIALIZED;
+	}
+	_calendar_deinit(&calendar->device);
+	calendar->device.hw = NULL;
+
+	return ERR_NONE;
+}
+
+/** \brief Enable the Calendar
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	_calendar_enable(&calendar->device);
+
+	return ERR_NONE;
+}
+
+/** \brief Disable the Calendar
+ */
+int32_t calendar_disable(struct calendar_descriptor *const calendar)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	_calendar_disable(&calendar->device);
+
+	return ERR_NONE;
+}
+
+/** \brief Set base year for calendar
+ */
+int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year)
+{
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	calendar->base_year = p_base_year;
+
+	return ERR_NONE;
+}
+
+/** \brief Set time for calendar
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
+{
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert time to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+	dt.time.sec  = p_calendar_time->sec;
+	dt.time.min  = p_calendar_time->min;
+	dt.time.hour = p_calendar_time->hour;
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+
+	_calendar_set_counter(&calendar->device, new_ts);
+
+	return ERR_NONE;
+}
+
+/** \brief Set date for calendar
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
+{
+	struct calendar_date_time dt;
+	uint32_t                  current_ts, new_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert date to timestamp */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, &dt);
+	dt.date.day   = p_calendar_date->day;
+	dt.date.month = p_calendar_date->month;
+	dt.date.year  = p_calendar_date->year;
+
+	new_ts = convert_datetime_to_timestamp(calendar, &dt);
+
+	_calendar_set_counter(&calendar->device, new_ts);
+
+	return ERR_NONE;
+}
+
+/** \brief Get date/time for calendar
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time)
+{
+	uint32_t current_ts;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+
+	/* convert current timestamp to date/time */
+	current_ts = _calendar_get_counter(&calendar->device);
+	convert_timestamp_to_datetime(calendar, current_ts, date_time);
+
+	return ERR_NONE;
+}
+
+/** \brief Set alarm for calendar
+ */
+int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
+                           calendar_cb_alarm_t callback)
+{
+	struct calendar_alarm *head;
+
+	/* Sanity check arguments */
+	ASSERT(calendar);
+	ASSERT(alarm);
+
+	alarm->callback = callback;
+
+	fill_alarm(calendar, alarm);
+
+	calendar->flags |= SET_ALARM_BUSY;
+
+	head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
+
+	if (head != NULL) {
+		/* already added */
+		if (is_list_element(&calendar->alarms, alarm)) {
+			if (callback == NULL) {
+				/* remove alarm */
+				list_delete_element(&calendar->alarms, alarm);
+
+				if (!list_get_head(&calendar->alarms)) {
+					_calendar_register_callback(&calendar->device, NULL);
+				}
+			} else {
+				/* re-add */
+				list_delete_element(&calendar->alarms, alarm);
+				calendar_add_new_alarm(&calendar->alarms, alarm);
+			}
+		} else if (callback != NULL) {
+			calendar_add_new_alarm(&calendar->alarms, alarm);
+		}
+
+		calendar->flags &= ~SET_ALARM_BUSY;
+
+		if (calendar->flags & PROCESS_ALARM_BUSY) {
+			CRITICAL_SECTION_ENTER()
+			calendar->flags &= ~PROCESS_ALARM_BUSY;
+			_calendar_set_irq(&calendar->device);
+			CRITICAL_SECTION_LEAVE()
+		}
+	} else if (callback != NULL) {
+		/* if head is NULL, Register callback*/
+		_calendar_register_callback(&calendar->device, calendar_alarm);
+		calendar_add_new_alarm(&calendar->alarms, alarm);
+	}
+
+	calendar->flags &= ~SET_ALARM_BUSY;
+
+	return ERR_NONE;
+}
+
+/** \brief Retrieve driver version
+ *  \return Current driver version
+ */
+uint32_t calendar_get_version(void)
+{
+	return CALENDAR_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_delay.c b/Smol Watch Project/My Project/hal/src/hal_delay.c
new file mode 100644
index 0000000..6f77cc7
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_delay.c	
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief HAL delay related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+#include "hal_delay.h"
+#include <hpl_delay.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief The pointer to a hardware instance used by the driver.
+ */
+static void *hardware;
+
+/**
+ * \brief Initialize Delay driver
+ */
+void delay_init(void *const hw)
+{
+	_delay_init(hardware = hw);
+}
+
+/**
+ * \brief Perform delay in us
+ */
+void delay_us(const uint16_t us)
+{
+	_delay_cycles(hardware, _get_cycles_for_us(us));
+}
+
+/**
+ * \brief Perform delay in ms
+ */
+void delay_ms(const uint16_t ms)
+{
+	_delay_cycles(hardware, _get_cycles_for_ms(ms));
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t delay_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_ext_irq.c b/Smol Watch Project/My Project/hal/src/hal_ext_irq.c
new file mode 100644
index 0000000..d0b9292
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_ext_irq.c	
@@ -0,0 +1,188 @@
+/**
+ * \file
+ *
+ * \brief External interrupt functionality imkplementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_ext_irq.h"
+
+#define EXT_IRQ_AMOUNT 3
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief External IRQ struct
+ */
+struct ext_irq {
+	ext_irq_cb_t cb;
+	uint32_t     pin;
+};
+
+/* Remove KEIL compiling error in case no IRQ line selected */
+#if EXT_IRQ_AMOUNT == 0
+#undef EXT_IRQ_AMOUNT
+#define EXT_IRQ_AMOUNT 1
+#endif
+
+/**
+ * \brief Array of external IRQs callbacks
+ */
+static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT];
+
+static void process_ext_irq(const uint32_t pin);
+
+/**
+ * \brief Initialize external irq component if any
+ */
+int32_t ext_irq_init(void)
+{
+	uint16_t i;
+
+	for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
+		ext_irqs[i].pin = 0xFFFFFFFF;
+		ext_irqs[i].cb  = NULL;
+	}
+
+	return _ext_irq_init(process_ext_irq);
+}
+
+/**
+ * \brief Deinitialize external irq if any
+ */
+int32_t ext_irq_deinit(void)
+{
+	return _ext_irq_deinit();
+}
+
+/**
+ * \brief Register callback for the given external interrupt
+ */
+int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb)
+{
+	uint8_t i = 0, j = 0;
+	bool    found = false;
+
+	for (; i < EXT_IRQ_AMOUNT; i++) {
+		if (ext_irqs[i].pin == pin) {
+			ext_irqs[i].cb = cb;
+			found          = true;
+			break;
+		}
+	}
+
+	if (NULL == cb) {
+		if (!found) {
+			return ERR_INVALID_ARG;
+		}
+		return _ext_irq_enable(pin, false);
+	}
+
+	if (!found) {
+		for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
+			if (NULL == ext_irqs[i].cb) {
+				ext_irqs[i].cb  = cb;
+				ext_irqs[i].pin = pin;
+				found           = true;
+				break;
+			}
+		}
+		for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
+			if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
+				struct ext_irq tmp = ext_irqs[j];
+
+				ext_irqs[j] = ext_irqs[i];
+				ext_irqs[i] = tmp;
+			}
+		}
+	}
+
+	if (!found) {
+		return ERR_INVALID_ARG;
+	}
+
+	return _ext_irq_enable(pin, true);
+}
+
+/**
+ * \brief Enable external irq
+ */
+int32_t ext_irq_enable(const uint32_t pin)
+{
+	return _ext_irq_enable(pin, true);
+}
+
+/**
+ * \brief Disable external irq
+ */
+int32_t ext_irq_disable(const uint32_t pin)
+{
+	return _ext_irq_enable(pin, false);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t ext_irq_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \brief Interrupt processing routine
+ *
+ * \param[in] pin The pin which triggered the interrupt
+ */
+static void process_ext_irq(const uint32_t pin)
+{
+	uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+	while (upper >= lower) {
+		middle = (upper + lower) >> 1;
+		if (middle >= EXT_IRQ_AMOUNT) {
+			return;
+		}
+
+		if (ext_irqs[middle].pin == pin) {
+			if (ext_irqs[middle].cb) {
+				ext_irqs[middle].cb();
+			}
+			return;
+		}
+
+		if (ext_irqs[middle].pin < pin) {
+			lower = middle + 1;
+		} else {
+			upper = middle - 1;
+		}
+	}
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_gpio.c b/Smol Watch Project/My Project/hal/src/hal_gpio.c
new file mode 100644
index 0000000..00dfea6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_gpio.c	
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_gpio.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t gpio_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_i2c_m_sync.c b/Smol Watch Project/My Project/hal/src/hal_i2c_m_sync.c
new file mode 100644
index 0000000..30821a2
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_i2c_m_sync.c	
@@ -0,0 +1,258 @@
+/**
+ * \file
+ *
+ * \brief I/O I2C related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hal_i2c_m_sync.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Sync version of I2C I/O read
+ */
+static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+	struct _i2c_m_msg       msg;
+	int32_t                 ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = buf;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret) {
+		return ret;
+	}
+
+	return n;
+}
+
+/**
+ * \brief Sync version of I2C I/O write
+ */
+static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+	struct _i2c_m_msg       msg;
+	int32_t                 ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = (uint8_t *)buf;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret) {
+		return ret;
+	}
+
+	return n;
+}
+
+/**
+ * \brief Sync version of i2c initialize
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
+{
+	int32_t init_status;
+	ASSERT(i2c);
+
+	init_status = _i2c_m_sync_init(&i2c->device, hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	/* Init I/O */
+	i2c->io.read  = i2c_m_sync_read;
+	i2c->io.write = i2c_m_sync_write;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief deinitialize
+ */
+int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c)
+{
+	int32_t status;
+	ASSERT(i2c);
+
+	status = _i2c_m_sync_deinit(&i2c->device);
+	if (status) {
+		return status;
+	}
+
+	i2c->io.read  = NULL;
+	i2c->io.write = NULL;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c enable
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
+{
+	return _i2c_m_sync_enable(&i2c->device);
+}
+
+/**
+ * \brief Sync version of i2c disable
+ */
+int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c)
+{
+	return _i2c_m_sync_disable(&i2c->device);
+}
+
+/**
+ * \brief Sync version of i2c set slave address
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
+{
+	return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
+}
+
+/**
+ * \brief Sync version of i2c set baudrate
+ */
+int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate)
+{
+	return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate);
+}
+
+/**
+ * \brief Sync version of i2c write command
+ */
+int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = buffer;
+	msg.len    = length;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c read command
+ */
+int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = buffer;
+	msg.len    = length;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c transfer command
+ */
+int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg)
+{
+	return _i2c_m_sync_transfer(&i2c->device, msg);
+}
+
+/**
+ * \brief Sync version of i2c send stop condition command
+ */
+int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c)
+{
+	return _i2c_m_sync_send_stop(&i2c->device);
+}
+
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
+{
+	*io = &i2c->io;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t i2c_m_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_init.c b/Smol Watch Project/My Project/hal/src/hal_init.c
new file mode 100644
index 0000000..fb65341
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_init.c	
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_init.h"
+
+/**
+ * \brief Driver version
+ */
+#define HAL_INIT_VERSION 0x00000001u
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t init_get_version(void)
+{
+	return HAL_INIT_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_io.c b/Smol Watch Project/My Project/hal/src/hal_io.c
new file mode 100644
index 0000000..7e8feb0
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_io.c	
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief I/O functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hal_io.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t io_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->write(io_descr, buf, length);
+}
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->read(io_descr, buf, length);
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_pwm.c b/Smol Watch Project/My Project/hal/src/hal_pwm.c
new file mode 100644
index 0000000..bc0629f
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_pwm.c	
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief PWM functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_pwm.h"
+#include <utils_assert.h>
+#include <utils.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+static void pwm_period_expired(struct _pwm_device *device);
+static void pwm_detect_fault(struct _pwm_device *device);
+
+/**
+ * \brief Initialize pwm
+ */
+int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func)
+{
+	ASSERT(descr && hw && func);
+	descr->func = func;
+	descr->func->init(&descr->device, hw);
+	descr->device.callback.pwm_period_cb = pwm_period_expired;
+	descr->device.callback.pwm_error_cb  = pwm_detect_fault;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize pwm
+ */
+int32_t pwm_deinit(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr && descr->func);
+	descr->func->deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Start pwm
+ */
+int32_t pwm_enable(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr && descr->func);
+	if (descr->func->is_pwm_enabled(&descr->device)) {
+		return ERR_DENIED;
+	}
+	descr->func->start_pwm(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Stop pwm
+ */
+int32_t pwm_disable(struct pwm_descriptor *const descr)
+{
+	ASSERT(descr && descr->func);
+	if (!descr->func->is_pwm_enabled(&descr->device)) {
+		return ERR_DENIED;
+	}
+	descr->func->stop_pwm(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Register PWM callback
+ */
+int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb)
+{
+	switch (type) {
+	case PWM_PERIOD_CB:
+		descr->pwm_cb.period = cb;
+		break;
+
+	case PWM_ERROR_CB:
+		descr->pwm_cb.error = cb;
+		break;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+	ASSERT(descr && descr->func);
+	descr->func->set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Change PWM parameter
+ */
+int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle)
+{
+	ASSERT(descr && descr->func);
+	descr->func->set_pwm_param(&descr->device, period, duty_cycle);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t pwm_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \internal Process interrupts caused by period experied
+ */
+static void pwm_period_expired(struct _pwm_device *device)
+{
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.period) {
+		descr->pwm_cb.period(descr);
+	}
+}
+
+/**
+ * \internal Process interrupts caused by pwm fault
+ */
+static void pwm_detect_fault(struct _pwm_device *device)
+{
+	struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+	if (descr->pwm_cb.error) {
+		descr->pwm_cb.error(descr);
+	}
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_slcd_sync.c b/Smol Watch Project/My Project/hal/src/hal_slcd_sync.c
new file mode 100644
index 0000000..573eb0e
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_slcd_sync.c	
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
+ *        declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hal_slcd_sync.h>
+#include <utils_assert.h>
+
+/**
+ * \brief              Initialize SLCD Descriptor
+ */
+int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw)
+{
+	ASSERT(descr && hw);
+	return _slcd_sync_init(&descr->dev, hw);
+}
+
+/**
+ * \brief              Deinitialize SLCD Descriptor
+ */
+int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	return _slcd_sync_deinit(&descr->dev);
+}
+
+/**
+ * \brief              Enable SLCD driver
+ *
+ */
+int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	return _slcd_sync_enable(&descr->dev);
+}
+/**
+ * \brief              Disable SLCD driver
+ *
+ */
+int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	return _slcd_sync_disable(&descr->dev);
+}
+/**
+ * \brief              Turn on a Segment
+ */
+int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg)
+{
+	ASSERT(descr);
+	return _slcd_sync_seg_on(&descr->dev, seg);
+}
+/**
+ * \brief              Turn off a Segment
+ */
+int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg)
+{
+	ASSERT(descr);
+	return _slcd_sync_seg_off(&descr->dev, seg);
+}
+/**
+ * \brief              Blink a Segment
+ */
+int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period)
+{
+	ASSERT(descr && period);
+	return _slcd_sync_seg_blink(&descr->dev, seg, period);
+}
+
+/**
+ * \brief              Displays a character
+ */
+int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index)
+{
+	ASSERT(descr);
+	return _slcd_sync_write_char(&descr->dev, character, index);
+}
+
+/**
+ * \brief              Displays character string string
+ */
+int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len,
+                               uint32_t index)
+{
+	uint32_t i;
+	ASSERT(descr && len);
+
+	for (i = 0; i < len; i++) {
+		if (_slcd_sync_write_char(&descr->dev, *(str + i), index + i) != ERR_NONE) {
+			return ERR_INVALID_ARG;
+		}
+	}
+	return ERR_NONE;
+}
+/**
+ * \brief               Start animation play by a segment array
+ */
+int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len,
+                                  const uint32_t period)
+{
+	ASSERT(descr && segs && len && period);
+	return _slcd_sync_start_animation(&descr->dev, segs, len, period);
+}
+
+/**
+ * \brief               Stop animation play by a segment array
+ */
+int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len)
+{
+	ASSERT(descr && segs && len);
+	return _slcd_sync_stop_animation(&descr->dev, segs, len);
+}
+
+/**
+ * \brief               Set animation Frequency
+ */
+int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period)
+{
+	ASSERT(descr && period);
+	return _slcd_sync_set_animation_period(&descr->dev, period);
+}
diff --git a/Smol Watch Project/My Project/hal/src/hal_sleep.c b/Smol Watch Project/My Project/hal/src/hal_sleep.c
new file mode 100644
index 0000000..89472f1
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/src/hal_sleep.c	
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_sleep.h"
+#include <hpl_sleep.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode)
+{
+	if (ERR_NONE != _set_sleep_mode(mode))
+		return ERR_INVALID_ARG;
+
+	_go_to_sleep();
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version
+ */
+uint32_t sleep_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/Smol Watch Project/My Project/hal/utils/include/compiler.h b/Smol Watch Project/My Project/hal/utils/include/compiler.h
new file mode 100644
index 0000000..f35db3d
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/compiler.h	
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Header
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/******************************************************************************
+ * compiler.h
+ *
+ * Created: 05.05.2014
+ * Author: N. Fomin
+ ******************************************************************************/
+
+#ifndef _COMPILER_H
+#define _COMPILER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifndef _UNIT_TEST_
+#include "parts.h"
+#endif
+#include "err_codes.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _COMPILER_H */
diff --git a/Smol Watch Project/My Project/hal/utils/include/err_codes.h b/Smol Watch Project/My Project/hal/utils/include/err_codes.h
new file mode 100644
index 0000000..a7aff01
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/err_codes.h	
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Error code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ERROR_CODES_H_INCLUDED
+#define ERROR_CODES_H_INCLUDED
+
+#define ERR_NONE 0
+#define ERR_INVALID_DATA -1
+#define ERR_NO_CHANGE -2
+#define ERR_ABORTED -3
+#define ERR_BUSY -4
+#define ERR_SUSPEND -5
+#define ERR_IO -6
+#define ERR_REQ_FLUSHED -7
+#define ERR_TIMEOUT -8
+#define ERR_BAD_DATA -9
+#define ERR_NOT_FOUND -10
+#define ERR_UNSUPPORTED_DEV -11
+#define ERR_NO_MEMORY -12
+#define ERR_INVALID_ARG -13
+#define ERR_BAD_ADDRESS -14
+#define ERR_BAD_FORMAT -15
+#define ERR_BAD_FRQ -16
+#define ERR_DENIED -17
+#define ERR_ALREADY_INITIALIZED -18
+#define ERR_OVERFLOW -19
+#define ERR_NOT_INITIALIZED -20
+#define ERR_SAMPLERATE_UNAVAILABLE -21
+#define ERR_RESOLUTION_UNAVAILABLE -22
+#define ERR_BAUDRATE_UNAVAILABLE -23
+#define ERR_PACKET_COLLISION -24
+#define ERR_PROTOCOL -25
+#define ERR_PIN_MUX_INVALID -26
+#define ERR_UNSUPPORTED_OP -27
+#define ERR_NO_RESOURCE -28
+#define ERR_NOT_READY -29
+#define ERR_FAILURE -30
+#define ERR_WRONG_LENGTH -31
+
+#endif
diff --git a/Smol Watch Project/My Project/hal/utils/include/events.h b/Smol Watch Project/My Project/hal/utils/include/events.h
new file mode 100644
index 0000000..3ee891a
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/events.h	
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _EVENTS_H_INCLUDED
+#define _EVENTS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+/**
+ * \brief List of events. Must start with 0, be unique and follow numerical order.
+ */
+#define EVENT_IS_READY_TO_SLEEP_ID 0
+#define EVENT_PREPARE_TO_SLEEP_ID 1
+#define EVENT_WOKEN_UP_ID 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EVENTS_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/utils/include/parts.h b/Smol Watch Project/My Project/hal/utils/include/parts.h
new file mode 100644
index 0000000..df30040
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/parts.h	
@@ -0,0 +1,41 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+#include "saml22.h"
+
+#include "hri_l22.h"
+
+#endif /* ATMEL_PARTS_H */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils.h b/Smol Watch Project/My Project/hal/utils/include/utils.h
new file mode 100644
index 0000000..1cf2699
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils.h	
@@ -0,0 +1,368 @@
+/**
+ * \file
+ *
+ * \brief Different macros.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef UTILS_H_INCLUDED
+#define UTILS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_macro
+ *
+ * @{
+ */
+
+/**
+ * \brief Retrieve pointer to parent structure
+ */
+#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name)))
+
+/**
+ * \brief Retrieve array size
+ */
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg  The pragma directive as it would appear after \e \#pragma
+ *             (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if defined __GNUC__
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif defined __ICCARM__
+#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#elif defined __CC_ARM
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#endif
+
+/**
+ * \brief Flash located data macros
+ */
+#if defined __GNUC__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __ICCARM__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __CC_ARM
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#endif
+
+/**
+ * \brief Optimization
+ */
+#if defined __GNUC__
+#define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#elif defined __CC_ARM
+#define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined __ICCARM__
+#define OPTIMIZE_HIGH _Pragma("optimize=high")
+#endif
+
+/**
+ * \brief RAM located function attribute
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define RAMFUNC __ramfunc
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#endif
+
+/**
+ * \brief No-init section.
+ * Place a data object or a function in a no-init section.
+ */
+#if defined(__CC_ARM)
+#define NO_INIT(a) __attribute__((zero_init))
+#elif defined(__ICCARM__)
+#define NO_INIT(a) __no_init
+#elif defined(__GNUC__)
+#define NO_INIT(a) __attribute__((section(".no_init")))
+#endif
+
+/**
+ * \brief Set user-defined section.
+ * Place a data object or a function in a user-defined section.
+ */
+#if defined(__CC_ARM)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#elif defined(__ICCARM__)
+#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a)
+#elif defined(__GNUC__)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#endif
+
+/**
+ * \brief Define WEAK attribute.
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define WEAK __attribute__((weak))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define WEAK __weak
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define WEAK __attribute__((weak))
+#endif
+
+/**
+ * \brief Pointer to function
+ */
+typedef void (*FUNC_PTR)(void);
+
+#define LE_BYTE0(a) ((uint8_t)(a))
+#define LE_BYTE1(a) ((uint8_t)((a) >> 8))
+#define LE_BYTE2(a) ((uint8_t)((a) >> 16))
+#define LE_BYTE3(a) ((uint8_t)((a) >> 24))
+
+#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8))
+#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24))
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define clz(u) __builtin_clz(u)
+#else
+#define clz(u)                                                                                                                                                                                                                                                                                                                                                                                     \
+	(                                                                                                                                                                                                                                                                                                                                                                                              \
+	    ((u) == 0)                                                                                                                                                                                                                                                                                                                                                                                 \
+	        ? 32                                                                                                                                                                                                                                                                                                                                                                                   \
+	        : ((u) & (1ul << 31))                                                                                                                                                                                                                                                                                                                                                                  \
+	              ? 0                                                                                                                                                                                                                                                                                                                                                                              \
+	              : ((u) & (1ul << 30))                                                                                                                                                                                                                                                                                                                                                            \
+	                    ? 1                                                                                                                                                                                                                                                                                                                                                                        \
+	                    : ((u) & (1ul << 29))                                                                                                                                                                                                                                                                                                                                                      \
+	                          ? 2                                                                                                                                                                                                                                                                                                                                                                  \
+	                          : ((u) & (1ul << 28))                                                                                                                                                                                                                                                                                                                                                \
+	                                ? 3                                                                                                                                                                                                                                                                                                                                                            \
+	                                : ((u) & (1ul << 27))                                                                                                                                                                                                                                                                                                                                          \
+	                                      ? 4                                                                                                                                                                                                                                                                                                                                                      \
+	                                      : ((u) & (1ul << 26))                                                                                                                                                                                                                                                                                                                                    \
+	                                            ? 5                                                                                                                                                                                                                                                                                                                                                \
+	                                            : ((u) & (1ul << 25))                                                                                                                                                                                                                                                                                                                              \
+	                                                  ? 6                                                                                                                                                                                                                                                                                                                                          \
+	                                                  : ((u) & (1ul << 24))                                                                                                                                                                                                                                                                                                                        \
+	                                                        ? 7                                                                                                                                                                                                                                                                                                                                    \
+	                                                        : ((u) & (1ul << 23))                                                                                                                                                                                                                                                                                                                  \
+	                                                              ? 8                                                                                                                                                                                                                                                                                                                              \
+	                                                              : ((u) & (1ul << 22))                                                                                                                                                                                                                                                                                                            \
+	                                                                    ? 9                                                                                                                                                                                                                                                                                                                        \
+	                                                                    : ((u) & (1ul << 21))                                                                                                                                                                                                                                                                                                      \
+	                                                                          ? 10                                                                                                                                                                                                                                                                                                                 \
+	                                                                          : ((u) & (1ul << 20))                                                                                                                                                                                                                                                                                                \
+	                                                                                ? 11                                                                                                                                                                                                                                                                                                           \
+	                                                                                : ((u) & (1ul << 19))                                                                                                                                                                                                                                                                                          \
+	                                                                                      ? 12                                                                                                                                                                                                                                                                                                     \
+	                                                                                      : ((u) & (1ul << 18))                                                                                                                                                                                                                                                                                    \
+	                                                                                            ? 13                                                                                                                                                                                                                                                                                               \
+	                                                                                            : ((u) & (1ul << 17)) ? 14                                                                                                                                                                                                                                                                         \
+	                                                                                                                  : ((u) & (1ul << 16)) ? 15                                                                                                                                                                                                                                                   \
+	                                                                                                                                        : ((u) & (1ul << 15)) ? 16                                                                                                                                                                                                                             \
+	                                                                                                                                                              : ((u) & (1ul << 14)) ? 17                                                                                                                                                                                                       \
+	                                                                                                                                                                                    : ((u) & (1ul << 13)) ? 18                                                                                                                                                                                 \
+	                                                                                                                                                                                                          : ((u) & (1ul << 12)) ? 19                                                                                                                                                           \
+	                                                                                                                                                                                                                                : ((u)                                                                                                                                                         \
+	                                                                                                                                                                                                                                   & (1ul                                                                                                                                                      \
+	                                                                                                                                                                                                                                      << 11))                                                                                                                                                  \
+	                                                                                                                                                                                                                                      ? 20                                                                                                                                                     \
+	                                                                                                                                                                                                                                      : ((u)                                                                                                                                                   \
+	                                                                                                                                                                                                                                         & (1ul                                                                                                                                                \
+	                                                                                                                                                                                                                                            << 10))                                                                                                                                            \
+	                                                                                                                                                                                                                                            ? 21                                                                                                                                               \
+	                                                                                                                                                                                                                                            : ((u)                                                                                                                                             \
+	                                                                                                                                                                                                                                               & (1ul                                                                                                                                          \
+	                                                                                                                                                                                                                                                  << 9))                                                                                                                                       \
+	                                                                                                                                                                                                                                                  ? 22                                                                                                                                         \
+	                                                                                                                                                                                                                                                  : ((u)                                                                                                                                       \
+	                                                                                                                                                                                                                                                     & (1ul                                                                                                                                    \
+	                                                                                                                                                                                                                                                        << 8))                                                                                                                                 \
+	                                                                                                                                                                                                                                                        ? 23                                                                                                                                   \
+	                                                                                                                                                                                                                                                        : ((u) & (1ul << 7)) ? 24                                                                                                              \
+	                                                                                                                                                                                                                                                                             : ((u) & (1ul << 6)) ? 25                                                                                         \
+	                                                                                                                                                                                                                                                                                                  : ((u)                                                                                       \
+	                                                                                                                                                                                                                                                                                                     & (1ul                                                                                    \
+	                                                                                                                                                                                                                                                                                                        << 5))                                                                                 \
+	                                                                                                                                                                                                                                                                                                        ? 26                                                                                   \
+	                                                                                                                                                                                                                                                                                                        : ((u) & (1ul << 4)) ? 27                                                              \
+	                                                                                                                                                                                                                                                                                                                             : ((u) & (1ul << 3)) ? 28                                         \
+	                                                                                                                                                                                                                                                                                                                                                  : ((u) & (1ul << 2)) ? 29                    \
+	                                                                                                                                                                                                                                                                                                                                                                       : (                     \
+	                                                                                                                                                                                                                                                                                                                                                                             (u) & (1ul << 1)) \
+	                                                                                                                                                                                                                                                                                                                                                                             ? 30              \
+	                                                                                                                                                                                                                                                                                                                                                                             : 31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define ctz(u) __builtin_ctz(u)
+#else
+#define ctz(u)                                                                                                                                                                                                                                                                                                   \
+	(                                                                                                                                                                                                                                                                                                            \
+	    (u) & (1ul << 0)                                                                                                                                                                                                                                                                                         \
+	        ? 0                                                                                                                                                                                                                                                                                                  \
+	        : (u) & (1ul << 1)                                                                                                                                                                                                                                                                                   \
+	              ? 1                                                                                                                                                                                                                                                                                            \
+	              : (u) & (1ul << 2)                                                                                                                                                                                                                                                                             \
+	                    ? 2                                                                                                                                                                                                                                                                                      \
+	                    : (u) & (1ul << 3)                                                                                                                                                                                                                                                                       \
+	                          ? 3                                                                                                                                                                                                                                                                                \
+	                          : (u) & (1ul << 4)                                                                                                                                                                                                                                                                 \
+	                                ? 4                                                                                                                                                                                                                                                                          \
+	                                : (u) & (1ul << 5)                                                                                                                                                                                                                                                           \
+	                                      ? 5                                                                                                                                                                                                                                                                    \
+	                                      : (u) & (1ul << 6)                                                                                                                                                                                                                                                     \
+	                                            ? 6                                                                                                                                                                                                                                                              \
+	                                            : (u) & (1ul << 7)                                                                                                                                                                                                                                               \
+	                                                  ? 7                                                                                                                                                                                                                                                        \
+	                                                  : (u) & (1ul << 8)                                                                                                                                                                                                                                         \
+	                                                        ? 8                                                                                                                                                                                                                                                  \
+	                                                        : (u) & (1ul << 9)                                                                                                                                                                                                                                   \
+	                                                              ? 9                                                                                                                                                                                                                                            \
+	                                                              : (u) & (1ul << 10)                                                                                                                                                                                                                            \
+	                                                                    ? 10                                                                                                                                                                                                                                     \
+	                                                                    : (u) & (1ul << 11)                                                                                                                                                                                                                      \
+	                                                                          ? 11                                                                                                                                                                                                                               \
+	                                                                          : (u) & (1ul << 12)                                                                                                                                                                                                                \
+	                                                                                ? 12                                                                                                                                                                                                                         \
+	                                                                                : (u) & (1ul << 13)                                                                                                                                                                                                          \
+	                                                                                      ? 13                                                                                                                                                                                                                   \
+	                                                                                      : (u) & (1ul << 14)                                                                                                                                                                                                    \
+	                                                                                            ? 14                                                                                                                                                                                                             \
+	                                                                                            : (u) & (1ul << 15)                                                                                                                                                                                              \
+	                                                                                                  ? 15                                                                                                                                                                                                       \
+	                                                                                                  : (u) & (1ul << 16)                                                                                                                                                                                        \
+	                                                                                                        ? 16                                                                                                                                                                                                 \
+	                                                                                                        : (u) & (1ul << 17)                                                                                                                                                                                  \
+	                                                                                                              ? 17                                                                                                                                                                                           \
+	                                                                                                              : (u) & (1ul << 18)                                                                                                                                                                            \
+	                                                                                                                    ? 18                                                                                                                                                                                     \
+	                                                                                                                    : (u) & (1ul << 19) ? 19                                                                                                                                                                 \
+	                                                                                                                                        : (u) & (1ul << 20) ? 20                                                                                                                                             \
+	                                                                                                                                                            : (u) & (1ul << 21) ? 21                                                                                                                         \
+	                                                                                                                                                                                : (u) & (1ul << 22) ? 22                                                                                                     \
+	                                                                                                                                                                                                    : (u) & (1ul << 23) ? 23                                                                                 \
+	                                                                                                                                                                                                                        : (u) & (1ul << 24) ? 24                                                             \
+	                                                                                                                                                                                                                                            : (u) & (1ul << 25) ? 25                                         \
+	                                                                                                                                                                                                                                                                : (u) & (1ul << 26) ? 26                     \
+	                                                                                                                                                                                                                                                                                    : (u) & (1ul << 27) ? 27 \
+	                                                                                                                                                                                                                                                                                                        : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32)
+#endif
+/** @} */
+
+/**
+ * \brief Counts the number of bits in a mask (no more than 32 bits)
+ * \param[in] mask Mask of which to count the bits.
+ */
+#define size_of_mask(mask) (32 - clz(mask) - ctz(mask))
+
+/**
+ * \brief Retrieve the start position of bits mask (no more than 32 bits)
+ * \param[in] mask Mask of which to retrieve the start position.
+ */
+#define pos_of_mask(mask) ctz(mask)
+
+/**
+ * \brief Return division result of a/b and round up the result to the closest
+ *        number divisible by "b"
+ */
+#define round_up(a, b) (((a)-1) / (b) + 1)
+
+/**
+ * \brief Get the minimum of x and y
+ */
+#define min(x, y) ((x) > (y) ? (y) : (x))
+
+/**
+ * \brief Get the maximum of x and y
+ */
+#define max(x, y) ((x) > (y) ? (x) : (y))
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* UTILS_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_assert.h b/Smol Watch Project/My Project/hal/utils/include/utils_assert.h
new file mode 100644
index 0000000..c2328d6
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_assert.h	
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _ASSERT_H_INCLUDED
+#define _ASSERT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+#ifndef USE_SIMPLE_ASSERT
+//# define USE_SIMPLE_ASSERT
+#endif
+
+/**
+ * \brief Assert macro
+ *
+ * This macro is used to throw asserts. It can be mapped to different function
+ * based on debug level.
+ *
+ * \param[in] condition A condition to be checked;
+ *                      assert is thrown if the given condition is false
+ */
+#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__)
+
+#ifdef DEBUG
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line)                                                                             \
+	if (!(condition))                                                                                                  \
+		__asm("BKPT #0");
+#else
+#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
+#endif
+
+#else /* DEBUG */
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#else
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#endif
+
+#endif /* DEBUG */
+
+/**
+ * \brief Assert function
+ *
+ * This function is used to throw asserts.
+ *
+ * \param[in] condition A condition to be checked; assert is thrown if the given
+ *                      condition is false
+ * \param[in] file File name
+ * \param[in] line Line number
+ */
+void assert(const bool condition, const char *const file, const int line);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ASSERT_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_decrement_macro.h b/Smol Watch Project/My Project/hal/utils/include/utils_decrement_macro.h
new file mode 100644
index 0000000..2b52469
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_decrement_macro.h	
@@ -0,0 +1,309 @@
+/**
+ * \file
+ *
+ * \brief Decrement macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_DECREMENT_MACRO_H
+#define _UTILS_DECREMENT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compile time decrement, result value is entire integer literal
+ *
+ * \param[in] val - value to be decremented
+ */
+#define DEC_VALUE(val) DEC_##val
+
+// Preprocessor increment implementation
+#define DEC_256 255
+#define DEC_255 254
+#define DEC_254 253
+#define DEC_253 252
+#define DEC_252 251
+#define DEC_251 250
+#define DEC_250 249
+#define DEC_249 248
+#define DEC_248 247
+#define DEC_247 246
+#define DEC_246 245
+#define DEC_245 244
+#define DEC_244 243
+#define DEC_243 242
+#define DEC_242 241
+#define DEC_241 240
+#define DEC_240 239
+#define DEC_239 238
+#define DEC_238 237
+#define DEC_237 236
+#define DEC_236 235
+#define DEC_235 234
+#define DEC_234 233
+#define DEC_233 232
+#define DEC_232 231
+#define DEC_231 230
+#define DEC_230 229
+#define DEC_229 228
+#define DEC_228 227
+#define DEC_227 226
+#define DEC_226 225
+#define DEC_225 224
+#define DEC_224 223
+#define DEC_223 222
+#define DEC_222 221
+#define DEC_221 220
+#define DEC_220 219
+#define DEC_219 218
+#define DEC_218 217
+#define DEC_217 216
+#define DEC_216 215
+#define DEC_215 214
+#define DEC_214 213
+#define DEC_213 212
+#define DEC_212 211
+#define DEC_211 210
+#define DEC_210 209
+#define DEC_209 208
+#define DEC_208 207
+#define DEC_207 206
+#define DEC_206 205
+#define DEC_205 204
+#define DEC_204 203
+#define DEC_203 202
+#define DEC_202 201
+#define DEC_201 200
+#define DEC_200 199
+#define DEC_199 198
+#define DEC_198 197
+#define DEC_197 196
+#define DEC_196 195
+#define DEC_195 194
+#define DEC_194 193
+#define DEC_193 192
+#define DEC_192 191
+#define DEC_191 190
+#define DEC_190 189
+#define DEC_189 188
+#define DEC_188 187
+#define DEC_187 186
+#define DEC_186 185
+#define DEC_185 184
+#define DEC_184 183
+#define DEC_183 182
+#define DEC_182 181
+#define DEC_181 180
+#define DEC_180 179
+#define DEC_179 178
+#define DEC_178 177
+#define DEC_177 176
+#define DEC_176 175
+#define DEC_175 174
+#define DEC_174 173
+#define DEC_173 172
+#define DEC_172 171
+#define DEC_171 170
+#define DEC_170 169
+#define DEC_169 168
+#define DEC_168 167
+#define DEC_167 166
+#define DEC_166 165
+#define DEC_165 164
+#define DEC_164 163
+#define DEC_163 162
+#define DEC_162 161
+#define DEC_161 160
+#define DEC_160 159
+#define DEC_159 158
+#define DEC_158 157
+#define DEC_157 156
+#define DEC_156 155
+#define DEC_155 154
+#define DEC_154 153
+#define DEC_153 152
+#define DEC_152 151
+#define DEC_151 150
+#define DEC_150 149
+#define DEC_149 148
+#define DEC_148 147
+#define DEC_147 146
+#define DEC_146 145
+#define DEC_145 144
+#define DEC_144 143
+#define DEC_143 142
+#define DEC_142 141
+#define DEC_141 140
+#define DEC_140 139
+#define DEC_139 138
+#define DEC_138 137
+#define DEC_137 136
+#define DEC_136 135
+#define DEC_135 134
+#define DEC_134 133
+#define DEC_133 132
+#define DEC_132 131
+#define DEC_131 130
+#define DEC_130 129
+#define DEC_129 128
+#define DEC_128 127
+#define DEC_127 126
+#define DEC_126 125
+#define DEC_125 124
+#define DEC_124 123
+#define DEC_123 122
+#define DEC_122 121
+#define DEC_121 120
+#define DEC_120 119
+#define DEC_119 118
+#define DEC_118 117
+#define DEC_117 116
+#define DEC_116 115
+#define DEC_115 114
+#define DEC_114 113
+#define DEC_113 112
+#define DEC_112 111
+#define DEC_111 110
+#define DEC_110 109
+#define DEC_109 108
+#define DEC_108 107
+#define DEC_107 106
+#define DEC_106 105
+#define DEC_105 104
+#define DEC_104 103
+#define DEC_103 102
+#define DEC_102 101
+#define DEC_101 100
+#define DEC_100 99
+#define DEC_99 98
+#define DEC_98 97
+#define DEC_97 96
+#define DEC_96 95
+#define DEC_95 94
+#define DEC_94 93
+#define DEC_93 92
+#define DEC_92 91
+#define DEC_91 90
+#define DEC_90 89
+#define DEC_89 88
+#define DEC_88 87
+#define DEC_87 86
+#define DEC_86 85
+#define DEC_85 84
+#define DEC_84 83
+#define DEC_83 82
+#define DEC_82 81
+#define DEC_81 80
+#define DEC_80 79
+#define DEC_79 78
+#define DEC_78 77
+#define DEC_77 76
+#define DEC_76 75
+#define DEC_75 74
+#define DEC_74 73
+#define DEC_73 72
+#define DEC_72 71
+#define DEC_71 70
+#define DEC_70 69
+#define DEC_69 68
+#define DEC_68 67
+#define DEC_67 66
+#define DEC_66 65
+#define DEC_65 64
+#define DEC_64 63
+#define DEC_63 62
+#define DEC_62 61
+#define DEC_61 60
+#define DEC_60 59
+#define DEC_59 58
+#define DEC_58 57
+#define DEC_57 56
+#define DEC_56 55
+#define DEC_55 54
+#define DEC_54 53
+#define DEC_53 52
+#define DEC_52 51
+#define DEC_51 50
+#define DEC_50 49
+#define DEC_49 48
+#define DEC_48 47
+#define DEC_47 46
+#define DEC_46 45
+#define DEC_45 44
+#define DEC_44 43
+#define DEC_43 42
+#define DEC_42 41
+#define DEC_41 40
+#define DEC_40 39
+#define DEC_39 38
+#define DEC_38 37
+#define DEC_37 36
+#define DEC_36 35
+#define DEC_35 34
+#define DEC_34 33
+#define DEC_33 32
+#define DEC_32 31
+#define DEC_31 30
+#define DEC_30 29
+#define DEC_29 28
+#define DEC_28 27
+#define DEC_27 26
+#define DEC_26 25
+#define DEC_25 24
+#define DEC_24 23
+#define DEC_23 22
+#define DEC_22 21
+#define DEC_21 20
+#define DEC_20 19
+#define DEC_19 18
+#define DEC_18 17
+#define DEC_17 16
+#define DEC_16 15
+#define DEC_15 14
+#define DEC_14 13
+#define DEC_13 12
+#define DEC_12 11
+#define DEC_11 10
+#define DEC_10 9
+#define DEC_9 8
+#define DEC_8 7
+#define DEC_7 6
+#define DEC_6 5
+#define DEC_5 4
+#define DEC_4 3
+#define DEC_3 2
+#define DEC_2 1
+#define DEC_1 0
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_DECREMENT_MACRO_H */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_event.h b/Smol Watch Project/My Project/hal/utils/include/utils_event.h
new file mode 100644
index 0000000..13067c4
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_event.h	
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_EVENT_H_INCLUDED
+#define _UTILS_EVENT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils.h>
+#include <utils_list.h>
+#include <events.h>
+
+/**
+ * \brief The maximum amount of events
+ */
+#define EVENT_MAX_AMOUNT 8
+
+/**
+ * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the
+ *        closest number divisible by 8.
+ */
+#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8))
+
+/**
+ * \brief The type of event ID. IDs should start with 0 and be in numerical order.
+ */
+typedef uint8_t event_id_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef uintptr_t event_data_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef void (*event_cb_t)(event_id_t id, event_data_t data);
+
+/**
+ * \brief Event structure
+ */
+struct event {
+	struct list_element elem;                  /*! The pointer to next event */
+	uint8_t             mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */
+	event_cb_t          cb;                    /*! Callback to be called when an event occurs */
+};
+
+/**
+ * \brief Subscribe to event
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to subscribe to
+ * \param[in] cb The callback function to call when the given event occurs
+ *
+ * \return The status of subscription
+ */
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb);
+
+/**
+ * \brief Remove event from subscription
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to remove subscription from
+ *
+ * \return The status of subscription removing
+ */
+int32_t event_unsubscribe(struct event *const event, const event_id_t id);
+
+/**
+ * \brief Post event
+ *
+ * \param[in] id The event ID to post
+ * \param[in] data The event data to be passed to event subscribers
+ */
+void event_post(const event_id_t id, const event_data_t data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UTILS_EVENT_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_increment_macro.h b/Smol Watch Project/My Project/hal/utils/include/utils_increment_macro.h
new file mode 100644
index 0000000..464c6cb
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_increment_macro.h	
@@ -0,0 +1,308 @@
+/**
+ * \file
+ *
+ * \brief Increment macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_INCREMENT_MACRO_H
+#define _UTILS_INCREMENT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compile time increment, result value is entire integer literal
+ *
+ * \param[in] val - value to be incremented (254 max)
+ */
+#define INC_VALUE(val) SP_INC_##val
+
+// Preprocessor increment implementation
+#define SP_INC_0 1
+#define SP_INC_1 2
+#define SP_INC_2 3
+#define SP_INC_3 4
+#define SP_INC_4 5
+#define SP_INC_5 6
+#define SP_INC_6 7
+#define SP_INC_7 8
+#define SP_INC_8 9
+#define SP_INC_9 10
+#define SP_INC_10 11
+#define SP_INC_11 12
+#define SP_INC_12 13
+#define SP_INC_13 14
+#define SP_INC_14 15
+#define SP_INC_15 16
+#define SP_INC_16 17
+#define SP_INC_17 18
+#define SP_INC_18 19
+#define SP_INC_19 20
+#define SP_INC_20 21
+#define SP_INC_21 22
+#define SP_INC_22 23
+#define SP_INC_23 24
+#define SP_INC_24 25
+#define SP_INC_25 26
+#define SP_INC_26 27
+#define SP_INC_27 28
+#define SP_INC_28 29
+#define SP_INC_29 30
+#define SP_INC_30 31
+#define SP_INC_31 32
+#define SP_INC_32 33
+#define SP_INC_33 34
+#define SP_INC_34 35
+#define SP_INC_35 36
+#define SP_INC_36 37
+#define SP_INC_37 38
+#define SP_INC_38 39
+#define SP_INC_39 40
+#define SP_INC_40 41
+#define SP_INC_41 42
+#define SP_INC_42 43
+#define SP_INC_43 44
+#define SP_INC_44 45
+#define SP_INC_45 46
+#define SP_INC_46 47
+#define SP_INC_47 48
+#define SP_INC_48 49
+#define SP_INC_49 50
+#define SP_INC_50 51
+#define SP_INC_51 52
+#define SP_INC_52 53
+#define SP_INC_53 54
+#define SP_INC_54 55
+#define SP_INC_55 56
+#define SP_INC_56 57
+#define SP_INC_57 58
+#define SP_INC_58 59
+#define SP_INC_59 60
+#define SP_INC_60 61
+#define SP_INC_61 62
+#define SP_INC_62 63
+#define SP_INC_63 64
+#define SP_INC_64 65
+#define SP_INC_65 66
+#define SP_INC_66 67
+#define SP_INC_67 68
+#define SP_INC_68 69
+#define SP_INC_69 70
+#define SP_INC_70 71
+#define SP_INC_71 72
+#define SP_INC_72 73
+#define SP_INC_73 74
+#define SP_INC_74 75
+#define SP_INC_75 76
+#define SP_INC_76 77
+#define SP_INC_77 78
+#define SP_INC_78 79
+#define SP_INC_79 80
+#define SP_INC_80 81
+#define SP_INC_81 82
+#define SP_INC_82 83
+#define SP_INC_83 84
+#define SP_INC_84 85
+#define SP_INC_85 86
+#define SP_INC_86 87
+#define SP_INC_87 88
+#define SP_INC_88 89
+#define SP_INC_89 90
+#define SP_INC_90 91
+#define SP_INC_91 92
+#define SP_INC_92 93
+#define SP_INC_93 94
+#define SP_INC_94 95
+#define SP_INC_95 96
+#define SP_INC_96 97
+#define SP_INC_97 98
+#define SP_INC_98 99
+#define SP_INC_99 100
+#define SP_INC_100 101
+#define SP_INC_101 102
+#define SP_INC_102 103
+#define SP_INC_103 104
+#define SP_INC_104 105
+#define SP_INC_105 106
+#define SP_INC_106 107
+#define SP_INC_107 108
+#define SP_INC_108 109
+#define SP_INC_109 110
+#define SP_INC_110 111
+#define SP_INC_111 112
+#define SP_INC_112 113
+#define SP_INC_113 114
+#define SP_INC_114 115
+#define SP_INC_115 116
+#define SP_INC_116 117
+#define SP_INC_117 118
+#define SP_INC_118 119
+#define SP_INC_119 120
+#define SP_INC_120 121
+#define SP_INC_121 122
+#define SP_INC_122 123
+#define SP_INC_123 124
+#define SP_INC_124 125
+#define SP_INC_125 126
+#define SP_INC_126 127
+#define SP_INC_127 128
+#define SP_INC_128 129
+#define SP_INC_129 130
+#define SP_INC_130 131
+#define SP_INC_131 132
+#define SP_INC_132 133
+#define SP_INC_133 134
+#define SP_INC_134 135
+#define SP_INC_135 136
+#define SP_INC_136 137
+#define SP_INC_137 138
+#define SP_INC_138 139
+#define SP_INC_139 140
+#define SP_INC_140 141
+#define SP_INC_141 142
+#define SP_INC_142 143
+#define SP_INC_143 144
+#define SP_INC_144 145
+#define SP_INC_145 146
+#define SP_INC_146 147
+#define SP_INC_147 148
+#define SP_INC_148 149
+#define SP_INC_149 150
+#define SP_INC_150 151
+#define SP_INC_151 152
+#define SP_INC_152 153
+#define SP_INC_153 154
+#define SP_INC_154 155
+#define SP_INC_155 156
+#define SP_INC_156 157
+#define SP_INC_157 158
+#define SP_INC_158 159
+#define SP_INC_159 160
+#define SP_INC_160 161
+#define SP_INC_161 162
+#define SP_INC_162 163
+#define SP_INC_163 164
+#define SP_INC_164 165
+#define SP_INC_165 166
+#define SP_INC_166 167
+#define SP_INC_167 168
+#define SP_INC_168 169
+#define SP_INC_169 170
+#define SP_INC_170 171
+#define SP_INC_171 172
+#define SP_INC_172 173
+#define SP_INC_173 174
+#define SP_INC_174 175
+#define SP_INC_175 176
+#define SP_INC_176 177
+#define SP_INC_177 178
+#define SP_INC_178 179
+#define SP_INC_179 180
+#define SP_INC_180 181
+#define SP_INC_181 182
+#define SP_INC_182 183
+#define SP_INC_183 184
+#define SP_INC_184 185
+#define SP_INC_185 186
+#define SP_INC_186 187
+#define SP_INC_187 188
+#define SP_INC_188 189
+#define SP_INC_189 190
+#define SP_INC_190 191
+#define SP_INC_191 192
+#define SP_INC_192 193
+#define SP_INC_193 194
+#define SP_INC_194 195
+#define SP_INC_195 196
+#define SP_INC_196 197
+#define SP_INC_197 198
+#define SP_INC_198 199
+#define SP_INC_199 200
+#define SP_INC_200 201
+#define SP_INC_201 202
+#define SP_INC_202 203
+#define SP_INC_203 204
+#define SP_INC_204 205
+#define SP_INC_205 206
+#define SP_INC_206 207
+#define SP_INC_207 208
+#define SP_INC_208 209
+#define SP_INC_209 210
+#define SP_INC_210 211
+#define SP_INC_211 212
+#define SP_INC_212 213
+#define SP_INC_213 214
+#define SP_INC_214 215
+#define SP_INC_215 216
+#define SP_INC_216 217
+#define SP_INC_217 218
+#define SP_INC_218 219
+#define SP_INC_219 220
+#define SP_INC_220 221
+#define SP_INC_221 222
+#define SP_INC_222 223
+#define SP_INC_223 224
+#define SP_INC_224 225
+#define SP_INC_225 226
+#define SP_INC_226 227
+#define SP_INC_227 228
+#define SP_INC_228 229
+#define SP_INC_229 230
+#define SP_INC_230 231
+#define SP_INC_231 232
+#define SP_INC_232 233
+#define SP_INC_233 234
+#define SP_INC_234 235
+#define SP_INC_235 236
+#define SP_INC_236 237
+#define SP_INC_237 238
+#define SP_INC_238 239
+#define SP_INC_239 240
+#define SP_INC_240 241
+#define SP_INC_241 242
+#define SP_INC_242 243
+#define SP_INC_243 244
+#define SP_INC_244 245
+#define SP_INC_245 246
+#define SP_INC_246 247
+#define SP_INC_247 248
+#define SP_INC_248 249
+#define SP_INC_249 250
+#define SP_INC_250 251
+#define SP_INC_251 252
+#define SP_INC_252 253
+#define SP_INC_253 254
+#define SP_INC_254 255
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_INCREMENT_MACRO_H */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_list.h b/Smol Watch Project/My Project/hal/utils/include/utils_list.h
new file mode 100644
index 0000000..977e8cc
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_list.h	
@@ -0,0 +1,164 @@
+/**
+ * \file
+ *
+ * \brief List declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_LIST_H_INCLUDED
+#define _UTILS_LIST_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_list
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+/**
+ * \brief List element type
+ */
+struct list_element {
+	struct list_element *next;
+};
+
+/**
+ * \brief List head type
+ */
+struct list_descriptor {
+	struct list_element *head;
+};
+
+/**
+ * \brief Reset list
+ *
+ * \param[in] list The pointer to a list descriptor
+ */
+static inline void list_reset(struct list_descriptor *const list)
+{
+	list->head = NULL;
+}
+
+/**
+ * \brief Retrieve list head
+ *
+ * \param[in] list The pointer to a list descriptor
+ *
+ * \return A pointer to the head of the given list or NULL if the list is
+ * empty
+ */
+static inline void *list_get_head(const struct list_descriptor *const list)
+{
+	return (void *)list->head;
+}
+
+/**
+ * \brief Retrieve next list head
+ *
+ * \param[in] list The pointer to a list element
+ *
+ * \return A pointer to the next list element or NULL if there is not next
+ * element
+ */
+static inline void *list_get_next_element(const void *const element)
+{
+	return element ? ((struct list_element *)element)->next : NULL;
+}
+
+/**
+ * \brief Insert an element as list head
+ *
+ * \param[in] list The pointer to a list element
+ * \param[in] element An element to insert to the given list
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Insert an element after the given list element
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_after(void *const after, void *const element);
+
+/**
+ * \brief Insert an element at list end
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Check whether an element belongs to a list
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to check
+ *
+ * \return The result of checking
+ * \retval true If the given element is an element of the given list
+ * \retval false Otherwise
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element);
+
+/**
+ * \brief Removes list head
+ *
+ * This function removes the list head and sets the next element after the list
+ * head as a new list head.
+ *
+ * \param[in] list The pointer to a list
+ *
+ * \return The pointer to the new list head of NULL if the list head is NULL
+ */
+void *list_remove_head(struct list_descriptor *const list);
+
+/**
+ * \brief Removes the list element
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to remove
+ *
+ * \return The result of element removing
+ * \retval true The given element is removed from the given list
+ * \retval false The given element is not an element of the given list
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_LIST_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_recursion_macro.h b/Smol Watch Project/My Project/hal/utils/include/utils_recursion_macro.h
new file mode 100644
index 0000000..294314c
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_recursion_macro.h	
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Recursion macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_RECURSION_MACRO_H
+#define _UTILS_RECURSION_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Macro recursion
+ *
+ * \param[in] macro Macro to be repeated recursively
+ * \param[in] arg A recursive threshold, building on this to decline by times
+ *                defined with parameter n
+ * \param[in] n The number of repetitious calls to macro
+ */
+#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n)
+
+/*
+ * \brief Second level is needed to get integer literal from "n" if it is
+ *        defined as macro
+ */
+#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg)
+
+#define RECURSION0(macro, arg)
+#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0)
+#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1)
+#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2)
+#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3)
+#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4)
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <utils_decrement_macro.h>
+#endif /* _UTILS_RECURSION_MACRO_H */
diff --git a/Smol Watch Project/My Project/hal/utils/include/utils_repeat_macro.h b/Smol Watch Project/My Project/hal/utils/include/utils_repeat_macro.h
new file mode 100644
index 0000000..89e6f52
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/include/utils_repeat_macro.h	
@@ -0,0 +1,322 @@
+/**
+ * \file
+ *
+ * \brief Repeat macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_REPEAT_MACRO_H
+#define _UTILS_REPEAT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Sequently repeates specified macro for n times (255 max).
+ *
+ * Specified macro shall have two arguments:  macro(arg, i)
+ *   arg - user defined argument, which have the same value for all iterations.
+ *   i - iteration number; numbering begins from zero and increments on each
+ *   iteration.
+ *
+ * \param[in] macro - macro to be repeated
+ * \param[in] arg - user defined argument for repeated macro
+ * \param[in] n - total number of iterations (255 max)
+ */
+#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n)
+
+/*
+ * \brief Second level is needed to get integer literal from "n" if it is
+ *        defined as macro
+ */
+#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0)
+
+#define REPEAT1(macro, arg, n) macro(arg, n)
+#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n))
+#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n))
+#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n))
+#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n))
+#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n))
+#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n))
+#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n))
+#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n))
+#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n))
+#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n))
+#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n))
+#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n))
+#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n))
+#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n))
+#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n))
+#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n))
+#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n))
+#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n))
+#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n))
+#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n))
+#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n))
+#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n))
+#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n))
+#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n))
+#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n))
+#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n))
+#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n))
+#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n))
+#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n))
+#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n))
+#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n))
+#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n))
+#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n))
+#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n))
+#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n))
+#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n))
+#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n))
+#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n))
+#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n))
+#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n))
+#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n))
+#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n))
+#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n))
+#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n))
+#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n))
+#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n))
+#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n))
+#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n))
+#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n))
+#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n))
+#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n))
+#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n))
+#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n))
+#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n))
+#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n))
+#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n))
+#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n))
+#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n))
+#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n))
+#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n))
+#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n))
+#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n))
+#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n))
+#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n))
+#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n))
+#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n))
+#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n))
+#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n))
+#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n))
+#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n))
+#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n))
+#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n))
+#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n))
+#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n))
+#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n))
+#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n))
+#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n))
+#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n))
+#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n))
+#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n))
+#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n))
+#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n))
+#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n))
+#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n))
+#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n))
+#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n))
+#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n))
+#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n))
+#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n))
+#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n))
+#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n))
+#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n))
+#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n))
+#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n))
+#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n))
+#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n))
+#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n))
+#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n))
+#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n))
+#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n))
+#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n))
+#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n))
+#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n))
+#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n))
+#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n))
+#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n))
+#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n))
+#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n))
+#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n))
+#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n))
+#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n))
+#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n))
+#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n))
+#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n))
+#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n))
+#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n))
+#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n))
+#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n))
+#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n))
+#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n))
+#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n))
+#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n))
+#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n))
+#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n))
+#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n))
+#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n))
+#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n))
+#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n))
+#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n))
+#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n))
+#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n))
+#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n))
+#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n))
+#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n))
+#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n))
+#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n))
+#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n))
+#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n))
+#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n))
+#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n))
+#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n))
+#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n))
+#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n))
+#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n))
+#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n))
+#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n))
+#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n))
+#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n))
+#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n))
+#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n))
+#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n))
+#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n))
+#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n))
+#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n))
+#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n))
+#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n))
+#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n))
+#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n))
+#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n))
+#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n))
+#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n))
+#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n))
+#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n))
+#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n))
+#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n))
+#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n))
+#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n))
+#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n))
+#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n))
+#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n))
+#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n))
+#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n))
+#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n))
+#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n))
+#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n))
+#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n))
+#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n))
+#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n))
+#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n))
+#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n))
+#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n))
+#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n))
+#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n))
+#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n))
+#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n))
+#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n))
+#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n))
+#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n))
+#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n))
+#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n))
+#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n))
+#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n))
+#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n))
+#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n))
+#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n))
+#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n))
+#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n))
+#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n))
+#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n))
+#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n))
+#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n))
+#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n))
+#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n))
+#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n))
+#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n))
+#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n))
+#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n))
+#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n))
+#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n))
+#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n))
+#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n))
+#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n))
+#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n))
+#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n))
+#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n))
+#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n))
+#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n))
+#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n))
+#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n))
+#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n))
+#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n))
+#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n))
+#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n))
+#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n))
+#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n))
+#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n))
+#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n))
+#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n))
+#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n))
+#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n))
+#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n))
+#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n))
+#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n))
+#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n))
+#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n))
+#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n))
+#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n))
+#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n))
+#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n))
+#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n))
+#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n))
+#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n))
+#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n))
+#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n))
+#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n))
+#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n))
+#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n))
+#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n))
+#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n))
+#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n))
+#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n))
+#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n))
+#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n))
+#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <utils_increment_macro.h>
+#endif /* _UTILS_REPEAT_MACRO_H */
diff --git a/Smol Watch Project/My Project/hal/utils/src/utils_assert.c b/Smol Watch Project/My Project/hal/utils/src/utils_assert.c
new file mode 100644
index 0000000..b376c97
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/src/utils_assert.c	
@@ -0,0 +1,46 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+	if (!(condition)) {
+		__asm("BKPT #0");
+	}
+	(void)file;
+	(void)line;
+}
diff --git a/Smol Watch Project/My Project/hal/utils/src/utils_event.c b/Smol Watch Project/My Project/hal/utils/src/utils_event.c
new file mode 100644
index 0000000..d1af9d0
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/src/utils_event.c	
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Events implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_event.h>
+#include <utils_assert.h>
+#include <string.h>
+
+#define EVENT_WORD_BITS (sizeof(event_word_t) * 8)
+
+static struct list_descriptor events;
+static uint8_t                subscribed[EVENT_MASK_SIZE];
+
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t position = id >> 3;
+	const uint8_t mask     = 1 << (id & 0x7);
+
+	ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+
+	if (event->mask[position] & mask) {
+		return ERR_NO_CHANGE; /* Already subscribed */
+	}
+
+	if (!is_list_element(&events, event)) {
+		memset(event->mask, 0, EVENT_MASK_SIZE);
+		list_insert_as_head(&events, event);
+	}
+	event->cb = cb;
+	event->mask[position] |= mask;
+
+	subscribed[position] |= mask;
+
+	return ERR_NONE;
+}
+
+int32_t event_unsubscribe(struct event *const event, const event_id_t id)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+	uint8_t             i;
+
+	ASSERT(event && (id < EVENT_MAX_AMOUNT));
+
+	if (!(event->mask[position] & mask)) {
+		return ERR_NO_CHANGE; /* Already unsubscribed */
+	}
+
+	event->mask[position] &= ~mask;
+
+	/* Check if there are more subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			break;
+		}
+	}
+	if (!current) {
+		subscribed[position] &= ~mask;
+	}
+
+	/* Remove event from the list. Can be unsave, document it! */
+	for (i = 0; i < ARRAY_SIZE(event->mask); i++) {
+		if (event->mask[i]) {
+			return ERR_NONE;
+		}
+	}
+	list_delete_element(&events, event);
+
+	return ERR_NONE;
+}
+
+void event_post(const event_id_t id, const event_data_t data)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+
+	ASSERT((id < EVENT_MAX_AMOUNT));
+
+	if (!(subscribed[position] & mask)) {
+		return; /* No subscribers */
+	}
+
+	/* Find all subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			current->cb(id, data);
+		}
+	}
+}
diff --git a/Smol Watch Project/My Project/hal/utils/src/utils_list.c b/Smol Watch Project/My Project/hal/utils/src/utils_list.c
new file mode 100644
index 0000000..4006a01
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/src/utils_list.c	
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief List functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_list.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Check whether element belongs to list
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element)
+{
+	struct list_element *it;
+	for (it = list->head; it; it = it->next) {
+		if (it == element) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * \brief Insert an element as list head
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element)
+{
+	ASSERT(!is_list_element(list, element));
+
+	((struct list_element *)element)->next = list->head;
+	list->head                             = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element after the given list element
+ */
+void list_insert_after(void *const after, void *const element)
+{
+	((struct list_element *)element)->next = ((struct list_element *)after)->next;
+	((struct list_element *)after)->next   = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element at list end
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element)
+{
+	struct list_element *it = list->head;
+
+	ASSERT(!is_list_element(list, element));
+
+	if (!list->head) {
+		list->head                             = (struct list_element *)element;
+		((struct list_element *)element)->next = NULL;
+		return;
+	}
+
+	while (it->next) {
+		it = it->next;
+	}
+	it->next                               = (struct list_element *)element;
+	((struct list_element *)element)->next = NULL;
+}
+
+/**
+ * \brief Removes list head
+ */
+void *list_remove_head(struct list_descriptor *const list)
+{
+	if (list->head) {
+		struct list_element *tmp = list->head;
+
+		list->head = list->head->next;
+		return (void *)tmp;
+	}
+
+	return NULL;
+}
+
+/**
+ * \brief Removes list element
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element)
+{
+	if (!element) {
+		return false;
+	}
+
+	if (list->head == element) {
+		list->head = list->head->next;
+		return true;
+	} else {
+		struct list_element *it = list->head;
+
+		while (it && it->next != element) {
+			it = it->next;
+		}
+		if (it) {
+			it->next = ((struct list_element *)element)->next;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+//@}
diff --git a/Smol Watch Project/My Project/hal/utils/src/utils_syscalls.c b/Smol Watch Project/My Project/hal/utils/src/utils_syscalls.c
new file mode 100644
index 0000000..79e2f1f
--- /dev/null
+++ b/Smol Watch Project/My Project/hal/utils/src/utils_syscalls.c	
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int     link(char *old, char *_new);
+extern int     _close(int file);
+extern int     _fstat(int file, struct stat *st);
+extern int     _isatty(int file);
+extern int     _lseek(int file, int ptr, int dir);
+extern void    _exit(int status);
+extern void    _kill(int pid, int sig);
+extern int     _getpid(void);
+
+/**
+ * \brief Replacement of C library of _sbrk
+ */
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *       prev_heap;
+
+	if (heap == NULL) {
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+
+	heap += incr;
+
+	return (caddr_t)prev_heap;
+}
+
+/**
+ * \brief Replacement of C library of link
+ */
+extern int link(char *old, char *_new)
+{
+	(void)old, (void)_new;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _close
+ */
+extern int _close(int file)
+{
+	(void)file;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _fstat
+ */
+extern int _fstat(int file, struct stat *st)
+{
+	(void)file;
+	st->st_mode = S_IFCHR;
+
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _isatty
+ */
+extern int _isatty(int file)
+{
+	(void)file;
+	return 1;
+}
+
+/**
+ * \brief Replacement of C library of _lseek
+ */
+extern int _lseek(int file, int ptr, int dir)
+{
+	(void)file, (void)ptr, (void)dir;
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _exit
+ */
+extern void _exit(int status)
+{
+	printf("Exiting with status %d.\n", status);
+
+	for (;;)
+		;
+}
+
+/**
+ * \brief Replacement of C library of _kill
+ */
+extern void _kill(int pid, int sig)
+{
+	(void)pid, (void)sig;
+	return;
+}
+
+/**
+ * \brief Replacement of C library of _getpid
+ */
+extern int _getpid(void)
+{
+	return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/Smol Watch Project/My Project/hpl/adc/hpl_adc.c b/Smol Watch Project/My Project/hpl/adc/hpl_adc.c
new file mode 100644
index 0000000..032302c
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/adc/hpl_adc.c	
@@ -0,0 +1,769 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Analog Digital Converter
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_adc_async.h>
+#include <hpl_adc_dma.h>
+#include <hpl_adc_sync.h>
+#include <utils_assert.h>
+#include <utils_repeat_macro.h>
+#include <hpl_adc_config.h>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 0
+#endif
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 0
+#endif
+
+/**
+ * \brief Macro is used to fill ADC configuration structure based on its number
+ *
+ * \param[in] n The number of structures
+ */
+#define ADC_CONFIGURATION(n)                                                                                           \
+	{                                                                                                                  \
+		(n),                                                                                                           \
+		    (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos), \
+		    ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER),                                                             \
+		    (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL),           \
+		    (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos)                                                       \
+		        | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos)                                                   \
+		        | (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos),                                                  \
+		    ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG) | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS),                 \
+		    ADC_CTRLC_WINMODE(CONF_ADC_##n##_WINMODE) | ADC_CTRLC_RESSEL(CONF_ADC_##n##_RESSEL)                        \
+		        | (CONF_ADC_##n##_CORREN << ADC_CTRLC_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLC_FREERUN_Pos)  \
+		        | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLC_LEFTADJ_Pos)                                                    \
+		        | (CONF_ADC_##n##_DIFFMODE << ADC_CTRLC_DIFFMODE_Pos),                                                 \
+		    ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM),               \
+		    (CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN),       \
+		    ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT),                              \
+		    ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR),      \
+		    CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos, ADC_SEQCTRL_SEQEN(CONF_ADC_##n##_SEQEN),                  \
+	}
+
+/**
+ * \brief ADC configuration
+ */
+struct adc_configuration {
+	uint8_t                  number;
+	hri_adc_ctrla_reg_t      ctrl_a;
+	hri_adc_ctrlb_reg_t      ctrl_b;
+	hri_adc_refctrl_reg_t    ref_ctrl;
+	hri_adc_evctrl_reg_t     ev_ctrl;
+	hri_adc_inputctrl_reg_t  input_ctrl;
+	hri_adc_ctrlc_reg_t      ctrl_c;
+	hri_adc_avgctrl_reg_t    avg_ctrl;
+	hri_adc_sampctrl_reg_t   samp_ctrl;
+	hri_adc_winlt_reg_t      win_lt;
+	hri_adc_winut_reg_t      win_ut;
+	hri_adc_gaincorr_reg_t   gain_corr;
+	hri_adc_offsetcorr_reg_t offset_corr;
+	hri_adc_dbgctrl_reg_t    dbg_ctrl;
+	hri_adc_seqctrl_reg_t    seq_ctrl;
+};
+
+#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE)
+
+/**
+ * \brief Array of ADC configurations
+ */
+static const struct adc_configuration _adcs[] = {
+#if CONF_ADC_0_ENABLE == 1
+    ADC_CONFIGURATION(0),
+#endif
+#if CONF_ADC_1_ENABLE == 1
+    ADC_CONFIGURATION(1),
+#endif
+};
+
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference);
+
+/**
+ * \brief Retrieve ordinal number of the given adc hardware instance
+ */
+static uint8_t _adc_get_hardware_index(const void *const hw)
+{
+
+	(void)hw;
+	return 0;
+}
+
+/** \brief Return the pointer to register settings of specific ADC
+ *  \param[in] hw_addr The hardware register base address.
+ *  \return Pointer to register settings of specific ADC.
+ */
+static uint8_t _adc_get_regs(const uint32_t hw_addr)
+{
+	uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
+	uint8_t i;
+
+	for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
+		if (_adcs[i].number == n) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return 0;
+}
+
+/**
+ * \brief Retrieve IRQ number for the given hardware instance
+ */
+static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
+{
+
+	(void)device;
+	return ADC_IRQn;
+}
+
+/**
+ * \brief Init irq param with the given afec hardware instance
+ */
+static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
+{
+}
+
+/**
+ * \brief Initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] i The number of hardware instance
+ */
+static int32_t _adc_init(void *const hw, const uint8_t i)
+{
+	uint16_t calib_reg = 0;
+	calib_reg          = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC_FUSES_BIASREFBUF_ADDR >> ADC_FUSES_BIASREFBUF_Pos))
+	            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC_FUSES_BIASCOMP_ADDR >> ADC_FUSES_BIASCOMP_Pos));
+
+	ASSERT(hw == ADC);
+
+	if (!hri_adc_is_syncing(hw, ADC_SYNCBUSY_SWRST)) {
+		if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) {
+			hri_adc_clear_CTRLA_ENABLE_bit(hw);
+			hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_ENABLE);
+		}
+		hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST);
+	}
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+
+	hri_adc_write_CALIB_reg(hw, calib_reg);
+	hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
+	hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
+	hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
+	hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
+	hri_adc_write_CTRLC_reg(hw, _adcs[i].ctrl_c);
+	hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
+	hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
+	hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
+	hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
+	hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
+	hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
+	hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
+	hri_adc_write_SEQCTRL_reg(hw, _adcs[i].seq_ctrl);
+	hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _adc_deinit(void *hw)
+{
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
+	if (init_status) {
+		return init_status;
+	}
+	device->hw = hw;
+	_adc_init_irq_param(hw, device);
+	NVIC_DisableIRQ(_adc_get_irq_num(device));
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
+	NVIC_EnableIRQ(_adc_get_irq_num(device));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_async_deinit(struct _adc_async_device *const device)
+{
+	NVIC_DisableIRQ(_adc_get_irq_num(device));
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
+
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Return address of ADC DMA source
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device)
+{
+	return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg);
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device)
+{
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_async_convert(struct _adc_async_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input source
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state)
+{
+	(void)channel;
+
+	void *const hw = device->hw;
+
+	if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
+		hri_adc_write_INTEN_WINMON_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
+		hri_adc_write_INTEN_OVERRUN_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
+		hri_adc_write_INTEN_RESRDY_bit(hw, state);
+	}
+}
+
+/**
+ * \brief Retrieve ADC sync helper functions
+ */
+void *_adc_get_adc_sync(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Retrieve ADC async helper functions
+ */
+void *_adc_get_adc_async(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Set ADC reference source
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] reference The reference to set
+ */
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference)
+{
+	bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
+
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_write_REFCTRL_REFSEL_bf(hw, reference);
+
+	if (enabled) {
+		hri_adc_set_CTRLA_ENABLE_bit(hw);
+	}
+}
diff --git a/Smol Watch Project/My Project/hpl/adc/hpl_adc_base.h b/Smol Watch Project/My Project/hpl/adc/hpl_adc_base.h
new file mode 100644
index 0000000..e9b9528
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/adc/hpl_adc_base.h	
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_ADC_H_INCLUDED
+#define _HPL_ADC_ADC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+#include <hpl_adc_async.h>
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve ADC helper functions
+ *
+ * \return A pointer to set of ADC helper functions
+ */
+void *_adc_get_adc_sync(void);
+void *_adc_get_adc_async(void);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_USART_UART_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/core/hpl_core_m0plus_base.c b/Smol Watch Project/My Project/hpl/core/hpl_core_m0plus_base.c
new file mode 100644
index 0000000..1d32300
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/core/hpl_core_m0plus_base.c	
@@ -0,0 +1,200 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_core.h>
+#include <hpl_irq.h>
+#include <hpl_reset.h>
+#include <hpl_sleep.h>
+#include <hpl_delay.h>
+#ifndef _UNIT_TEST_
+#include <utils.h>
+#endif
+#include <utils_assert.h>
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 1000000
+#endif
+
+#if CONF_CPU_FREQUENCY < 1000
+#define CPU_FREQ_POWER 3
+#elif CONF_CPU_FREQUENCY < 10000
+#define CPU_FREQ_POWER 4
+#elif CONF_CPU_FREQUENCY < 100000
+#define CPU_FREQ_POWER 5
+#elif CONF_CPU_FREQUENCY < 1000000
+#define CPU_FREQ_POWER 6
+#elif CONF_CPU_FREQUENCY < 10000000
+#define CPU_FREQ_POWER 7
+#elif CONF_CPU_FREQUENCY < 100000000
+#define CPU_FREQ_POWER 8
+#endif
+
+/**
+ * \brief The array of interrupt handlers
+ */
+struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn];
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * \brief Retrieve current IRQ number
+ */
+uint8_t _irq_get_current(void)
+{
+	return (uint8_t)__get_IPSR() - 16;
+}
+
+/**
+ * \brief Disable the given IRQ
+ */
+void _irq_disable(uint8_t n)
+{
+	NVIC_DisableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Set the given IRQ
+ */
+void _irq_set(uint8_t n)
+{
+	NVIC_SetPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Clear the given IRQ
+ */
+void _irq_clear(uint8_t n)
+{
+	NVIC_ClearPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Enable the given IRQ
+ */
+void _irq_enable(uint8_t n)
+{
+	NVIC_EnableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Register IRQ handler
+ */
+void _irq_register(const uint8_t n, struct _irq_descriptor *const irq)
+{
+	ASSERT(n < PERIPH_COUNT_IRQn);
+
+	_irq_table[n] = irq;
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 8:
+		return (us * (freq / 100000) - 1) / 10 + 1;
+	case 7:
+		return (us * (freq / 10000) - 1) / 100 + 1;
+	case 6:
+		return (us * (freq / 1000) - 1) / 1000 + 1;
+	case 5:
+		return (us * (freq / 100) - 1) / 10000 + 1;
+	case 4:
+		return (us * (freq / 10) - 1) / 100000 + 1;
+	default:
+		return (us * freq - 1) / 1000000 + 1;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+uint32_t _get_cycles_for_us(const uint16_t us)
+{
+	return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 8:
+		return (ms * (freq / 100000)) * 100;
+	case 7:
+		return (ms * (freq / 10000)) * 10;
+	case 6:
+		return (ms * (freq / 1000));
+	case 5:
+		return (ms * (freq / 100) - 1) / 10 + 1;
+	case 4:
+		return (ms * (freq / 10) - 1) / 100 + 1;
+	default:
+		return (ms * freq - 1) / 1000 + 1;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+uint32_t _get_cycles_for_ms(const uint16_t ms)
+{
+	return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
diff --git a/Smol Watch Project/My Project/hpl/core/hpl_core_port.h b/Smol Watch Project/My Project/hpl/core/hpl_core_port.h
new file mode 100644
index 0000000..3f3e8f2
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/core/hpl_core_port.h	
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_PORT_H_INCLUDED
+#define _HPL_CORE_PORT_H_INCLUDED
+
+#include <peripheral_clk_config.h>
+
+/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR
+ * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h),
+ * there will be assembling errors.
+ * So the following things are not included for assembling.
+ */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+/**
+ * \brief Check if it's in ISR handling
+ * \return \c true if it's in ISR
+ */
+static inline bool _is_in_isr(void)
+{
+	return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+}
+
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _HPL_CORE_PORT_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/core/hpl_init.c b/Smol Watch Project/My Project/hpl/core/hpl_init.c
new file mode 100644
index 0000000..900cf42
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/core/hpl_init.c	
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief HPL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gpio.h>
+#include <hpl_init.h>
+#include <hpl_gclk_base.h>
+#include <hpl_mclk_config.h>
+
+#include <hpl_dma.h>
+#include <hpl_dmac_config.h>
+
+/* Referenced GCLKs (out of 0~4), should be initialized firstly
+ */
+#define _GCLK_INIT_1ST 0x00000000
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST 0x0000001F
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+	hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+	_set_performance_level(2);
+
+	_osc32kctrl_init_sources();
+	_oscctrl_init_sources();
+	_mclk_init();
+#if _GCLK_INIT_1ST
+	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+	_oscctrl_init_referenced_generators();
+	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+#if CONF_DMAC_ENABLE
+	hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
+	_dma_init();
+#endif
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+	_port_event_init();
+#endif
+}
diff --git a/Smol Watch Project/My Project/hpl/dmac/hpl_dmac.c b/Smol Watch Project/My Project/hpl/dmac/hpl_dmac.c
new file mode 100644
index 0000000..c12e025
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/dmac/hpl_dmac.c	
@@ -0,0 +1,244 @@
+
+/**
+ * \file
+ *
+ * \brief Generic DMAC related functionality.
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_dma.h>
+#include <hpl_dmac_config.h>
+#include <utils.h>
+#include <utils_assert.h>
+#include <utils_repeat_macro.h>
+
+#if CONF_DMAC_ENABLE
+
+/* Section containing first descriptors for all DMAC channels */
+COMPILER_ALIGNED(16)
+DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/* Section containing current descriptors for all DMAC channels */
+COMPILER_ALIGNED(16)
+DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR;
+
+/* Array containing callbacks for DMAC channels */
+static struct _dma_resource _resources[DMAC_CH_NUM];
+
+/* This macro DMAC configuration */
+#define DMAC_CHANNEL_CFG(i, n)                                                                                         \
+	{(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | (CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos),        \
+	 DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n)                         \
+	     | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos)                         \
+	     | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n),                    \
+	 DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos)                 \
+	     | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos)         \
+	     | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n)                 \
+	     | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)},
+
+/* DMAC channel configuration */
+struct dmac_channel_cfg {
+	uint8_t  ctrla;
+	uint32_t ctrlb;
+	uint16_t btctrl;
+};
+
+/* DMAC channel configurations */
+const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)};
+
+/**
+ * \brief Initialize DMAC
+ */
+int32_t _dma_init(void)
+{
+	uint8_t i = 0;
+
+	hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC);
+	hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC);
+	hri_dmac_set_CHCTRLA_SWRST_bit(DMAC);
+
+	hri_dmac_write_CTRL_reg(DMAC,
+	                        (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos)
+	                            | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos)
+	                            | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos));
+	hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN);
+
+	hri_dmac_write_QOSCTRL_reg(DMAC,
+	                           DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS)
+	                               | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS));
+
+	hri_dmac_write_PRICTRL0_reg(
+	    DMAC,
+	    DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1)
+	        | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3)
+	        | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos)
+	        | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos));
+	hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section);
+	hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section);
+
+	for (; i < DMAC_CH_NUM; i++) {
+		hri_dmac_write_CHID_reg(DMAC, i);
+
+		hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY);
+
+		hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb);
+		hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl);
+		hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0);
+	}
+
+	NVIC_DisableIRQ(DMAC_IRQn);
+	NVIC_ClearPendingIRQ(DMAC_IRQn);
+	NVIC_EnableIRQ(DMAC_IRQn);
+
+	hri_dmac_set_CTRL_DMAENABLE_bit(DMAC);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable DMA interrupt
+ */
+void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state)
+{
+	hri_dmac_write_CHID_reg(DMAC, channel);
+
+	if (DMA_TRANSFER_COMPLETE_CB == type) {
+		hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state);
+	} else if (DMA_TRANSFER_ERROR_CB == type) {
+		hri_dmac_write_CHINTEN_TERR_bit(DMAC, state);
+	}
+}
+
+int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst)
+{
+	hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_source_address(const uint8_t channel, const void *const src)
+{
+	hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel)
+{
+	hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel],
+	                                      (uint32_t)&_descriptor_section[next_channel]);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable)
+{
+	hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount)
+{
+	uint32_t address   = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]);
+	uint8_t  beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]);
+
+	if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) {
+		hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
+	}
+
+	address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]);
+
+	if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) {
+		hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size));
+	}
+
+	hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount);
+
+	return ERR_NONE;
+}
+
+int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger)
+{
+	hri_dmac_write_CHID_reg(DMAC, channel);
+	hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]);
+	hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC);
+	if (software_trigger) {
+		hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel)
+{
+	*resource = &_resources[channel];
+
+	return ERR_NONE;
+}
+
+int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable)
+{
+	hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable);
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal DMAC interrupt handler
+ */
+static inline void _dmac_handler(void)
+{
+	uint8_t               channel         = hri_dmac_read_INTPEND_ID_bf(DMAC);
+	uint8_t               current_channel = hri_dmac_read_CHID_reg(DMAC);
+	uint8_t               flag_status;
+	struct _dma_resource *tmp_resource = &_resources[channel];
+
+	hri_dmac_write_CHID_reg(DMAC, channel);
+	flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK);
+
+	if (flag_status & DMAC_CHINTFLAG_TERR) {
+		hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC);
+		tmp_resource->dma_cb.error(tmp_resource);
+	} else if (flag_status & DMAC_CHINTFLAG_TCMPL) {
+		hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC);
+		tmp_resource->dma_cb.transfer_done(tmp_resource);
+	}
+	hri_dmac_write_CHID_reg(DMAC, current_channel);
+}
+
+/**
+ * \brief DMAC interrupt handler
+ */
+void DMAC_Handler(void)
+{
+	_dmac_handler();
+}
+
+#endif /* CONF_DMAC_ENABLE */
diff --git a/Smol Watch Project/My Project/hpl/eic/hpl_eic.c b/Smol Watch Project/My Project/hpl/eic/hpl_eic.c
new file mode 100644
index 0000000..3b473ef
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/eic/hpl_eic.c	
@@ -0,0 +1,255 @@
+
+/**
+ * \file
+ *
+ * \brief EIC related functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_eic_config.h>
+#include <hpl_ext_irq.h>
+#include <string.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+#ifdef __MINGW32__
+#define ffs __builtin_ffs
+#endif
+#if defined(__CC_ARM) || defined(__ICCARM__)
+/* Find the first bit set */
+static int ffs(int v)
+{
+	int i, bit = 1;
+	for (i = 0; i < sizeof(int) * 8; i++) {
+		if (v & bit) {
+			return i + 1;
+		}
+		bit <<= 1;
+	}
+	return 0;
+}
+#endif
+
+/**
+ * \brief Invalid external interrupt and pin numbers
+ */
+#define INVALID_EXTINT_NUMBER 0xFF
+#define INVALID_PIN_NUMBER 0xFFFFFFFF
+
+#ifndef CONFIG_EIC_EXTINT_MAP
+/** Dummy mapping to pass compiling. */
+#define CONFIG_EIC_EXTINT_MAP                                                                                          \
+	{                                                                                                                  \
+		INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER                                                                      \
+	}
+#endif
+
+#define EXT_IRQ_AMOUNT 3
+
+/**
+ * \brief EXTINTx and pin number map
+ */
+struct _eic_map {
+	uint8_t  extint;
+	uint32_t pin;
+};
+
+/**
+ * \brief PIN and EXTINT map for enabled external interrupts
+ */
+static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP};
+
+/**
+ * \brief The callback to upper layer's interrupt processing routine
+ */
+static void (*callback)(const uint32_t pin);
+
+static void _ext_irq_handler(void);
+
+/**
+ * \brief Initialize external interrupt module
+ */
+int32_t _ext_irq_init(void (*cb)(const uint32_t pin))
+{
+	if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) {
+		if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) {
+			hri_eic_clear_CTRLA_ENABLE_bit(EIC);
+			hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE);
+		}
+		hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST);
+	}
+	hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST);
+
+	hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL);
+
+	hri_eic_write_NMICTRL_reg(EIC,
+	                          (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos)
+	                              | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH)
+	                              | 0);
+
+	hri_eic_write_EVCTRL_reg(EIC,
+	                         (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2)
+	                             | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5)
+	                             | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8)
+	                             | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11)
+	                             | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13)
+	                             | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0);
+	hri_eic_write_ASYNCH_reg(EIC,
+	                         (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2)
+	                             | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5)
+	                             | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8)
+	                             | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11)
+	                             | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14)
+	                             | (CONF_EIC_ASYNCH15 << 15) | 0);
+
+	hri_eic_write_CONFIG_reg(EIC,
+	                         0,
+	                         (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0)
+	                             | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1)
+	                             | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2)
+	                             | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3)
+	                             | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4)
+	                             | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5)
+	                             | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6)
+	                             | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7)
+	                             | 0);
+
+	hri_eic_write_CONFIG_reg(EIC,
+	                         1,
+	                         (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8)
+	                             | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9)
+	                             | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10)
+	                             | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11)
+	                             | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12)
+	                             | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13)
+	                             | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14)
+	                             | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15)
+	                             | 0);
+
+	hri_eic_set_CTRLA_ENABLE_bit(EIC);
+	NVIC_DisableIRQ(EIC_IRQn);
+	NVIC_ClearPendingIRQ(EIC_IRQn);
+	NVIC_EnableIRQ(EIC_IRQn);
+
+	callback = cb;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize external interrupt module
+ */
+int32_t _ext_irq_deinit(void)
+{
+	NVIC_DisableIRQ(EIC_IRQn);
+	callback = NULL;
+
+	hri_eic_clear_CTRLA_ENABLE_bit(EIC);
+	hri_eic_set_CTRLA_SWRST_bit(EIC);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable / disable external irq
+ */
+int32_t _ext_irq_enable(const uint32_t pin, const bool enable)
+{
+	uint8_t extint = INVALID_EXTINT_NUMBER;
+	uint8_t i      = 0;
+
+	for (; i < ARRAY_SIZE(_map); i++) {
+		if (_map[i].pin == pin) {
+			extint = _map[i].extint;
+			break;
+		}
+	}
+	if (INVALID_EXTINT_NUMBER == extint) {
+		return -1;
+	}
+
+	if (enable) {
+		hri_eic_set_INTEN_reg(EIC, 1ul << extint);
+	} else {
+		hri_eic_clear_INTEN_reg(EIC, 1ul << extint);
+		hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Inter EIC interrupt handler
+ */
+static void _ext_irq_handler(void)
+{
+	volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
+	int8_t            pos;
+	uint32_t          pin = INVALID_PIN_NUMBER;
+
+	hri_eic_clear_INTFLAG_reg(EIC, flags);
+
+	ASSERT(callback);
+
+	while (flags) {
+		pos = ffs(flags) - 1;
+		while (-1 != pos) {
+			uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+			while (upper >= lower) {
+				middle = (upper + lower) >> 1;
+				if (_map[middle].extint == pos) {
+					pin = _map[middle].pin;
+					break;
+				}
+				if (_map[middle].extint < pos) {
+					lower = middle + 1;
+				} else {
+					upper = middle - 1;
+				}
+			}
+
+			if (INVALID_PIN_NUMBER != pin) {
+				callback(pin);
+			}
+			flags &= ~(1ul << pos);
+			pos = ffs(flags) - 1;
+		}
+		flags = hri_eic_read_INTFLAG_reg(EIC);
+		hri_eic_clear_INTFLAG_reg(EIC, flags);
+	}
+}
+
+/**
+ * \brief EIC interrupt handler
+ */
+void EIC_Handler(void)
+{
+	_ext_irq_handler();
+}
diff --git a/Smol Watch Project/My Project/hpl/gclk/hpl_gclk.c b/Smol Watch Project/My Project/hpl/gclk/hpl_gclk.c
new file mode 100644
index 0000000..8645116
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/gclk/hpl_gclk.c	
@@ -0,0 +1,163 @@
+
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller related functionality.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gclk_config.h>
+#include <hpl_init.h>
+#include <utils_assert.h>
+
+/* Compatible naming definition */
+#ifndef GCLK_GENCTRL_SRC_DPLL
+#define GCLK_GENCTRL_SRC_DPLL GCLK_GENCTRL_SRC_FDPLL
+#endif
+
+/**
+ * \brief Initializes generators
+ */
+void _gclk_init_generators(void)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    0,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    1,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    2,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    3,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    4,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+#endif
+}
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	if (bm & (1ul << 0)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    0,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	if (bm & (1ul << 1)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    1,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	if (bm & (1ul << 2)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    2,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	if (bm & (1ul << 3)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    3,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	if (bm & (1ul << 4)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    4,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+	}
+#endif
+}
diff --git a/Smol Watch Project/My Project/hpl/gclk/hpl_gclk_base.h b/Smol Watch Project/My Project/hpl/gclk/hpl_gclk_base.h
new file mode 100644
index 0000000..3e7d282
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/gclk/hpl_gclk_base.h	
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GCLK_H_INCLUDED
+#define _HPL_GCLK_H_INCLUDED
+
+#include <compiler.h>
+#ifdef _UNIT_TEST_
+#include <hri_gclk1_v210_mock.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup gclk_group GCLK Hardware Proxy Layer
+ *
+ * \section gclk_hpl_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Enable clock on the given channel with the given clock source
+ *
+ * This function maps the given clock source to the given clock channel
+ * and enables channel.
+ *
+ * \param[in] channel The channel to enable clock for
+ * \param[in] source The clock source for the given channel
+ */
+static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source)
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN);
+}
+
+/**
+ * \brief Initialize GCLK generators by function references
+ * \param[in] bm Bit mapping for referenced generators,
+ *               a bit 1 in position triggers generator initialization.
+ */
+void _gclk_init_generators_by_fref(uint32_t bm);
+
+//@}
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_GCLK_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/mclk/hpl_mclk.c b/Smol Watch Project/My Project/hpl/mclk/hpl_mclk.c
new file mode 100644
index 0000000..2ada756
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/mclk/hpl_mclk.c	
@@ -0,0 +1,45 @@
+/**
+ * \file
+ *
+ * \brief SAM Main Clock.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hpl_mclk_config.h>
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void)
+{
+	void *hw = (void *)MCLK;
+	hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV));
+	hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV));
+}
diff --git a/Smol Watch Project/My Project/hpl/osc32kctrl/hpl_osc32kctrl.c b/Smol Watch Project/My Project/hpl/osc32kctrl/hpl_osc32kctrl.c
new file mode 100644
index 0000000..b6c624c
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/osc32kctrl/hpl_osc32kctrl.c	
@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief SAM 32k Oscillators Controller.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hpl_init.h>
+#include <compiler.h>
+#include <hpl_osc32kctrl_config.h>
+
+/**
+ * \brief Initialize 32 kHz clock sources
+ */
+void _osc32kctrl_init_sources(void)
+{
+	void *   hw    = (void *)OSC32KCTRL;
+	uint16_t calib = 0;
+
+#if CONF_XOSC32K_CONFIG == 1
+	hri_osc32kctrl_write_XOSC32K_reg(
+	    hw,
+	    OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+	        | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+	        | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
+	        | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos)
+	        | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
+
+	hri_osc32kctrl_write_CFDCTRL_reg(hw,
+	                                 (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
+	                                     | (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos));
+
+	hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos));
+#endif
+
+#if CONF_OSCULP32K_CONFIG == 1
+	calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
+	hri_osc32kctrl_write_OSCULP32K_reg(hw,
+#if CONF_OSC32K_CALIB_ENABLE == 1
+	                                   OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
+#else
+	                                   OSC32KCTRL_OSCULP32K_CALIB(calib)
+#endif
+	);
+#endif
+
+#if CONF_XOSC32K_CONFIG
+#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
+	while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
+		;
+#endif
+#if CONF_OSCULP32K_ULP32KSW == 1
+	hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW);
+	while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw))
+		;
+#endif
+#endif
+
+	hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+	(void)calib;
+}
diff --git a/Smol Watch Project/My Project/hpl/oscctrl/hpl_oscctrl.c b/Smol Watch Project/My Project/hpl/oscctrl/hpl_oscctrl.c
new file mode 100644
index 0000000..e11d70d
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/oscctrl/hpl_oscctrl.c	
@@ -0,0 +1,179 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Oscillators Controller.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_init.h>
+#include <hpl_oscctrl_config.h>
+
+/**
+ * \brief Initialize clock sources
+ */
+void _oscctrl_init_sources(void)
+{
+	void *hw = (void *)OSCCTRL;
+
+#if CONF_XOSC_CONFIG == 1
+	hri_oscctrl_write_XOSCCTRL_reg(
+	    hw,
+	    OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos)
+	        | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
+	        | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) | (CONF_XOSC_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos)
+	        | (CONF_XOSC_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos)
+	        | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
+
+	hri_oscctrl_write_EVCTRL_reg(hw, (CONF_XOSC_CFDEO << OSCCTRL_EVCTRL_CFDEO_Pos));
+#endif
+
+#if CONF_OSC16M_CONFIG == 1
+	hri_oscctrl_write_OSC16MCTRL_reg(hw,
+	                                 (CONF_OSC16M_ONDEMAND << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos)
+	                                     | (CONF_OSC16M_RUNSTDBY << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos)
+	                                     | (CONF_OSC16M_ENABLE << OSCCTRL_OSC16MCTRL_ENABLE_Pos)
+	                                     | OSCCTRL_OSC16MCTRL_FSEL(CONF_OSC16M_FSEL));
+#endif
+
+#if CONF_XOSC_CONFIG == 1
+#if CONF_XOSC_ENABLE == 1
+	while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw))
+		;
+#endif
+#if CONF_XOSC_AMPGC == 1
+	hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw);
+#endif
+#if CONF_XOSC_ONDEMAND == 1
+	hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw);
+#endif
+#endif
+
+#if CONF_OSC16M_CONFIG == 1
+#if CONF_OSC16M_ENABLE == 1
+	while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw))
+		;
+#endif
+#if CONF_OSC16M_ONDEMAND == 1
+	hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw);
+#endif
+#endif
+	(void)hw;
+}
+
+void _oscctrl_init_referenced_generators(void)
+{
+	void *                     hw  = (void *)OSCCTRL;
+	hri_oscctrl_dfllctrl_reg_t tmp = 0;
+
+#if CONF_DFLL_CONFIG == 1
+#if CONF_DFLL_OVERWRITE_CALIBRATION == 0
+#define NVM_DFLL_COARSE_POS 26
+#define NVM_DFLL_COARSE_SIZE 6
+	uint32_t coarse;
+	coarse = *((uint32_t *)(NVMCTRL_OTP5)) >> NVM_DFLL_COARSE_POS;
+#endif
+#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0
+	hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK));
+#endif
+	hri_oscctrl_write_DFLLCTRL_reg(hw, OSCCTRL_DFLLCTRL_ENABLE);
+	while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
+		;
+	hri_oscctrl_write_DFLLMUL_reg(hw,
+	                              OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP)
+	                                  | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL));
+	while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
+		;
+
+#if CONF_DFLL_OVERWRITE_CALIBRATION == 0
+	/* FINE is set to fixed value, which defined by DFLL48M Characteristics */
+	hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(coarse) | OSCCTRL_DFLLVAL_FINE(512));
+#else
+	hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE));
+#endif
+
+	tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRL_BPLCKC_Pos)
+	      | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRL_CCDIS_Pos)
+	      | (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRL_USBCRM_Pos)
+	      | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRL_STABLE_Pos)
+	      | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << OSCCTRL_DFLLCTRL_ENABLE_Pos);
+	hri_oscctrl_write_DFLLCTRL_reg(hw, tmp);
+
+#endif
+
+#if CONF_DPLL_CONFIG == 1
+#if CONF_DPLL_REFCLK == 2
+	hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK));
+#endif
+	hri_oscctrl_write_DPLLRATIO_reg(
+	    hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR));
+	hri_oscctrl_write_DPLLCTRLB_reg(
+	    hw,
+	    OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
+	        | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK)
+	        | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos)
+	        | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER));
+	hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC));
+	hri_oscctrl_write_DPLLCTRLA_reg(hw,
+	                                (0 << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
+	                                    | (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+	                                    | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
+#endif
+
+#if CONF_DFLL_CONFIG == 1
+	if (hri_oscctrl_get_DFLLCTRL_MODE_bit(hw)) {
+		hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
+
+		while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask)
+			;
+	} else {
+		while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
+			;
+	}
+#if CONF_DFLL_ONDEMAND == 1
+	hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(hw);
+#endif
+#endif
+
+#if CONF_DPLL_CONFIG == 1
+#if CONF_DPLL_ENABLE == 1
+	while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw)))
+		;
+#endif
+#if CONF_DPLL_ONDEMAND == 1
+	hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw);
+#endif
+#endif
+
+#if CONF_DFLL_CONFIG == 1
+	while (hri_gclk_read_SYNCBUSY_reg(GCLK))
+		;
+#endif
+	(void)hw, (void)tmp;
+}
diff --git a/Smol Watch Project/My Project/hpl/pm/hpl_pm.c b/Smol Watch Project/My Project/hpl/pm/hpl_pm.c
new file mode 100644
index 0000000..d6439f1
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/pm/hpl_pm.c	
@@ -0,0 +1,77 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Power manager
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_sleep.h>
+#include <hpl_reset.h>
+#include <hpl_init.h>
+
+/**
+ * \brief Retrieve the reset reason
+ */
+enum reset_reason _get_reset_reason(void)
+{
+	return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC);
+}
+
+/**
+ * \brief Set the sleep mode for the device
+ */
+int32_t _set_sleep_mode(const uint8_t mode)
+{
+	switch (mode) {
+	case 2: /* IDLE */
+	case 4: /* STANDBY */
+	case 5: /* BACKUP */
+	case 6: /* OFF */
+		hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode);
+		break;
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set performance level
+ */
+void _set_performance_level(const uint8_t level)
+{
+	if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) {
+		hri_pm_clear_INTFLAG_reg(PM, 0xFF);
+		hri_pm_write_PLCFG_PLSEL_bf(PM, level);
+		while (!hri_pm_read_INTFLAG_reg(PM))
+			;
+	}
+}
diff --git a/Smol Watch Project/My Project/hpl/pm/hpl_pm_base.h b/Smol Watch Project/My Project/hpl/pm/hpl_pm_base.h
new file mode 100644
index 0000000..5a50a91
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/pm/hpl_pm_base.h	
@@ -0,0 +1,45 @@
+/**
+ * \file
+ *
+ * \brief SAM Power manager
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_PM_BASE_H_INCLUDED
+#define _HPL_PM_BASE_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_PM_BASE_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/port/hpl_gpio_base.h b/Smol Watch Project/My Project/hpl/port/hpl_gpio_base.h
new file mode 100644
index 0000000..3cc1981
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/port/hpl_gpio_base.h	
@@ -0,0 +1,170 @@
+
+/**
+ * \file
+ *
+ * \brief SAM PORT.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+#include <hpl_port_config.h>
+
+/**
+ * \brief Set direction on port with mask
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction)
+{
+	switch (direction) {
+	case GPIO_DIRECTION_OFF:
+		hri_port_clear_DIR_reg(PORT_IOBUS, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_IN:
+		hri_port_clear_DIR_reg(PORT_IOBUS, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(PORT,
+		                            port,
+		                            PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN
+		                                | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_OUT:
+		hri_port_set_DIR_reg(PORT_IOBUS, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	default:
+		ASSERT(false);
+	}
+}
+
+/**
+ * \brief Set output level on port with mask
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	if (level) {
+		hri_port_set_OUT_reg(PORT_IOBUS, port, mask);
+	} else {
+		hri_port_clear_OUT_reg(PORT_IOBUS, port, mask);
+	}
+}
+
+/**
+ * \brief Change output level to the opposite with mask
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask)
+{
+	hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask);
+}
+
+/**
+ * \brief Get input levels on all port pins
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port)
+{
+	uint32_t tmp;
+
+	CRITICAL_SECTION_ENTER();
+
+	uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port);
+
+	tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
+	tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp;
+
+	CRITICAL_SECTION_LEAVE();
+
+	return tmp;
+}
+
+/**
+ * \brief Set pin pull mode
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode)
+{
+	switch (pull_mode) {
+	case GPIO_PULL_OFF:
+		hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin);
+		break;
+
+	case GPIO_PULL_UP:
+		hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin);
+		break;
+
+	case GPIO_PULL_DOWN:
+		hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin);
+		break;
+
+	default:
+		ASSERT(false);
+		break;
+	}
+}
+
+/**
+ * \brief Set gpio pin function
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
+{
+	uint8_t port = GPIO_PORT(gpio);
+	uint8_t pin  = GPIO_PIN(gpio);
+
+	if (function == GPIO_PIN_FUNCTION_OFF) {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
+
+	} else {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
+
+		if (pin & 1) {
+			// Odd numbered pin
+			hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
+		} else {
+			// Even numbered pin
+			hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
+		}
+	}
+}
+
+static inline void _port_event_init()
+{
+	hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
+	hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
+}
diff --git a/Smol Watch Project/My Project/hpl/rtc/hpl_rtc.c b/Smol Watch Project/My Project/hpl/rtc/hpl_rtc.c
new file mode 100644
index 0000000..2369a03
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/rtc/hpl_rtc.c	
@@ -0,0 +1,397 @@
+
+/**
+ * \file
+ *
+ * \brief RTC Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_calendar.h>
+#include <utils_assert.h>
+#include <hpl_rtc_config.h>
+
+/*!< Pointer to hpl device */
+static struct calendar_dev *_rtc_dev = NULL;
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ */
+int32_t _calendar_init(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	_rtc_dev = dev;
+
+	if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
+#if !CONF_RTC_INIT_RESET
+		return ERR_DENIED;
+#else
+		hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+		hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
+#endif
+	}
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+	hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
+
+#if CONF_RTC_EVENT_CONTROL_ENABLE == 1
+	hri_rtcmode0_write_EVCTRL_reg(
+	    dev->hw,
+	    (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+	        | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+	        | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+	        | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+	        | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
+#endif
+
+	hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC);
+
+	hri_rtc_write_TAMPCTRL_reg(
+	    dev->hw,
+	    (CONF_RTC_TAMPER_INACT_0 << RTC_TAMPCTRL_IN0ACT_Pos) | (CONF_RTC_TAMPER_INACT_1 << RTC_TAMPCTRL_IN1ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_2 << RTC_TAMPCTRL_IN2ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_3 << RTC_TAMPCTRL_IN3ACT_Pos)
+	        | (CONF_RTC_TAMPER_INACT_4 << RTC_TAMPCTRL_IN4ACT_Pos) | (CONF_RTC_TAMP_LVL_0 << RTC_TAMPCTRL_TAMLVL0_Pos)
+	        | (CONF_RTC_TAMP_LVL_1 << RTC_TAMPCTRL_TAMLVL1_Pos) | (CONF_RTC_TAMP_LVL_2 << RTC_TAMPCTRL_TAMLVL2_Pos)
+	        | (CONF_RTC_TAMP_LVL_3 << RTC_TAMPCTRL_TAMLVL3_Pos) | (CONF_RTC_TAMP_LVL_4 << RTC_TAMPCTRL_TAMLVL4_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_0 << RTC_TAMPCTRL_DEBNC0_Pos) | (CONF_RTC_TAMP_DEBNC_1 << RTC_TAMPCTRL_DEBNC1_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_2 << RTC_TAMPCTRL_DEBNC2_Pos) | (CONF_RTC_TAMP_DEBNC_3 << RTC_TAMPCTRL_DEBNC3_Pos)
+	        | (CONF_RTC_TAMP_DEBNC_4 << RTC_TAMPCTRL_DEBNC4_Pos));
+
+	if ((CONF_RTC_TAMPER_INACT_0 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_1 == TAMPER_MODE_ACTL)
+	    | (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL)
+	    | (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) {
+		hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw);
+	}
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinit the RTC module
+ */
+int32_t _calendar_deinit(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	NVIC_DisableIRQ(RTC_IRQn);
+	dev->callback = NULL;
+
+	hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+	hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable the RTC module
+ */
+int32_t _calendar_enable(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable the RTC module
+ */
+int32_t _calendar_disable(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set the current calendar time to desired time.
+ */
+int32_t _calendar_set_counter(struct calendar_dev *const dev, const uint32_t counter)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_write_COUNT_reg(dev->hw, counter);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get current counter
+ */
+uint32_t _calendar_get_counter(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	return hri_rtcmode0_read_COUNT_reg(dev->hw);
+}
+
+/**
+ * \brief Set the compare for the specified value.
+ */
+int32_t _calendar_set_comp(struct calendar_dev *const dev, const uint32_t comp)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtcmode0_write_COMP_reg(dev->hw, 0, comp);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get the compare value
+ */
+uint32_t _calendar_get_comp(struct calendar_dev *const dev)
+{
+	ASSERT(dev && dev->hw);
+
+	return hri_rtcmode0_read_COMP_reg(dev->hw, 0);
+}
+
+/**
+ * \brief Find tamper is detected on specified pin
+ */
+bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin)
+{
+	bool value;
+
+	ASSERT(dev && dev->hw);
+
+	value = ((hri_rtc_read_TAMPID_reg(dev->hw) >> tamper_id_pin) & 0x01);
+	return value;
+}
+
+/**
+ * \brief Clear the Tamper ID flag
+ */
+int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin)
+{
+	ASSERT(dev && dev->hw);
+
+	hri_rtc_write_TAMPID_reg(dev->hw, (true << tamper_id_pin));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable Tamper Debounce Asynchronous Feature
+ */
+int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBASYNC_bit(dev->hw, true);
+		return_value = ERR_NONE;
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Disable Tamper Debounce Asynchronous Feature
+ */
+int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBASYNC_bit(dev->hw, false);
+		return_value = ERR_NONE;
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Enable Tamper Debounce Majority Feature
+ */
+int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBMAJ_bit(dev->hw, true);
+		return_value = ERR_NONE;
+
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Disable Tamper Debounce Majority Feature
+ */
+int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev)
+{
+	int32_t return_value;
+
+	hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, false);
+
+	while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+	}
+
+	if (hri_rtcmode0_read_CTRLA_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		return_value = ERR_FAILURE;
+	} else {
+		hri_rtcmode0_write_CTRLB_DEBMAJ_bit(dev->hw, false);
+		return_value = ERR_NONE;
+
+		while (hri_rtcmode0_read_SYNCBUSY_reg(dev->hw) & RTC_MODE2_CTRLA_ENABLE) {
+		}
+		hri_rtcmode0_write_CTRLA_ENABLE_bit(dev->hw, true);
+	}
+
+	return return_value;
+}
+
+int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper)
+{
+	ASSERT(dev && dev->hw);
+
+	/* Check callback */
+	if (callback_tamper != NULL) {
+		/* register the callback */
+		dev->callback_tamper = callback_tamper;
+
+		/* enable RTC_IRQn */
+		NVIC_ClearPendingIRQ(RTC_IRQn);
+		NVIC_EnableIRQ(RTC_IRQn);
+
+		/* enable tamper interrupt */
+		hri_rtcmode0_set_INTEN_TAMPER_bit(dev->hw);
+	} else {
+		/* disable tamper interrupt */
+		hri_rtcmode0_clear_INTEN_TAMPER_bit(dev->hw);
+
+		/* disable RTC_IRQn */
+		NVIC_DisableIRQ(RTC_IRQn);
+	}
+
+	return ERR_NONE;
+}
+/**
+ * \brief Registers callback for the specified callback type
+ */
+int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback)
+{
+	ASSERT(dev && dev->hw);
+
+	/* Check callback */
+	if (callback != NULL) {
+		/* register the callback */
+		dev->callback = callback;
+
+		/* enable RTC_IRQn */
+		NVIC_ClearPendingIRQ(RTC_IRQn);
+		NVIC_EnableIRQ(RTC_IRQn);
+
+		/* enable cmp */
+		hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw);
+	} else {
+		/* disable cmp */
+		hri_rtcmode0_clear_INTEN_CMP0_bit(dev->hw);
+
+		/* disable RTC_IRQn */
+		NVIC_DisableIRQ(RTC_IRQn);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief RTC interrupt handler
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+static void _rtc_interrupt_handler(struct calendar_dev *dev)
+{
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status  = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
+	uint16_t interrupt_enabled = hri_rtcmode0_read_INTEN_reg(dev->hw);
+
+	if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
+		dev->callback(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+	} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
+		dev->callback_tamper(dev);
+
+		/* Clear interrupt flag */
+		hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+	}
+}
+/**
+ * \brief Set calendar IRQ
+ */
+void _calendar_set_irq(struct calendar_dev *const dev)
+{
+	(void)dev;
+	NVIC_SetPendingIRQ(RTC_IRQn);
+}
+
+/**
+ * \brief Rtc interrupt handler
+ */
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(_rtc_dev);
+}
diff --git a/Smol Watch Project/My Project/hpl/rtc/hpl_rtc_base.h b/Smol Watch Project/My Project/hpl/rtc/hpl_rtc_base.h
new file mode 100644
index 0000000..06e3bd7
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/rtc/hpl_rtc_base.h	
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_RTC2_V200_H_INCLUDED
+#define _HPL_RTC2_V200_H_INCLUDED
+
+#include <hpl_timer.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_rtc_get_timer(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_RTC2_V200_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/sercom/hpl_sercom.c b/Smol Watch Project/My Project/hpl/sercom/hpl_sercom.c
new file mode 100644
index 0000000..a241e97
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/sercom/hpl_sercom.c	
@@ -0,0 +1,2929 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Serial Communication Interface
+ *
+ * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hpl_dma.h>
+#include <hpl_i2c_m_async.h>
+#include <hpl_i2c_m_sync.h>
+#include <hpl_i2c_s_async.h>
+#include <hpl_sercom_config.h>
+#include <hpl_spi_m_async.h>
+#include <hpl_spi_m_sync.h>
+#include <hpl_spi_s_async.h>
+#include <hpl_spi_s_sync.h>
+#include <hpl_usart_async.h>
+#include <hpl_usart_sync.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+#ifndef CONF_SERCOM_0_USART_ENABLE
+#define CONF_SERCOM_0_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_USART_ENABLE
+#define CONF_SERCOM_1_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_USART_ENABLE
+#define CONF_SERCOM_3_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_USART_ENABLE
+#define CONF_SERCOM_4_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_USART_ENABLE
+#define CONF_SERCOM_5_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_USART_ENABLE
+#define CONF_SERCOM_6_USART_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_USART_ENABLE
+#define CONF_SERCOM_7_USART_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as USART. */
+#define SERCOM_USART_AMOUNT                                                                                            \
+	(CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \
+	 + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE                            \
+	 + CONF_SERCOM_7_USART_ENABLE)
+
+/**
+ * \brief Macro is used to fill usart configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define SERCOM_CONFIGURATION(n)                                                                                        \
+	{                                                                                                                  \
+		n,                                                                                                             \
+		    SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE)                                                      \
+		        | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos)                                \
+		        | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos)                                        \
+		        | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR)                                              \
+		        | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO)                                                \
+		        | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO)                                                \
+		        | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA)                                              \
+		        | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM)                                                \
+		        | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos)                                      \
+		        | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos),                                       \
+		    SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE)                                                  \
+		        | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos)                                    \
+		        | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos)                                    \
+		        | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos)                                          \
+		        | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos)                                      \
+		        | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos)                                        \
+		        | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos),                                       \
+		    (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL,                         \
+		    CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE,                     \
+	}
+
+/**
+ * \brief SERCOM USART configuration type
+ */
+struct usart_configuration {
+	uint8_t                       number;
+	hri_sercomusart_ctrla_reg_t   ctrl_a;
+	hri_sercomusart_ctrlb_reg_t   ctrl_b;
+	hri_sercomusart_baud_reg_t    baud;
+	uint8_t                       fractional;
+	hri_sercomusart_rxpl_reg_t    rxpl;
+	hri_sercomusart_dbgctrl_reg_t debug_ctrl;
+};
+
+#if SERCOM_USART_AMOUNT < 1
+/** Dummy array to pass compiling. */
+static struct usart_configuration _usarts[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM USART configurations
+ */
+static struct usart_configuration _usarts[] = {
+#if CONF_SERCOM_0_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_USART_ENABLE == 1
+    SERCOM_CONFIGURATION(7),
+#endif
+};
+#endif
+
+static uint8_t _get_sercom_index(const void *const hw);
+static uint8_t _sercom_get_irq_num(const void *const hw);
+static void    _sercom_init_irq_param(const void *const hw, void *dev);
+static uint8_t _sercom_get_hardware_index(const void *const hw);
+
+static int32_t     _usart_init(void *const hw);
+static inline void _usart_deinit(void *const hw);
+static uint16_t    _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                              const enum usart_baud_rate_mode mode, const uint8_t fraction);
+static void        _usart_set_baud_rate(void *const hw, const uint32_t baud_rate);
+static void        _usart_set_data_order(void *const hw, const enum usart_data_order order);
+static void        _usart_set_mode(void *const hw, const enum usart_mode mode);
+static void        _usart_set_parity(void *const hw, const enum usart_parity parity);
+static void        _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits);
+static void        _usart_set_character_size(void *const hw, const enum usart_character_size size);
+
+/**
+ * \brief Initialize synchronous SERCOM USART
+ */
+int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _usart_init(hw);
+}
+
+/**
+ * \brief Initialize asynchronous SERCOM USART
+ */
+int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _usart_init(hw);
+	if (init_status) {
+		return init_status;
+	}
+	device->hw = hw;
+	_sercom_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize SERCOM USART
+ */
+void _usart_sync_deinit(struct _usart_sync_device *const device)
+{
+	_usart_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize SERCOM USART
+ */
+void _usart_async_deinit(struct _usart_async_device *const device)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw));
+	_usart_deinit(device->hw);
+}
+
+/**
+ * \brief Calculate baud rate register value
+ */
+uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                         const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction);
+}
+
+/**
+ * \brief Calculate baud rate register value
+ */
+uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                          const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction);
+}
+
+/**
+ * \brief Enable SERCOM module
+ */
+void _usart_sync_enable(struct _usart_sync_device *const device)
+{
+	hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable SERCOM module
+ */
+void _usart_async_enable(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable SERCOM module
+ */
+void _usart_sync_disable(struct _usart_sync_device *const device)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable SERCOM module
+ */
+void _usart_async_disable(struct _usart_async_device *const device)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Set baud rate
+ */
+void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate)
+{
+	_usart_set_baud_rate(device->hw, baud_rate);
+}
+
+/**
+ * \brief Set baud rate
+ */
+void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate)
+{
+	_usart_set_baud_rate(device->hw, baud_rate);
+}
+
+/**
+ * \brief Set data order
+ */
+void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order)
+{
+	_usart_set_data_order(device->hw, order);
+}
+
+/**
+ * \brief Set data order
+ */
+void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order)
+{
+	_usart_set_data_order(device->hw, order);
+}
+
+/**
+ * \brief Set mode
+ */
+void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode)
+{
+	_usart_set_mode(device->hw, mode);
+}
+
+/**
+ * \brief Set mode
+ */
+void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode)
+{
+	_usart_set_mode(device->hw, mode);
+}
+
+/**
+ * \brief Set parity
+ */
+void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity)
+{
+	_usart_set_parity(device->hw, parity);
+}
+
+/**
+ * \brief Set parity
+ */
+void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity)
+{
+	_usart_set_parity(device->hw, parity);
+}
+
+/**
+ * \brief Set stop bits mode
+ */
+void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits)
+{
+	_usart_set_stop_bits(device->hw, stop_bits);
+}
+
+/**
+ * \brief Set stop bits mode
+ */
+void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits)
+{
+	_usart_set_stop_bits(device->hw, stop_bits);
+}
+
+/**
+ * \brief Set character size
+ */
+void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size)
+{
+	_usart_set_character_size(device->hw, size);
+}
+
+/**
+ * \brief Set character size
+ */
+void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size)
+{
+	_usart_set_character_size(device->hw, size);
+}
+
+/**
+ * \brief Retrieve SERCOM usart status
+ */
+uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Retrieve SERCOM usart status
+ */
+uint32_t _usart_async_get_status(const struct _usart_async_device *const device)
+{
+	return hri_sercomusart_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Write a byte to the given SERCOM USART instance
+ */
+void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data)
+{
+	hri_sercomusart_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Write a byte to the given SERCOM USART instance
+ */
+void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data)
+{
+	hri_sercomusart_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Read a byte from the given SERCOM USART instance
+ */
+uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_read_DATA_reg(device->hw);
+}
+
+/**
+ * \brief Check if USART is ready to send next byte
+ */
+bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Check if USART transmission complete
+ */
+bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
+}
+
+/**
+ * \brief Check if USART is ready to send next byte
+ */
+bool _usart_async_is_byte_sent(const struct _usart_async_device *const device)
+{
+	return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Check if there is data received by USART
+ */
+bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device)
+{
+	return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
+}
+
+/**
+ * \brief Set the state of flow control pins
+ */
+void _usart_sync_set_flow_control_state(struct _usart_sync_device *const     device,
+                                        const union usart_flow_control_state state)
+{
+	(void)device;
+	(void)state;
+}
+
+/**
+ * \brief Set the state of flow control pins
+ */
+void _usart_async_set_flow_control_state(struct _usart_async_device *const    device,
+                                         const union usart_flow_control_state state)
+{
+	(void)device;
+	(void)state;
+}
+
+/**
+ * \brief Retrieve the state of flow control pins
+ */
+union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device)
+{
+	(void)device;
+	union usart_flow_control_state state;
+
+	state.value           = 0;
+	state.bit.unavailable = 1;
+	return state;
+}
+
+/**
+ * \brief Retrieve the state of flow control pins
+ */
+union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device)
+{
+	(void)device;
+	union usart_flow_control_state state;
+
+	state.value           = 0;
+	state.bit.unavailable = 1;
+	return state;
+}
+
+/**
+ * \brief Enable data register empty interrupt
+ */
+void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_INTEN_DRE_bit(device->hw);
+}
+
+/**
+ * \brief Enable transmission complete interrupt
+ */
+void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device)
+{
+	hri_sercomusart_set_INTEN_TXC_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve ordinal number of the given sercom hardware instance
+ */
+static uint8_t _sercom_get_hardware_index(const void *const hw)
+{
+#ifdef _UNIT_TEST_
+	return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom);
+#endif
+
+	return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
+}
+
+/**
+ * \brief Retrieve ordinal number of the given SERCOM USART hardware instance
+ */
+uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device)
+{
+	return _sercom_get_hardware_index(device->hw);
+}
+
+/**
+ * \brief Retrieve ordinal number of the given SERCOM USART hardware instance
+ */
+uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device)
+{
+	return _sercom_get_hardware_index(device->hw);
+}
+
+/**
+ * \brief Enable/disable USART interrupt
+ */
+void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
+                                const bool state)
+{
+	ASSERT(device);
+
+	if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) {
+		hri_sercomusart_write_INTEN_DRE_bit(device->hw, state);
+		hri_sercomusart_write_INTEN_TXC_bit(device->hw, state);
+	} else if (USART_ASYNC_RX_DONE == type) {
+		hri_sercomusart_write_INTEN_RXC_bit(device->hw, state);
+	} else if (USART_ASYNC_ERROR == type) {
+		hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state);
+	}
+}
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static uint8_t _get_sercom_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_usarts); i++) {
+		if (_usarts[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return 0;
+}
+
+/**
+ * \brief Init irq param with the given sercom hardware instance
+ */
+static void _sercom_init_irq_param(const void *const hw, void *dev)
+{
+}
+
+/**
+ * \internal Initialize SERCOM USART
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The status of initialization
+ */
+static int32_t _usart_init(void *const hw)
+{
+	uint8_t i = _get_sercom_index(hw);
+
+	if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
+		uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
+		if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
+			hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+		}
+		hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
+	}
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+
+	hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a);
+	hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b);
+	if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) {
+		((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud;
+		((Sercom *)hw)->USART.BAUD.FRAC.FP   = _usarts[i].fractional;
+	} else {
+		hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud);
+	}
+
+	hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
+	hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal De-initialize SERCOM USART
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _usart_deinit(void *const hw)
+{
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomusart_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \internal Calculate baud rate register value
+ *
+ * \param[in] baud Required baud rate
+ * \param[in] clock_rate SERCOM clock frequency
+ * \param[in] samples The number of samples
+ * \param[in] mode USART mode
+ * \param[in] fraction A fraction value
+ *
+ * \return Calculated baud rate register value
+ */
+static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
+                                           const enum usart_baud_rate_mode mode, const uint8_t fraction)
+{
+	if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) {
+		return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate;
+	}
+
+	if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) {
+		return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction);
+	}
+
+	if (USART_BAUDRATE_SYNCH == mode) {
+		return clock_rate / baud / 2 - 1;
+	}
+
+	return 0;
+}
+
+/**
+ * \internal Set baud rate
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] baud_rate A baud rate to set
+ */
+static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_BAUD_reg(hw, baud_rate);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set data order
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] order A data order to set
+ */
+static void _usart_set_data_order(void *const hw, const enum usart_data_order order)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLA_DORD_bit(hw, order);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] mode A mode to set
+ */
+static void _usart_set_mode(void *const hw, const enum usart_mode mode)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set parity
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] parity A parity to set
+ */
+static void _usart_set_parity(void *const hw, const enum usart_parity parity)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+
+	if (USART_PARITY_NONE != parity) {
+		hri_sercomusart_set_CTRLA_FORM_bf(hw, 1);
+	} else {
+		hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1);
+	}
+
+	hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set stop bits mode
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] stop_bits A stop bits mode to set
+ */
+static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits);
+	CRITICAL_SECTION_LEAVE()
+
+	hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled);
+}
+
+/**
+ * \internal Set character size
+ *
+ * \param[in] device The pointer to USART device instance
+ * \param[in] size A character size to set
+ */
+static void _usart_set_character_size(void *const hw, const enum usart_character_size size)
+{
+	bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw);
+
+	hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
+	hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size);
+	CRITICAL_SECTION_LEAVE()
+
+	if (enabled) {
+		hri_sercomusart_set_CTRLA_ENABLE_bit(hw);
+	}
+}
+
+	/* Sercom I2C implementation */
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_I2CM_ENABLE
+#define CONF_SERCOM_1_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_I2CM_ENABLE
+#define CONF_SERCOM_2_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_I2CM_ENABLE
+#define CONF_SERCOM_3_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_I2CM_ENABLE
+#define CONF_SERCOM_4_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_I2CM_ENABLE
+#define CONF_SERCOM_5_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_I2CM_ENABLE
+#define CONF_SERCOM_6_I2CM_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_I2CM_ENABLE
+#define CONF_SERCOM_7_I2CM_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as I2C Master. */
+#define SERCOM_I2CM_AMOUNT                                                                                             \
+	(CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE     \
+	 + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE)
+
+/**
+ * \brief Macro is used to fill i2cm configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define I2CM_CONFIGURATION(n)                                                                                          \
+	{                                                                                                                  \
+		(n),                                                                                                           \
+		    (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)  \
+		        | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos),                                   \
+		    SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE),                                      \
+		    CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \
+	}
+
+#define ERROR_FLAG (1 << 7)
+#define SB_FLAG (1 << 1)
+#define MB_FLAG (1 << 0)
+
+#define CMD_STOP 0x3
+#define I2C_IDLE 0x1
+#define I2C_SM 0x0
+#define I2C_FM 0x1
+#define I2C_HS 0x2
+#define TEN_ADDR_FRAME 0x78
+#define TEN_ADDR_MASK 0x3ff
+#define SEVEN_ADDR_MASK 0x7f
+
+/**
+ * \brief SERCOM I2CM configuration type
+ */
+struct i2cm_configuration {
+	uint8_t                      number;
+	hri_sercomi2cm_ctrla_reg_t   ctrl_a;
+	hri_sercomi2cm_ctrlb_reg_t   ctrl_b;
+	hri_sercomi2cm_baud_reg_t    baud;
+	hri_sercomi2cm_dbgctrl_reg_t dbgctrl;
+	uint16_t                     trise;
+	uint32_t                     clk; /* SERCOM peripheral clock frequency */
+};
+
+static inline int32_t _i2c_m_enable_implementation(void *hw);
+static int32_t        _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw);
+
+#if SERCOM_I2CM_AMOUNT < 1
+/** Dummy array to pass compiling. */
+static struct i2cm_configuration _i2cms[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM I2CM configurations
+ */
+static struct i2cm_configuration _i2cms[] = {
+#if CONF_SERCOM_0_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_I2CM_ENABLE == 1
+    I2CM_CONFIGURATION(7),
+#endif
+};
+#endif
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2cm_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+		if (_i2cms[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+static inline void _sercom_i2c_send_stop(void *const hw)
+{
+	hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP);
+}
+
+/**
+ * \brief SERCOM I2CM analyze hardware status and transfer next byte
+ */
+static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg)
+{
+	int      sclsm  = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+	uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw);
+
+	if (flags & MB_FLAG) {
+		/* tx error */
+		if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+			hri_sercomi2cm_clear_interrupt_MB_bit(hw);
+			msg->flags |= I2C_M_FAIL;
+			msg->flags &= ~I2C_M_BUSY;
+
+			if (status & SERCOM_I2CM_STATUS_BUSERR) {
+				return I2C_ERR_BUS;
+			}
+
+			return I2C_ERR_BAD_ADDRESS;
+		} else {
+			if (status & SERCOM_I2CM_STATUS_RXNACK) {
+
+				/* Slave rejects to receive more data */
+				if (msg->len > 0) {
+					msg->flags |= I2C_M_FAIL;
+				}
+
+				if (msg->flags & I2C_M_STOP) {
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+
+				return I2C_NACK;
+			}
+
+			if (msg->flags & I2C_M_TEN) {
+				hri_sercomi2cm_write_ADDR_reg(hw,
+				                              ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+				                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+				msg->flags &= ~I2C_M_TEN;
+
+				return I2C_OK;
+			}
+
+			if (msg->len == 0) {
+				if (msg->flags & I2C_M_STOP) {
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+			} else {
+				hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+				msg->buffer++;
+				msg->len--;
+			}
+
+			return I2C_OK;
+		}
+	} else if (flags & SB_FLAG) {
+		if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+			msg->len--;
+
+			/* last byte, send nack */
+			if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+				hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+			}
+
+			if (msg->len == 0) {
+				if (msg->flags & I2C_M_STOP) {
+					hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw);
+					_sercom_i2c_send_stop(hw);
+				}
+
+				msg->flags &= ~I2C_M_BUSY;
+			}
+
+			/* Accessing DATA.DATA auto-triggers I2C bus operations.
+			 * The operation performed depends on the state of
+			 * CTRLB.ACKACT, CTRLB.SMEN
+			 **/
+			*msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+		} else {
+			hri_sercomi2cm_clear_interrupt_SB_bit(hw);
+			return I2C_NACK;
+		}
+
+		hri_sercomi2cm_clear_interrupt_SB_bit(hw);
+	}
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Enable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+}
+
+/**
+ * \brief Disable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set baudrate of master
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] clkrate The clock rate of i2c master, in KHz
+ * \param[in] baudrate The baud rate desired for i2c master, in KHz
+ */
+int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate)
+{
+	uint32_t tmp;
+	void *   hw = i2c_dev->hw;
+
+	if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_DENIED;
+	}
+
+	tmp     = _get_i2cm_index(hw);
+	clkrate = _i2cms[tmp].clk / 1000;
+
+	if (i2c_dev->service.mode == I2C_STANDARD_MODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_FASTMODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) {
+		tmp = (clkrate - 2 * baudrate) / (2 * baudrate);
+		hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp);
+	} else {
+		/* error baudrate */
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve IRQ number for the given hardware instance
+ */
+static uint8_t _sercom_get_irq_num(const void *const hw)
+{
+	return SERCOM0_IRQn + _sercom_get_hardware_index(hw);
+}
+
+/**
+ * \brief Initialize sercom i2c module to use in async mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(i2c_dev);
+
+	i2c_dev->hw = hw;
+
+	init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	_sercom_init_irq_param(hw, (void *)i2c_dev);
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize sercom i2c module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw);
+	hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Transfer the slave address to bus, which will start the transfer
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *             hw    = i2c_dev->hw;
+	struct _i2c_m_msg *msg   = &i2c_dev->service.msg;
+	int                sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+
+	ASSERT(i2c_dev);
+
+	if (msg->len == 1 && sclsm) {
+		hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+	} else {
+		hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw);
+	}
+
+	/* ten bit address */
+	if (msg->addr & I2C_M_TEN) {
+		if (msg->flags & I2C_M_RD) {
+			msg->flags |= I2C_M_TEN;
+		}
+
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	} else {
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Transfer data specified by msg
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] msg The pointer to i2c message
+ *
+ * \return Transfer status.
+ * \retval 0 Transfer success
+ * \retval <0 Transfer fail, return the error code
+ */
+int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg)
+{
+	int ret;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+	ASSERT(msg);
+
+	if (msg->len == 0) {
+		return ERR_NONE;
+	}
+
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return ERR_BUSY;
+	}
+
+	msg->flags |= I2C_M_BUSY;
+	i2c_dev->service.msg = *msg;
+	hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw);
+
+	ret = _sercom_i2c_send_address(i2c_dev);
+
+	if (ret) {
+		i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set callback to be called in interrupt handler
+ *
+ * \param[in] i2c_dev The pointer to master i2c device
+ * \param[in] type The callback type
+ * \param[in] func The callback function pointer
+ */
+int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type,
+                                       FUNC_PTR func)
+{
+	switch (type) {
+	case I2C_M_ASYNC_DEVICE_ERROR:
+		i2c_dev->cb.error = (_i2c_error_cb_t)func;
+		break;
+	case I2C_M_ASYNC_DEVICE_TX_COMPLETE:
+		i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func;
+		break;
+	case I2C_M_ASYNC_DEVICE_RX_COMPLETE:
+		i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func;
+		break;
+	default:
+		/* error */
+		break;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set stop condition on I2C
+ *
+ * \param i2c_dev Pointer to master i2c device
+ *
+ * \return Operation status
+ * \retval I2C_OK Operation was successfull
+ */
+int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	_sercom_i2c_send_stop(hw);
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Get number of bytes left in transfer buffer
+ *
+ * \param i2c_dev Pointer to i2c master device
+ *
+ * \return Bytes left in buffer
+ * \retval =>0 Bytes left in buffer
+ */
+int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev)
+{
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return i2c_dev->service.msg.len;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Initialize sercom i2c module to use in sync mode
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw)
+{
+	ASSERT(i2c_dev);
+
+	i2c_dev->hw = hw;
+
+	return _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+}
+
+/**
+ * \brief Deinitialize sercom i2c module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw);
+	hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev)
+{
+	ASSERT(i2c_dev);
+
+	return _i2c_m_enable_implementation(i2c_dev->hw);
+}
+
+/**
+ * \brief Disable the i2c master module
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+
+	hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set baudrate of master
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] clkrate The clock rate of i2c master, in KHz
+ * \param[in] baudrate The baud rate desired for i2c master, in KHz
+ */
+int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate)
+{
+	uint32_t tmp;
+	void *   hw = i2c_dev->hw;
+
+	if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_DENIED;
+	}
+
+	tmp     = _get_i2cm_index(hw);
+	clkrate = _i2cms[tmp].clk / 1000;
+
+	if (i2c_dev->service.mode == I2C_STANDARD_MODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_FASTMODE) {
+		tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001))
+		                 / (2 * baudrate));
+		hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp);
+	} else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) {
+		tmp = (clkrate - 2 * baudrate) / (2 * baudrate);
+		hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp);
+	} else {
+		/* error baudrate */
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable I2C master interrupt
+ */
+void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
+                                const bool state)
+{
+	if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) {
+		hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state);
+		hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state);
+	} else if (I2C_M_ASYNC_DEVICE_ERROR == type) {
+		hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state);
+	}
+}
+
+/**
+ * \brief Wait for bus response
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] flags Store the hardware response
+ *
+ * \return Bus response status.
+ * \retval 0 Bus response status OK
+ * \retval <0 Bus response fail
+ */
+inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags)
+{
+	uint32_t timeout = 65535;
+	void *   hw      = i2c_dev->hw;
+
+	do {
+		*flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+
+		if (timeout-- == 0) {
+			return I2C_ERR_BUS;
+		}
+	} while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+
+	return I2C_OK;
+}
+
+/**
+ * \brief Send the slave address to bus, which will start the transfer
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ */
+static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *             hw    = i2c_dev->hw;
+	struct _i2c_m_msg *msg   = &i2c_dev->service.msg;
+	int                sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw);
+	uint32_t           flags;
+
+	ASSERT(i2c_dev);
+
+	if (msg->len == 1 && sclsm) {
+		hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw);
+	} else {
+		hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw);
+	}
+
+	/* ten bit address */
+	if (msg->addr & I2C_M_TEN) {
+		if (msg->flags & I2C_M_RD) {
+			msg->flags |= I2C_M_TEN;
+		}
+
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	} else {
+		hri_sercomi2cm_write_ADDR_reg(hw,
+		                              ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+		                                  | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+	}
+
+	_sercom_i2c_sync_wait_bus(i2c_dev, &flags);
+	return _sercom_i2c_sync_analyse_flags(hw, flags, msg);
+}
+
+/**
+ * \brief Transfer data specified by msg
+ *
+ * \param[in] i2c_dev The pointer to i2c device
+ * \param[in] msg The pointer to i2c message
+ *
+ * \return Transfer status.
+ * \retval 0 Transfer success
+ * \retval <0 Transfer fail or partial fail, return the error code
+ */
+int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg)
+{
+	uint32_t flags;
+	int      ret;
+	void *   hw = i2c_dev->hw;
+
+	ASSERT(i2c_dev);
+	ASSERT(i2c_dev->hw);
+	ASSERT(msg);
+
+	if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		return I2C_ERR_BUSY;
+	}
+
+	msg->flags |= I2C_M_BUSY;
+	i2c_dev->service.msg = *msg;
+	hri_sercomi2cm_set_CTRLB_SMEN_bit(hw);
+
+	ret = _sercom_i2c_sync_send_address(i2c_dev);
+
+	if (ret) {
+		i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+		return ret;
+	}
+
+	while (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+		ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags);
+
+		if (ret) {
+			if (msg->flags & I2C_M_STOP) {
+				_sercom_i2c_send_stop(hw);
+			}
+
+			i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+
+			return ret;
+		}
+
+		ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg);
+	}
+
+	return ret;
+}
+
+int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev)
+{
+	void *hw = i2c_dev->hw;
+
+	_sercom_i2c_send_stop(hw);
+
+	return I2C_OK;
+}
+
+static inline int32_t _i2c_m_enable_implementation(void *const hw)
+{
+	int timeout         = 65535;
+	int timeout_attempt = 4;
+
+	ASSERT(hw);
+
+	/* Enable interrupts */
+	hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw);
+
+	while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) {
+		timeout--;
+
+		if (timeout <= 0) {
+			if (--timeout_attempt)
+				timeout = 65535;
+			else
+				return I2C_ERR_BUSY;
+			hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE));
+		}
+	}
+	return ERR_NONE;
+}
+
+static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw)
+{
+	uint8_t i = _get_i2cm_index(hw);
+
+	if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) {
+		uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk;
+		if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) {
+			hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE);
+		}
+		hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode);
+	}
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+
+	hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a);
+	hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b);
+	hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud);
+
+	service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1);
+
+	service->trise = _i2cms[i].trise;
+
+	return ERR_NONE;
+}
+
+	/* SERCOM I2C slave */
+
+#ifndef CONF_SERCOM_0_I2CS_ENABLE
+#define CONF_SERCOM_0_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_I2CS_ENABLE
+#define CONF_SERCOM_1_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_I2CS_ENABLE
+#define CONF_SERCOM_2_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_I2CS_ENABLE
+#define CONF_SERCOM_3_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_I2CS_ENABLE
+#define CONF_SERCOM_4_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_I2CS_ENABLE
+#define CONF_SERCOM_5_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_I2CS_ENABLE
+#define CONF_SERCOM_6_I2CS_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_I2CS_ENABLE
+#define CONF_SERCOM_7_I2CS_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as I2C Slave. */
+#define SERCOM_I2CS_AMOUNT                                                                                             \
+	(CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE     \
+	 + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE)
+
+/**
+ * \brief Macro is used to fill I2C slave configuration structure based on
+ * its number
+ *
+ * \param[in] n The number of structures
+ */
+#define I2CS_CONFIGURATION(n)                                                                                          \
+	{                                                                                                                  \
+		n,                                                                                                             \
+		    SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)     \
+		        | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD)                                            \
+		        | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)                                  \
+		        | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos)                                        \
+		        | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos),                                 \
+		    SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \
+		    (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos)                                             \
+		        | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS)                                                \
+		        | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos)                                   \
+		        | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK)                                       \
+	}
+
+/**
+ * \brief Macro to check 10-bit addressing
+ */
+#define I2CS_7BIT_ADDRESSING_MASK 0x7F
+
+static int32_t     _i2c_s_init(void *const hw);
+static int8_t      _get_i2c_s_index(const void *const hw);
+static inline void _i2c_s_deinit(void *const hw);
+static int32_t     _i2c_s_set_address(void *const hw, const uint16_t address);
+
+/**
+ * \brief SERCOM I2C slave configuration type
+ */
+struct i2cs_configuration {
+	uint8_t                    number;
+	hri_sercomi2cs_ctrla_reg_t ctrl_a;
+	hri_sercomi2cs_ctrlb_reg_t ctrl_b;
+	hri_sercomi2cs_addr_reg_t  address;
+};
+
+#if SERCOM_I2CS_AMOUNT < 1
+/** Dummy array for compiling. */
+static struct i2cs_configuration _i2css[1] = {{0}};
+#else
+/**
+ * \brief Array of SERCOM I2C slave configurations
+ */
+static struct i2cs_configuration _i2css[] = {
+#if CONF_SERCOM_0_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(0),
+#endif
+#if CONF_SERCOM_1_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(1),
+#endif
+#if CONF_SERCOM_2_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(2),
+#endif
+#if CONF_SERCOM_3_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(3),
+#endif
+#if CONF_SERCOM_4_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(4),
+#endif
+#if CONF_SERCOM_5_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(5),
+#endif
+#if CONF_SERCOM_6_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(6),
+#endif
+#if CONF_SERCOM_7_I2CS_ENABLE == 1
+    I2CS_CONFIGURATION(7),
+#endif
+};
+#endif
+
+/**
+ * \brief Initialize synchronous I2C slave
+ */
+int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw)
+{
+	int32_t status;
+
+	ASSERT(device);
+
+	status = _i2c_s_init(hw);
+	if (status) {
+		return status;
+	}
+	device->hw = hw;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize asynchronous I2C slave
+ */
+int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _i2c_s_init(hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	device->hw = hw;
+	_sercom_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	// Enable Address Match and PREC interrupt by default.
+	hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
+	hri_sercomi2cs_set_INTEN_PREC_bit(hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize synchronous I2C
+ */
+int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device)
+{
+	_i2c_s_deinit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize asynchronous I2C
+ */
+int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw));
+	_i2c_s_deinit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable I2C module
+ */
+int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable I2C module
+ */
+int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable I2C module
+ */
+int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable I2C module
+ */
+int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ */
+int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw);
+}
+
+/**
+ * \brief Check if 10-bit addressing mode is on
+ */
+int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device)
+{
+	return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw);
+}
+
+/**
+ * \brief Set I2C slave address
+ */
+int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address)
+{
+	return _i2c_s_set_address(device->hw, address);
+}
+
+/**
+ * \brief Set I2C slave address
+ */
+int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address)
+{
+	return _i2c_s_set_address(device->hw, address);
+}
+
+/**
+ * \brief Write a byte to the given I2C instance
+ */
+void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data)
+{
+	hri_sercomi2cs_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Write a byte to the given I2C instance
+ */
+void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data)
+{
+	hri_sercomi2cs_write_DATA_reg(device->hw, data);
+}
+
+/**
+ * \brief Read a byte from the given I2C instance
+ */
+uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_read_DATA_reg(device->hw);
+}
+
+/**
+ * \brief Check if I2C is ready to send next byt
+ */
+bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if there is data received by I2C
+ */
+bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve I2C slave status
+ */
+i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device)
+{
+	return hri_sercomi2cs_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Clear the Data Ready interrupt flag
+ */
+int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device)
+{
+	hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve I2C slave status
+ */
+i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device)
+{
+	return hri_sercomi2cs_read_STATUS_reg(device->hw);
+}
+
+/**
+ * \brief Abort data transmission
+ */
+int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device)
+{
+	hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable/disable I2C slave interrupt
+ */
+int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
+                                   const bool state)
+{
+	ASSERT(device);
+
+	if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) {
+		hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state);
+	} else if (I2C_S_DEVICE_ERROR == type) {
+		hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state);
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal Initalize i2c slave hardware
+ *
+ * \param[in] p The pointer to hardware instance
+ *
+ *\ return status of initialization
+ */
+static int32_t _i2c_s_init(void *const hw)
+{
+	int8_t i = _get_i2c_s_index(hw);
+	if (i == -1) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) {
+		uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk;
+		if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) {
+			hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE);
+		}
+		hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode);
+	}
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+
+	hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a);
+	hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b);
+	hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address);
+
+	return ERR_NONE;
+}
+
+/**
+ * \internal Retrieve ordinal number of the given sercom hardware instance
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2c_s_index(const void *const hw)
+{
+	uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_i2css); i++) {
+		if (_i2css[i].number == sercom_offset) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+/**
+ * \internal De-initialize i2c slave
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _i2c_s_deinit(void *const hw)
+{
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomi2cs_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \internal De-initialize i2c slave
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] address Address to set
+ */
+static int32_t _i2c_s_set_address(void *const hw, const uint16_t address)
+{
+	bool enabled;
+
+	enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw);
+
+	CRITICAL_SECTION_ENTER()
+	hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address);
+	CRITICAL_SECTION_LEAVE()
+
+	if (enabled) {
+		hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+	/* Sercom SPI implementation */
+
+#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2)
+#endif
+
+#define SPI_DEV_IRQ_MODE 0x8000
+
+#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF)
+#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF)
+
+COMPILER_PACK_SET(1)
+/** Initialization configuration of registers. */
+struct sercomspi_regs_cfg {
+	uint32_t ctrla;
+	uint32_t ctrlb;
+	uint32_t addr;
+	uint8_t  baud;
+	uint8_t  dbgctrl;
+	uint16_t dummy_byte;
+	uint8_t  n;
+};
+COMPILER_PACK_RESET()
+
+/** Build configuration from header macros. */
+#define SERCOMSPI_REGS(n)                                                                                              \
+	{                                                                                                                  \
+		(((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0))                      \
+		 | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO)       \
+		 | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos)                                                   \
+		 | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)                                           \
+		 | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */                                             \
+		    ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos)                                                 \
+		     | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos)                                             \
+		     | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos)                                               \
+		     | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos)                                         \
+		     | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE)                                                     \
+		     | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */                                     \
+		    (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR)                                                          \
+		     | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)),      /* addr */                              \
+		    ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE),                        /* baud */                              \
+		    (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */                           \
+		    CONF_SERCOM_##n##_SPI_DUMMYBYTE,                                   /* Dummy byte for SPI master mode */    \
+		    n                                                                  /* sercom number */                     \
+	}
+
+#ifndef CONF_SERCOM_0_SPI_ENABLE
+#define CONF_SERCOM_0_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_1_SPI_ENABLE
+#define CONF_SERCOM_1_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_2_SPI_ENABLE
+#define CONF_SERCOM_2_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_4_SPI_ENABLE
+#define CONF_SERCOM_4_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_5_SPI_ENABLE
+#define CONF_SERCOM_5_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_6_SPI_ENABLE
+#define CONF_SERCOM_6_SPI_ENABLE 0
+#endif
+#ifndef CONF_SERCOM_7_SPI_ENABLE
+#define CONF_SERCOM_7_SPI_ENABLE 0
+#endif
+
+/** Amount of SERCOM that is used as SPI */
+#define SERCOM_SPI_AMOUNT                                                                                              \
+	(CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE         \
+	 + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE)
+
+#if SERCOM_SPI_AMOUNT < 1
+/** Dummy array for compiling. */
+static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}};
+#else
+/** The SERCOM SPI configurations of SERCOM that is used as SPI. */
+static const struct sercomspi_regs_cfg sercomspi_regs[] = {
+#if CONF_SERCOM_0_SPI_ENABLE
+    SERCOMSPI_REGS(0),
+#endif
+#if CONF_SERCOM_1_SPI_ENABLE
+    SERCOMSPI_REGS(1),
+#endif
+#if CONF_SERCOM_2_SPI_ENABLE
+    SERCOMSPI_REGS(2),
+#endif
+#if CONF_SERCOM_3_SPI_ENABLE
+    SERCOMSPI_REGS(3),
+#endif
+#if CONF_SERCOM_4_SPI_ENABLE
+    SERCOMSPI_REGS(4),
+#endif
+#if CONF_SERCOM_5_SPI_ENABLE
+    SERCOMSPI_REGS(5),
+#endif
+#if CONF_SERCOM_6_SPI_ENABLE
+    SERCOMSPI_REGS(6),
+#endif
+#if CONF_SERCOM_7_SPI_ENABLE
+    SERCOMSPI_REGS(7),
+#endif
+};
+#endif
+
+/** \internal De-initialize SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return De-initialization status
+ */
+static int32_t _spi_deinit(void *const hw)
+{
+	hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+	hri_sercomspi_set_CTRLA_SWRST_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Enable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Enabling status
+ */
+static int32_t _spi_sync_enable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_set_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Enable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Enabling status
+ */
+static int32_t _spi_async_enable(void *const hw)
+{
+	_spi_sync_enable(hw);
+	NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	return ERR_NONE;
+}
+
+/** \internal Disable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Disabling status
+ */
+static int32_t _spi_sync_disable(void *const hw)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+	hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+
+	return ERR_NONE;
+}
+
+/** \internal Disable SERCOM SPI
+ *
+ *  \param[in] hw Pointer to the hardware register base.
+ *
+ * \return Disabling status
+ */
+static int32_t _spi_async_disable(void *const hw)
+{
+	_spi_sync_disable(hw);
+	hri_sercomspi_clear_INTEN_reg(
+	    hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE);
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI mode
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] mode The mode to set
+ *
+ * \return Setting mode status
+ */
+static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode)
+{
+	uint32_t ctrla;
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) {
+		return ERR_BUSY;
+	}
+
+	ctrla = hri_sercomspi_read_CTRLA_reg(hw);
+	ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA);
+	ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos;
+	hri_sercomspi_write_CTRLA_reg(hw, ctrla);
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI baudrate
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ *
+ * \return Setting baudrate status
+ */
+static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val)
+{
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_write_BAUD_reg(hw, baud_val);
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI char size
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ * \param[out] size Stored char size
+ *
+ * \return Setting char size status
+ */
+static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size)
+{
+	/* Only 8-bit or 9-bit accepted */
+	if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) {
+		return ERR_BUSY;
+	}
+
+	hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size);
+	*size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2;
+
+	return ERR_NONE;
+}
+
+/** \internal Set SERCOM SPI data order
+ *
+ * \param[in] hw Pointer to the hardware register base.
+ * \param[in] baud_val The baudrate to set
+ *
+ * \return Setting data order status
+ */
+static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord)
+{
+	uint32_t ctrla;
+
+	if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		return ERR_BUSY;
+	}
+
+	ctrla = hri_sercomspi_read_CTRLA_reg(hw);
+
+	if (dord == SPI_DATA_ORDER_LSB_1ST) {
+		ctrla |= SERCOM_SPI_CTRLA_DORD;
+	} else {
+		ctrla &= ~SERCOM_SPI_CTRLA_DORD;
+	}
+	hri_sercomspi_write_CTRLA_reg(hw, ctrla);
+
+	return ERR_NONE;
+}
+
+/** \brief Load SERCOM registers to init for SPI master mode
+ *  The settings will be applied with default master mode, unsupported things
+ *  are ignored.
+ *  \param[in, out] hw Pointer to the hardware register base.
+ *  \param[in] regs Pointer to register configuration values.
+ */
+static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs)
+{
+	ASSERT(hw && regs);
+	hri_sercomspi_write_CTRLA_reg(
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+	hri_sercomspi_write_CTRLB_reg(
+	    hw,
+	    (regs->ctrlb
+	     & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN))
+	        | (SERCOM_SPI_CTRLB_RXEN));
+	hri_sercomspi_write_BAUD_reg(hw, regs->baud);
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+}
+
+/** \brief Load SERCOM registers to init for SPI slave mode
+ *  The settings will be applied with default slave mode, unsupported things
+ *  are ignored.
+ *  \param[in, out] hw Pointer to the hardware register base.
+ *  \param[in] regs Pointer to register configuration values.
+ */
+static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs)
+{
+	ASSERT(hw && regs);
+	hri_sercomspi_write_CTRLA_reg(
+	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
+	hri_sercomspi_write_CTRLB_reg(hw,
+	                              (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
+	                                  | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
+	hri_sercomspi_write_ADDR_reg(hw, regs->addr);
+	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
+	while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
+		;
+}
+
+/** \brief Return the pointer to register settings of specific SERCOM
+ *  \param[in] hw_addr The hardware register base address.
+ *  \return Pointer to register settings of specific SERCOM.
+ */
+static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr)
+{
+	uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
+	uint8_t i;
+
+	for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) {
+		if (sercomspi_regs[i].n == n) {
+			return &sercomspi_regs[i];
+		}
+	}
+
+	return NULL;
+}
+
+int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
+{
+	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
+
+	ASSERT(dev && hw);
+
+	if (regs == NULL) {
+		return ERR_INVALID_ARG;
+	}
+
+	if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
+		uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
+		if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
+			hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
+			hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
+		}
+		hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
+	}
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+
+	dev->prvt = hw;
+
+	if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
+		_spi_load_regs_slave(hw, regs);
+	} else {
+		_spi_load_regs_master(hw, regs);
+	}
+
+	/* Load character size from default hardware configuration */
+	dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
+
+	dev->dummy_byte = regs->dummy_byte;
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw)
+{
+	return _spi_m_sync_init(dev, hw);
+}
+
+int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw)
+{
+	struct _spi_async_dev *spid = dev;
+	/* Do hardware initialize. */
+	int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw);
+
+	if (rc < 0) {
+		return rc;
+	}
+
+	_sercom_init_irq_param(hw, (void *)dev);
+	/* Initialize callbacks: must use them */
+	spid->callbacks.complete = NULL;
+	spid->callbacks.rx       = NULL;
+	spid->callbacks.tx       = NULL;
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw)
+{
+	return _spi_m_async_init(dev, hw);
+}
+
+int32_t _spi_m_async_deinit(struct _spi_async_dev *dev)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev)
+{
+	NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+	NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt));
+
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev)
+{
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev)
+{
+	return _spi_deinit(dev->prvt);
+}
+
+int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_enable(dev->prvt);
+}
+
+int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_enable(dev->prvt);
+}
+
+int32_t _spi_m_async_enable(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_enable(dev->prvt);
+}
+
+int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_enable(dev->prvt);
+}
+
+int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_disable(dev->prvt);
+}
+
+int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_sync_disable(dev->prvt);
+}
+
+int32_t _spi_m_async_disable(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_disable(dev->prvt);
+}
+
+int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_async_disable(dev->prvt);
+}
+
+int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_mode(dev->prvt, mode);
+}
+
+int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud)
+{
+	int32_t rc;
+	ASSERT(dev);
+
+	/* Not accept 0es */
+	if (clk == 0 || baud == 0) {
+		return ERR_INVALID_ARG;
+	}
+
+	/* Check baudrate range of current assigned clock */
+	if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) {
+		return ERR_INVALID_ARG;
+	}
+
+	rc = ((clk >> 1) / baud) - 1;
+	return rc;
+}
+
+int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_baudrate(dev->prvt, baud_val);
+}
+
+int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_baudrate(dev->prvt, baud_val);
+}
+
+int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_char_size(dev->prvt, char_size, &dev->char_size);
+}
+
+int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord)
+{
+	ASSERT(dev && dev->prvt);
+
+	return _spi_set_data_order(dev->prvt, dord);
+}
+
+/** Wait until SPI bus idle. */
+static inline void _spi_wait_bus_idle(void *const hw)
+{
+	while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
+		;
+	}
+	hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE);
+}
+
+/** Holds run time information for message sync transaction. */
+struct _spi_trans_ctrl {
+	/** Pointer to transmitting data buffer. */
+	uint8_t *txbuf;
+	/** Pointer to receiving data buffer. */
+	uint8_t *rxbuf;
+	/** Count number of data transmitted. */
+	uint32_t txcnt;
+	/** Count number of data received. */
+	uint32_t rxcnt;
+	/** Data character size. */
+	uint8_t char_size;
+};
+
+/** Check interrupt flag of RXC and update transaction runtime information. */
+static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl)
+{
+	uint32_t data;
+
+	if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
+		return false;
+	}
+
+	data = hri_sercomspi_read_DATA_reg(hw);
+
+	if (ctrl->rxbuf) {
+		*ctrl->rxbuf++ = (uint8_t)data;
+
+		if (ctrl->char_size > 1) {
+			*ctrl->rxbuf++ = (uint8_t)(data >> 8);
+		}
+	}
+
+	ctrl->rxcnt++;
+
+	return true;
+}
+
+/** Check interrupt flag of DRE and update transaction runtime information. */
+static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl,
+                                          uint16_t dummy)
+{
+	uint32_t data;
+
+	if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
+		return;
+	}
+
+	if (ctrl->txbuf) {
+		data = *ctrl->txbuf++;
+
+		if (ctrl->char_size > 1) {
+			data |= (*ctrl->txbuf) << 8;
+			ctrl->txbuf++;
+		}
+	} else {
+		data = dummy;
+	}
+
+	ctrl->txcnt++;
+	hri_sercomspi_write_DATA_reg(hw, data);
+}
+
+/** Check interrupt flag of ERROR and update transaction runtime information. */
+static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw)
+{
+	if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
+		hri_sercomspi_clear_STATUS_reg(hw, ~0);
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR);
+		return ERR_OVERFLOW;
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
+{
+	void *                 hw   = dev->prvt;
+	int32_t                rc   = 0;
+	struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
+
+	ASSERT(dev && hw);
+
+	/* If settings are not applied (pending), we can not go on */
+	if (hri_sercomspi_is_syncing(
+	        hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
+		return ERR_BUSY;
+	}
+
+	/* SPI must be enabled to start synchronous transfer */
+	if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
+		return ERR_NOT_INITIALIZED;
+	}
+
+	for (;;) {
+		uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
+
+		if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
+			/* In master mode, do not start next byte before previous byte received
+			 * to make better output waveform */
+			if (ctrl.rxcnt >= ctrl.txcnt) {
+				_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
+			}
+		}
+
+		rc = _spi_err_check(iflag, hw);
+
+		if (rc < 0) {
+			break;
+		}
+		if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
+			rc = ctrl.txcnt;
+			break;
+		}
+	}
+	/* Wait until SPI bus idle */
+	_spi_wait_bus_idle(hw);
+
+	return rc;
+}
+
+int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_DRE_bit(hw);
+	} else {
+		hri_sercomspi_clear_INTEN_DRE_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_tx(dev, state);
+}
+
+int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev);
+	ASSERT(hw);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_RXC_bit(hw);
+	} else {
+		hri_sercomspi_clear_INTEN_RXC_bit(hw);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_rx(dev, state);
+}
+
+int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state)
+{
+	ASSERT(dev && dev->prvt);
+
+	if (state) {
+		hri_sercomspi_set_INTEN_TXC_bit(dev->prvt);
+	} else {
+		hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt);
+	}
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state)
+{
+	return _spi_m_async_enable_tx_complete(dev, state);
+}
+
+int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data)
+{
+	ASSERT(dev && dev->prvt);
+
+	hri_sercomspi_write_DATA_reg(dev->prvt, data);
+
+	return ERR_NONE;
+}
+
+uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomspi_read_DATA_reg(dev->prvt);
+}
+
+int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func)
+{
+	typedef void (*func_t)(void);
+	struct _spi_async_dev *spid = dev;
+
+	ASSERT(dev && (cb_type < SPI_DEV_CB_N));
+
+	func_t *p_ls  = (func_t *)&spid->callbacks;
+	p_ls[cb_type] = (func_t)func;
+
+	return ERR_NONE;
+}
+
+int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
+                                       const FUNC_PTR func)
+{
+	return _spi_m_async_register_callback(dev, cb_type, func);
+}
+
+bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE);
+}
+
+bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev)
+{
+	ASSERT(dev && dev->prvt);
+
+	return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC);
+}
+
+bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) {
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC);
+		return true;
+	}
+	return false;
+}
+
+bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev)
+{
+	void *hw = dev->prvt;
+
+	ASSERT(dev && hw);
+
+	if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) {
+		hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF);
+		hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR);
+		return true;
+	}
+	return false;
+}
+
+/**
+ * \brief Enable/disable SPI master interrupt
+ *
+ * param[in] device The pointer to SPI master device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state)
+{
+	ASSERT(device);
+
+	if (SPI_DEV_CB_ERROR == type) {
+		hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state);
+	}
+}
+
+/**
+ * \brief Enable/disable SPI slave interrupt
+ *
+ * param[in] device The pointer to SPI slave device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] state Enable or disable
+ */
+void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type,
+                                const bool state)
+{
+	_spi_m_async_set_irq_state(device, type, state);
+}
diff --git a/Smol Watch Project/My Project/hpl/slcd/hpl_slcd.c b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd.c
new file mode 100644
index 0000000..f8f42bd
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd.c	
@@ -0,0 +1,336 @@
+/**
+ * \file
+ *
+ * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
+ *        Implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+#include <hpl_slcd_sync.h>
+#include <hpl_slcd_config.h>
+#include <hpl_slcd_cm_7_seg_mapping.h>
+#include <hpl_slcd_cm_14_seg_mapping.h>
+
+static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg,
+                                      const bool on);
+
+/**
+ * \brief SLCD configuration type
+ */
+struct slcd_configuration {
+	hri_slcd_ctrla_reg_t ctrla; /*!< Control A Register */
+	hri_slcd_ctrlb_reg_t ctrlb; /*!< Control B Register */
+	hri_slcd_ctrlc_reg_t ctrlc; /*!< Control C Register */
+	hri_slcd_ctrld_reg_t ctrld; /*!< Control D Register */
+};
+
+/**
+ * \brief Array of AC configurations
+ */
+static struct slcd_configuration _slcd
+    = {SLCD_CTRLA_DUTY(CONF_SLCD_COM_NUM) | CONF_SLCD_WMOD << SLCD_CTRLA_WMOD_Pos
+           | CONF_SLCD_RUNSTDBY << SLCD_CTRLA_RUNSTDBY_Pos | SLCD_CTRLA_PRESC(CONF_SLCD_PRESC)
+           | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
+           | CONF_SLCD_XVLCD << SLCD_CTRLA_XVLCD_Pos | SLCD_CTRLA_PRF(CONF_SLCD_PRF) | SLCD_CTRLA_RRF(CONF_SLCD_RRF),
+       CONF_SLCD_BBEN << SLCD_CTRLB_BBEN_Pos | SLCD_CTRLB_BBD(CONF_SLCD_BBD - 1),
+       SLCD_CTRLC_CTST(CONF_SLCD_CONTRAST_ADJUST),
+       SLCD_CTRLD_DISPEN};
+static const struct slcd_char_setting cm_setting[] = SLCD_CHAR_SETTING_TABLE;
+static const struct slcd_char_mapping cm7_lut[]    = SLCD_SEG7_LUT;
+static const struct slcd_char_mapping cm14_lut[]   = SLCD_SEG14_LUT;
+/**
+ * \brief              Initialize SLCD Device Descriptor
+ */
+int32_t _slcd_sync_init(struct _slcd_sync_device *dev, void *const hw)
+{
+	if (!hri_slcd_is_syncing(hw, SLCD_SYNCBUSY_SWRST)) {
+		if (hri_slcd_get_CTRLA_ENABLE_bit(hw)) {
+			hri_slcd_clear_CTRLA_ENABLE_bit(hw);
+			hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_ENABLE);
+		}
+		hri_slcd_write_CTRLA_reg(hw, SLCD_CTRLA_SWRST);
+	}
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
+
+	dev->hw = hw;
+	hri_slcd_write_CTRLA_reg(hw, _slcd.ctrla);
+	hri_slcd_write_CTRLB_reg(hw, _slcd.ctrlb);
+	hri_slcd_write_CTRLC_reg(hw, _slcd.ctrlc);
+	hri_slcd_write_CTRLD_reg(hw, _slcd.ctrld);
+	hri_slcd_write_LPENL_reg(hw, CONF_SLCD_LPENL);
+	hri_slcd_write_LPENH_reg(hw, CONF_SLCD_LPENH);
+	hri_slcd_write_SDATAL0_reg(hw, 0);
+	hri_slcd_write_SDATAH0_reg(hw, 0);
+	hri_slcd_write_SDATAL1_reg(hw, 0);
+	hri_slcd_write_SDATAH1_reg(hw, 0);
+	hri_slcd_write_SDATAL2_reg(hw, 0);
+	hri_slcd_write_SDATAH2_reg(hw, 0);
+	hri_slcd_write_SDATAL3_reg(hw, 0);
+	hri_slcd_write_SDATAH3_reg(hw, 0);
+	hri_slcd_write_SDATAL4_reg(hw, 0);
+	hri_slcd_write_SDATAH4_reg(hw, 0);
+	hri_slcd_write_SDATAL5_reg(hw, 0);
+	hri_slcd_write_SDATAH5_reg(hw, 0);
+	hri_slcd_write_SDATAL6_reg(hw, 0);
+	hri_slcd_write_SDATAH6_reg(hw, 0);
+	hri_slcd_write_SDATAL7_reg(hw, 0);
+	hri_slcd_write_SDATAH7_reg(hw, 0);
+	hri_slcd_set_BCFG_MODE_bit(dev->hw);
+	return ERR_NONE;
+}
+
+/**
+ * \brief              DeInitialize SLCD Device Descriptor
+ */
+int32_t _slcd_sync_deinit(struct _slcd_sync_device *dev)
+{
+	hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE);
+	hri_slcd_set_CTRLA_SWRST_bit(dev->hw);
+	dev->hw = NULL;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief              Enable SLCD driver
+ *
+ * \param[in] dev      SLCD device descriptor to be enabled
+ */
+int32_t _slcd_sync_enable(struct _slcd_sync_device *dev)
+{
+	hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
+	return ERR_NONE;
+}
+
+/**
+ * \brief              Disable SLCD driver
+ */
+int32_t _slcd_sync_disable(struct _slcd_sync_device *dev)
+{
+	hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
+	return ERR_NONE;
+}
+
+/**
+ * \brief               Turn on a Segment
+ */
+int32_t _slcd_sync_seg_on(struct _slcd_sync_device *dev, uint32_t seg)
+{
+	return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true);
+}
+
+/**
+ * \brief               Turn off a Segment
+ */
+int32_t _slcd_sync_seg_off(struct _slcd_sync_device *dev, uint32_t seg)
+{
+	return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), false);
+}
+
+/**
+ * \brief               Blink a Segment
+ */
+int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *dev, uint32_t seg, const uint32_t period)
+{
+	if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) {
+		return ERR_INVALID_ARG;
+	}
+	/* COM[0..7], Seg[0,1] support blink */
+	if (SLCD_SEGNUM(seg) >= 2) {
+		return ERR_INVALID_ARG;
+	}
+	/* Verify period */
+	if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) {
+		return ERR_INVALID_ARG;
+	}
+	/* Set Period, use Frame Counter 0 for blink */
+	hri_slcd_clear_CTRLD_FC0EN_bit(dev->hw);
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
+	if (period <= SLCD_FC_BYPASS_MAX_MS) {
+		hri_slcd_set_FC0_reg(dev->hw, SLCD_FC0_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1));
+	} else {
+		hri_slcd_set_FC0_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)));
+	}
+	hri_slcd_set_CTRLD_FC0EN_bit(dev->hw);
+
+	/* Set Blink Segments */
+	_slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true);
+	hri_slcd_clear_CTRLD_BLINK_bit(dev->hw);
+
+	hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE);
+
+	/* Update BCFG */
+	if (SLCD_SEGNUM(seg) == 0) {
+		hri_slcd_set_BCFG_BSS0_bf(dev->hw, 1 << SLCD_COMNUM(seg));
+	} else {
+		hri_slcd_set_BCFG_BSS1_bf(dev->hw, 1 << SLCD_COMNUM(seg));
+	}
+	hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
+	hri_slcd_set_CTRLD_BLINK_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief              Displays a character
+ */
+int32_t _slcd_sync_write_char(struct _slcd_sync_device *dev, const uint8_t character, uint32_t index)
+{
+	uint32_t i;
+	uint32_t data = ~0;
+	if (cm_setting[index].size == 7) {
+		for (i = 0; i<sizeof(cm7_lut)>> 2; i++) {
+			if (cm7_lut[i].character == character) {
+				data = cm7_lut[i].mapping;
+				break;
+			}
+		}
+	} else if (cm_setting[index].size == 14) {
+		for (i = 0; i<sizeof(cm14_lut)>> 2; i++) {
+			if (cm14_lut[i].character == character) {
+				data = cm14_lut[i].mapping;
+				break;
+			}
+		}
+	}
+	if (data == 0xFFFFFFFF) {
+		return ERR_INVALID_ARG;
+	}
+
+	hri_slcd_write_CMCFG_NSEG_bf(dev->hw, cm_setting[index].nseg);
+	hri_slcd_write_CMINDEX_CINDEX_bf(dev->hw, cm_setting[index].com_index);
+	hri_slcd_write_CMINDEX_SINDEX_bf(dev->hw, cm_setting[index].seg_index);
+
+	if (cm_setting[index].size == 7) {
+		hri_slcd_write_CMDMASK_reg(dev->hw, SEG7_MASK);
+	} else if (cm_setting[index].size == 14) {
+		hri_slcd_write_CMDMASK_reg(dev->hw, SEG14_MASK);
+	}
+	while (hri_slcd_get_STATUS_CMWRBUSY_bit(dev->hw))
+		;
+	hri_slcd_write_CMDATA_reg(dev->hw, data);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief               Start animation play by a segment array
+ */
+int32_t _slcd_sync_start_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len,
+                                   const uint32_t period)
+{
+	uint32_t i;
+	uint32_t csrlen = 0;
+	if (len > 16) {
+		return ERR_INVALID_ARG;
+	}
+	/* COM[0..7], Seg[2,3] support animation */
+	for (i = 0; i < len; i++) {
+		if ((SLCD_SEGNUM(segs[i]) != 2 && SLCD_SEGNUM(segs[i]) != 3)) {
+			return ERR_INVALID_ARG;
+		}
+	}
+	/* Verify period */
+	if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) {
+		return ERR_INVALID_ARG;
+	}
+	/* Set Period */
+	_slcd_sync_set_animation_period(dev, period);
+
+	/* Set animation segments */
+	hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw);
+	hri_slcd_clear_CTRLD_CSREN_bit(dev->hw);
+
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE | SLCD_SYNCBUSY_CTRLD);
+	hri_slcd_set_CSRCFG_FCS_bf(dev->hw, 1);
+	hri_slcd_write_CSRCFG_DATA_bf(dev->hw, 0);
+	for (i = 0; i < len; i++) {
+		hri_slcd_set_CSRCFG_DATA_bf(dev->hw, (1 << ((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2))));
+		if (((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)) > csrlen) {
+			csrlen = (SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2);
+		}
+	}
+	hri_slcd_set_CSRCFG_SIZE_bf(dev->hw, csrlen + 1);
+	hri_slcd_set_BCFG_MODE_bit(dev->hw);
+	hri_slcd_set_CTRLD_CSREN_bit(dev->hw);
+	hri_slcd_set_CTRLA_ENABLE_bit(dev->hw);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief               Stop animation play by a segment array
+ */
+int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len)
+{
+	/* Not used because of the current version is not supported, Reserved */
+	(void)segs;
+	(void)len;
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
+	hri_slcd_clear_CTRLD_CSREN_bit(dev->hw);
+	return ERR_NONE;
+}
+
+/**
+ * \brief               Set animation Frequency
+ */
+int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *dev, const uint32_t period)
+{
+	hri_slcd_clear_CTRLD_FC1EN_bit(dev->hw);
+	hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD);
+	/* Use Frame Counter 1 for blink */
+	if (period <= SLCD_FC_BYPASS_MAX_MS) {
+		hri_slcd_set_FC1_reg(dev->hw, SLCD_FC1_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1));
+	} else {
+		hri_slcd_set_FC1_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)));
+	}
+	hri_slcd_set_CTRLD_FC1EN_bit(dev->hw);
+	return ERR_NONE;
+}
+
+static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg,
+                                      const bool on)
+{
+	if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) {
+		return ERR_INVALID_ARG;
+	}
+	/* Use register instead hri interface to optimization code */
+	if (on) {
+		((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)]
+		    |= (seg < 32) ? (1 << seg) : (1 << (seg >> 5));
+	} else {
+		((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)]
+		    &= ~((seg < 32) ? (1 << seg) : (1 << (seg >> 5)));
+	}
+
+	return ERR_NONE;
+}
diff --git a/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm.h b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm.h
new file mode 100644
index 0000000..66dbde9
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm.h	
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief SLCD Character Mapping declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HPL_SLCD_CM_H_INCLUDED
+#define HPL_SLCD_CM_H_INCLUDED
+
+#include <stdint.h>
+
+/* Character Mapping Struct */
+struct slcd_char_mapping {
+	uint32_t character : 8; /*!< ASCII character */
+	uint32_t mapping : 24;  /*!< Mapping value */
+};
+
+/* SLCD Character settting Struct */
+struct slcd_char_setting {
+	uint8_t com_index; /*!< Common terminal index, start from 0 */
+	uint8_t seg_index; /*!< Segment terminal index, start from 0 */
+	uint8_t nseg;      /*!< Number of Segment, this field is used to
+	                        indentify which segments line will be
+	                        used. For example, if char mapping from
+	                        COM1/SEG2 and nseg=2,size=7, then
+	                        COM1/SEG2, COM1/SEG3, COM2/SEG2,
+	                        COM2/SEG3, COM3/SEG2, COM3/SEG3,
+	                        COM4/SEG2 will be used for mapping
+	                        */
+	uint8_t size;      /*!< char size, typical is 7/14/16 */
+};
+#endif /* HPL_SLCD_CM_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_14_seg_mapping.h b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_14_seg_mapping.h
new file mode 100644
index 0000000..65777d6
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_14_seg_mapping.h	
@@ -0,0 +1,104 @@
+#include <hpl_slcd_config.h>
+
+/**
+ * character segments position index
+ *
+ * For a 14-segments character, each segment has an unique position index.
+ * The segment layout and position index value is shown as below.
+ * The symbol '-', '|', '/', '\' represent the SLCD character segment, and the
+ * number represent each segment's position index, which equals to macro
+ * SEG14_0 to SEG14_7.
+ * The character lookup mapping table use those position index
+ * (SEG14_0..SEG14_14) to compose some visible arabic numerals, letters or some
+ * specific ASCII.
+ * For example char '1' can be represented by use position index 1,2.
+ * (SEG7_1 | SEG7_2).
+ * More predefined character lookup can be found at below "14-segment character
+ * lookup mapping table"
+ *
+ *         -0
+ * |5  \6  |7  /8  |1
+ *     -9      -10
+ * |4  /11 |12 \13 |2
+ *         -3
+ */
+
+/**
+ * Character segment position remapping setting
+ *
+ * An SLCD screen typically use several hardware segments to display a
+ * character(for example from COM3/SEG0 to COM4/SEG7).
+ * The lowest COM and SEG index is 0 (COM3/SEG0 index is 0).
+ * The "hardware character segments index" maybe different with the "character
+ * segments position index". The remapping setting allow application to adjust
+ * those sequence.
+ *
+ */
+#define SEG14_0 (0x1 << CONF_SLCD_CM_14SEGS_0_SETTING)
+#define SEG14_1 (0x1 << CONF_SLCD_CM_14SEGS_1_SETTING)
+#define SEG14_2 (0x1 << CONF_SLCD_CM_14SEGS_2_SETTING)
+#define SEG14_3 (0x1 << CONF_SLCD_CM_14SEGS_3_SETTING)
+#define SEG14_4 (0x1 << CONF_SLCD_CM_14SEGS_4_SETTING)
+#define SEG14_5 (0x1 << CONF_SLCD_CM_14SEGS_5_SETTING)
+#define SEG14_6 (0x1 << CONF_SLCD_CM_14SEGS_6_SETTING)
+#define SEG14_7 (0x1 << CONF_SLCD_CM_14SEGS_7_SETTING)
+#define SEG14_8 (0x1 << CONF_SLCD_CM_14SEGS_8_SETTING)
+#define SEG14_9 (0x1 << CONF_SLCD_CM_14SEGS_9_SETTING)
+#define SEG14_10 (0x1 << CONF_SLCD_CM_14SEGS_10_SETTING)
+#define SEG14_11 (0x1 << CONF_SLCD_CM_14SEGS_11_SETTING)
+#define SEG14_12 (0x1 << CONF_SLCD_CM_14SEGS_12_SETTING)
+#define SEG14_13 (0x1 << CONF_SLCD_CM_14SEGS_13_SETTING)
+
+/**
+ * 17-segments character mask value
+ */
+#define SEG14_MASK                                                                                                     \
+	(0xFFFFFF                                                                                                          \
+	 & ~(SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_6 | SEG14_7 | SEG14_8 | SEG14_9 | SEG14_10  \
+	     | SEG14_11 | SEG14_12 | SEG14_13))
+
+/**
+ * 14-segment character lookup mapping table
+ * struct slcd_char_mapping;
+ */
+#define SLCD_SEG14_LUT                                                                                                 \
+	{                                                                                                                  \
+		{'0', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_8 | SEG14_11},                         \
+		    {'1', SEG14_1 | SEG14_2}, {'2', SEG14_0 | SEG14_1 | SEG14_3 | SEG14_4 | SEG14_9 | SEG14_10},               \
+		    {'3', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_9 | SEG14_10},                                         \
+		    {'4', SEG14_1 | SEG14_2 | SEG14_5 | SEG14_9 | SEG14_10},                                                   \
+		    {'5', SEG14_0 | SEG14_2 | SEG14_3 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'6', SEG14_0 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                               \
+		    {'7', SEG14_0 | SEG14_1 | SEG14_2},                                                                        \
+		    {'8', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                     \
+		    {'9', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_5 | SEG14_9 | SEG14_10},                               \
+		    {'a', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                               \
+		    {'b', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_7 | SEG14_10 | SEG14_12},                              \
+		    {'c', SEG14_0 | SEG14_3 | SEG14_4 | SEG14_5},                                                              \
+		    {'d', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_7 | SEG14_12},                                         \
+		    {'e', SEG14_0 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'f', SEG14_0 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                                                   \
+		    {'g', SEG14_0 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_10},                                         \
+		    {'h', SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'i', SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'j', SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4}, {'k', SEG14_4 | SEG14_5 | SEG14_8 | SEG14_9 | SEG14_13},     \
+		    {'l', SEG14_3 | SEG14_4 | SEG14_5}, {'m', SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_6 | SEG14_8},      \
+		    {'n', SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_6 | SEG14_13},                                         \
+		    {'o', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5},                                          \
+		    {'p', SEG14_0 | SEG14_1 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'q', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5 | SEG14_13},                               \
+		    {'r', SEG14_0 | SEG14_1 | SEG14_4 | SEG14_5 | SEG14_9 | SEG14_10 | SEG14_13},                              \
+		    {'s', SEG14_0 | SEG14_3 | SEG14_5 | SEG14_9 | SEG14_13}, {'t', SEG14_0 | SEG14_7 | SEG14_12},              \
+		    {'u', SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_5}, {'v', SEG14_4 | SEG14_5 | SEG14_8 | SEG14_11},     \
+		    {'w', SEG14_1 | SEG14_2 | SEG14_4 | SEG14_5 | SEG14_11 | SEG14_13},                                        \
+		    {'x', SEG14_6 | SEG14_8 | SEG14_11 | SEG14_13},                                                            \
+		    {'y', SEG14_1 | SEG14_2 | SEG14_3 | SEG14_5 | SEG14_9 | SEG14_10},                                         \
+		    {'z', SEG14_0 | SEG14_3 | SEG14_8 | SEG14_11}, {'-', SEG14_9 | SEG14_10},                                  \
+		    {'+', SEG14_7 | SEG14_9 | SEG14_10 | SEG14_12}, {'/', SEG14_8 | SEG14_11},                                 \
+		    {'=', SEG14_3 | SEG14_9 | SEG14_10},                                                                       \
+		    {'#', SEG14_1 | SEG14_2 | SEG14_3 | SEG14_7 | SEG14_9 | SEG14_10 | SEG14_12},                              \
+		    {'*', SEG14_6 | SEG14_8 | SEG14_11 | SEG14_13}, {'\'', SEG14_13}, {')', SEG14_6 | SEG14_11},               \
+		    {'(', SEG14_8 | SEG14_13}, {'@', SEG14_0 | SEG14_1 | SEG14_2 | SEG14_3 | SEG14_4 | SEG14_9 | SEG14_13},    \
+		    {'$', SEG14_0 | SEG14_2 | SEG14_3 | SEG14_5 | SEG14_7 | SEG14_9 | SEG14_10 | SEG14_12},                    \
+		    {'%', SEG14_2 | SEG14_5 | SEG14_8 | SEG14_11}, {'\\', SEG14_6 | SEG14_13}, {'_', SEG14_3}, {0, 0},         \
+	}
diff --git a/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_7_seg_mapping.h b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_7_seg_mapping.h
new file mode 100644
index 0000000..eae344c
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/slcd/hpl_slcd_cm_7_seg_mapping.h	
@@ -0,0 +1,68 @@
+#include <hpl_slcd_config.h>
+
+/**
+ * character segments position index
+ *
+ * For a 7 segments character, each segment has an unique position index.
+ * The segment layout and position index value is shown as below.
+ * The symbol '-', '|' represent the SLCD character segment, and the
+ * number represent each segment's position index, which equals to macro
+ * SEG7_0 to SEG7_7.
+ * The character lookup mapping table use those position index (SEG7_0..SEG7_7)
+ * to compose some visible arabic numerals, letters or some specific ASCII.
+ * For example char '0' can be represented by use position index 0,1,2,3,4,5.
+ * (SEG7_0 | SEG7_1 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5).
+ * More predefined character lookup can be found at below "7-segments character
+ * lookup mapping table"
+ *   -0
+ * |5   |1
+ *   -6
+ * |4   |2
+ *   -3
+ */
+
+/**
+ * Character segment position remapping setting
+ *
+ * An SLCD screen typically use several hardware segments to display a
+ * character(for example from COM3/SEG0 to COM3/SEG7).
+ * The lowest COM and SEG index is 0 (COM3/SEG0 index is 0).
+ * The "hardware character segments index" maybe different with the "character
+ * segments position index". The remapping setting allow application to adjust
+ * those sequence.
+ *
+ */
+#define SEG7_0 (0x1 << CONF_SLCD_CM_7SEGS_0_SETTING)
+#define SEG7_1 (0x1 << CONF_SLCD_CM_7SEGS_1_SETTING)
+#define SEG7_2 (0x1 << CONF_SLCD_CM_7SEGS_2_SETTING)
+#define SEG7_3 (0x1 << CONF_SLCD_CM_7SEGS_3_SETTING)
+#define SEG7_4 (0x1 << CONF_SLCD_CM_7SEGS_4_SETTING)
+#define SEG7_5 (0x1 << CONF_SLCD_CM_7SEGS_5_SETTING)
+#define SEG7_6 (0x1 << CONF_SLCD_CM_7SEGS_6_SETTING)
+
+/**
+ * 7-segments character mask value
+ */
+#define SEG7_MASK (0xFFFFFF & ~(SEG7_0 | SEG7_1 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5 | SEG7_6))
+
+/**
+ * 7-segments character lookup mapping table.
+ *
+ * Array value of slcd_char_mapping struct, application can add or remove
+ * item from it.
+ */
+#define SLCD_SEG7_LUT                                                                                                  \
+	{                                                                                                                  \
+		{0, 0}, {'0', SEG7_0 | SEG7_1 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5}, {'1', SEG7_1 | SEG7_2},                    \
+		    {'2', SEG7_0 | SEG7_1 | SEG7_3 | SEG7_4 | SEG7_6}, {'3', SEG7_0 | SEG7_1 | SEG7_2 | SEG7_3 | SEG7_6},      \
+		    {'4', SEG7_1 | SEG7_2 | SEG7_5 | SEG7_6}, {'5', SEG7_0 | SEG7_2 | SEG7_3 | SEG7_5 | SEG7_6},               \
+		    {'6', SEG7_0 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5 | SEG7_6}, {'7', SEG7_0 | SEG7_1 | SEG7_2},               \
+		    {'8', SEG7_0 | SEG7_1 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5 | SEG7_6},                                       \
+		    {'9', SEG7_0 | SEG7_1 | SEG7_2 | SEG7_5 | SEG7_6},                                                         \
+		    {'a', SEG7_0 | SEG7_1 | SEG7_2 | SEG7_4 | SEG7_5 | SEG7_6},                                                \
+		    {'b', SEG7_2 | SEG7_3 | SEG7_4 | SEG7_5 | SEG7_6}, {'c', SEG7_0 | SEG7_3 | SEG7_4 | SEG7_5},               \
+		    {'d', SEG7_1 | SEG7_2 | SEG7_3 | SEG7_4 | SEG7_6}, {'e', SEG7_0 | SEG7_3 | SEG7_4 | SEG7_5 | SEG7_6},      \
+		{                                                                                                              \
+			'f', SEG7_0 | SEG7_4 | SEG7_5 | SEG7_6                                                                     \
+		}                                                                                                              \
+	}
diff --git a/Smol Watch Project/My Project/hpl/systick/hpl_systick.c b/Smol Watch Project/My Project/hpl/systick/hpl_systick.c
new file mode 100644
index 0000000..3caf674
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/systick/hpl_systick.c	
@@ -0,0 +1,103 @@
+
+/**
+ * \file
+ *
+ * \brief SysTick related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_time_measure.h>
+#include <hpl_systick_config.h>
+
+/**
+ * \brief Initialize system time module
+ */
+void _system_time_init(void *const hw)
+{
+	(void)hw;
+	SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos);
+	SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos)
+	                | (1 << SysTick_CTRL_CLKSOURCE_Pos);
+}
+/**
+ * \brief Initialize delay functionality
+ */
+void _delay_init(void *const hw)
+{
+	_system_time_init(hw);
+}
+
+/**
+ * \brief De-initialize system time module
+ */
+void _system_time_deinit(void *const hw)
+{
+	(void)hw;
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * \brief Get system time
+ */
+system_time_t _system_time_get(const void *const hw)
+{
+	(void)hw;
+	return (system_time_t)SysTick->VAL;
+}
+
+/**
+ * \brief Get maximum possible system time
+ */
+system_time_t _system_time_get_max_time_value(const void *const hw)
+{
+	(void)hw;
+	return 0xFFFFFF;
+}
+/**
+ * \brief Delay loop to delay n number of cycles
+ */
+void _delay_cycles(void *const hw, uint32_t cycles)
+{
+	(void)hw;
+	uint8_t  n   = cycles >> 24;
+	uint32_t buf = cycles;
+
+	while (n--) {
+		SysTick->LOAD = 0xFFFFFF;
+		SysTick->VAL  = 0xFFFFFF;
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk))
+			;
+		buf -= 0xFFFFFF;
+	}
+
+	SysTick->LOAD = buf;
+	SysTick->VAL  = buf;
+	while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk))
+		;
+}
diff --git a/Smol Watch Project/My Project/hpl/tc/hpl_tc.c b/Smol Watch Project/My Project/hpl/tc/hpl_tc.c
new file mode 100644
index 0000000..38fa893
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/tc/hpl_tc.c	
@@ -0,0 +1,374 @@
+
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_pwm.h>
+#include <hpl_tc_config.h>
+#include <hpl_timer.h>
+#include <utils.h>
+#include <utils_assert.h>
+#include <hpl_tc_base.h>
+
+#ifndef CONF_TC0_ENABLE
+#define CONF_TC0_ENABLE 0
+#endif
+#ifndef CONF_TC1_ENABLE
+#define CONF_TC1_ENABLE 0
+#endif
+#ifndef CONF_TC2_ENABLE
+#define CONF_TC2_ENABLE 0
+#endif
+#ifndef CONF_TC3_ENABLE
+#define CONF_TC3_ENABLE 0
+#endif
+#ifndef CONF_TC4_ENABLE
+#define CONF_TC4_ENABLE 0
+#endif
+#ifndef CONF_TC5_ENABLE
+#define CONF_TC5_ENABLE 0
+#endif
+#ifndef CONF_TC6_ENABLE
+#define CONF_TC6_ENABLE 0
+#endif
+#ifndef CONF_TC7_ENABLE
+#define CONF_TC7_ENABLE 0
+#endif
+
+/**
+ * \brief Macro is used to fill usart configuration structure based on its
+ * number
+ *
+ * \param[in] n The number of structures
+ */
+#define TC_CONFIGURATION(n)                                                                                            \
+	{                                                                                                                  \
+		n, TC##n##_IRQn,                                                                                               \
+		    TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC)                              \
+		        | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos)  \
+		        | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos),             \
+		    (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos)                    \
+		        | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos)            \
+		        | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos),           \
+		    (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1,      \
+	}
+/**
+ * \brief TC configuration type
+ */
+struct tc_configuration {
+	uint8_t                number;
+	IRQn_Type              irq;
+	hri_tc_ctrla_reg_t     ctrl_a;
+	hri_tc_evctrl_reg_t    event_ctrl;
+	hri_tc_dbgctrl_reg_t   dbg_ctrl;
+	hri_tccount8_per_reg_t per;
+	hri_tccount32_cc_reg_t cc0;
+	hri_tccount32_cc_reg_t cc1;
+};
+
+/**
+ * \brief Array of TC configurations
+ */
+static struct tc_configuration _tcs[] = {
+#if CONF_TC0_ENABLE == 1
+    TC_CONFIGURATION(0),
+#endif
+#if CONF_TC1_ENABLE == 1
+    TC_CONFIGURATION(1),
+#endif
+#if CONF_TC2_ENABLE == 1
+    TC_CONFIGURATION(2),
+#endif
+#if CONF_TC3_ENABLE == 1
+    TC_CONFIGURATION(3),
+#endif
+#if CONF_TC4_ENABLE == 1
+    TC_CONFIGURATION(4),
+#endif
+#if CONF_TC5_ENABLE == 1
+    TC_CONFIGURATION(5),
+#endif
+#if CONF_TC6_ENABLE == 1
+    TC_CONFIGURATION(6),
+#endif
+#if CONF_TC7_ENABLE == 1
+    TC_CONFIGURATION(7),
+#endif
+};
+/**
+ * \brief Set of pointer to hal_pwm helper functions
+ */
+static struct _pwm_hpl_interface _tc_pwm_functions = {
+    _tc_pwm_init,
+    _tc_pwm_deinit,
+    _tc_start_pwm,
+    _tc_stop_pwm,
+    _tc_set_pwm_param,
+    _tc_is_pwm_enabled,
+    _tc_pwm_get_period,
+    _tc_pwm_get_duty,
+    _tc_pwm_set_irq_state,
+};
+
+static struct _pwm_device *_tc3_dev = NULL;
+
+static int8_t         get_tc_index(const void *const hw);
+static void           _tc_init_irq_param(const void *const hw, void *dev);
+static inline uint8_t _get_hardware_offset(const void *const hw);
+/**
+ * \brief Initialize TC for PWM mode
+ */
+int32_t _tc_pwm_init(struct _pwm_device *const device, void *const hw)
+{
+	int8_t i   = get_tc_index(hw);
+	device->hw = hw;
+
+	if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
+		if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
+			hri_tc_clear_CTRLA_ENABLE_bit(hw);
+			hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE);
+		}
+		hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST);
+	}
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+
+	hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
+	hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
+	hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
+	hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MPWM_Val);
+
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+		hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
+		hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+	} else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
+		hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
+		hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
+	} else {
+		/* 8-bit resolution is not accepted by duty cycle control */
+		return -1;
+	}
+
+	_tc_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ(_tcs[i].irq);
+	NVIC_ClearPendingIRQ(_tcs[i].irq);
+	NVIC_EnableIRQ(_tcs[i].irq);
+
+	return 0;
+}
+/**
+ * \brief De-initialize TC for PWM mode
+ */
+void _tc_pwm_deinit(struct _pwm_device *const device)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+	ASSERT(ARRAY_SIZE(_tcs));
+
+	NVIC_DisableIRQ(_tcs[i].irq);
+
+	hri_tc_clear_CTRLA_ENABLE_bit(hw);
+	hri_tc_set_CTRLA_SWRST_bit(hw);
+}
+/**
+ * \brief Start PWM
+ */
+void _tc_start_pwm(struct _pwm_device *const device)
+{
+	hri_tc_set_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Stop PWM
+ */
+void _tc_stop_pwm(struct _pwm_device *const device)
+{
+	hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Set PWM parameter
+ */
+void _tc_set_pwm_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+
+	_tcs[i].cc0 = period;
+	_tcs[i].cc1 = duty_cycle;
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+		hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
+		hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+	} else {
+		hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0);
+		hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1);
+	}
+}
+/**
+ * \brief Get pwm waveform period value
+ */
+pwm_period_t _tc_pwm_get_period(const struct _pwm_device *const device)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+		return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0));
+	} else {
+		return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0));
+	}
+}
+/**
+ * \brief Get pwm waveform duty cycle
+ */
+uint32_t _tc_pwm_get_duty(const struct _pwm_device *const device)
+{
+	void *const hw = device->hw;
+	int8_t      i  = get_tc_index(hw);
+	uint32_t    per;
+	uint32_t    duty_cycle;
+
+	if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+		per        = hri_tccount32_read_CC_reg(hw, 0);
+		duty_cycle = hri_tccount32_read_CC_reg(hw, 1);
+	} else {
+		per        = hri_tccount16_read_CC_reg(hw, 0);
+		duty_cycle = hri_tccount16_read_CC_reg(hw, 1);
+	}
+
+	return ((duty_cycle * 1000) / per);
+}
+/**
+ * \brief Check if PWM is running
+ */
+bool _tc_is_pwm_enabled(const struct _pwm_device *const device)
+{
+	return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Enable/disable PWM interrupt
+ */
+void _tc_pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
+{
+	ASSERT(device);
+
+	if (PWM_DEVICE_PERIOD_CB == type) {
+		hri_tc_write_INTEN_OVF_bit(device->hw, disable);
+	} else if (PWM_DEVICE_ERROR_CB == type) {
+		hri_tc_write_INTEN_ERR_bit(device->hw, disable);
+	}
+}
+
+/**
+ * \brief Retrieve timer helper functions
+ */
+struct _timer_hpl_interface *_tc_get_timer(void)
+{
+	return NULL;
+}
+
+/**
+ * \brief Retrieve pwm helper functions
+ */
+struct _pwm_hpl_interface *_tc_get_pwm(void)
+{
+	return &_tc_pwm_functions;
+}
+/**
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+	void *const hw = device->hw;
+
+	if (hri_tc_get_interrupt_OVF_bit(hw)) {
+		hri_tc_clear_interrupt_OVF_bit(hw);
+		if (NULL != device->callback.pwm_period_cb) {
+			device->callback.pwm_period_cb(device);
+		}
+	}
+	if (hri_tc_get_INTEN_ERR_bit(hw)) {
+		hri_tc_clear_interrupt_ERR_bit(hw);
+		if (NULL != device->callback.pwm_error_cb) {
+			device->callback.pwm_error_cb(device);
+		}
+	}
+}
+
+/**
+ * \brief TC interrupt handler
+ */
+void TC3_Handler(void)
+{
+	tc_pwm_interrupt_handler(_tc3_dev);
+}
+
+/**
+ * \internal Retrieve TC index
+ *
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return The index of TC configuration
+ */
+static int8_t get_tc_index(const void *const hw)
+{
+	uint8_t index = _get_hardware_offset(hw);
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+		if (_tcs[i].number == index) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return -1;
+}
+
+/**
+ * \brief Init irq param with the given tc hardware instance
+ */
+static void _tc_init_irq_param(const void *const hw, void *dev)
+{
+	if (hw == TC3) {
+		_tc3_dev = (struct _pwm_device *)dev;
+	}
+}
+
+/**
+ * \internal Retrieve TC hardware index
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline uint8_t _get_hardware_offset(const void *const hw)
+{
+	return (((uint32_t)hw - (uint32_t)TC0) >> 10);
+}
diff --git a/Smol Watch Project/My Project/hpl/tc/hpl_tc_base.h b/Smol Watch Project/My Project/hpl/tc/hpl_tc_base.h
new file mode 100644
index 0000000..d602ae6
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/tc/hpl_tc_base.h	
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer/Counter
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_TC_BASE_H_INCLUDED
+#define _HPL_TC_BASE_H_INCLUDED
+
+#include <hpl_timer.h>
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup tc_group TC Hardware Proxy Layer
+ *
+ * \section tc_hpl_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_tc_get_timer(void);
+/**
+ * \brief Initialize TC for PWM
+ *
+ * This function does low level TC configuration.
+ *
+ * \param[in] device The pointer to TC device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _tc_pwm_init(struct _pwm_device *const device, void *const hw);
+
+/**
+ * \brief De-initialize TC for PWM
+ *
+ * \param[in] device The pointer to TC device instance
+ */
+void _tc_pwm_deinit(struct _pwm_device *const device);
+
+/**
+ * \brief Retrieve offset of the given tc hardware instance
+ *
+ * \param[in] device The pointer to TC device instance
+ *
+ * \return The offset of the given tc hardware instance
+ */
+uint8_t _tc_pwm_get_hardware_offset(const struct _pwm_device *const device);
+
+/**
+ * \brief Start PWM
+ *
+ * \param[in] device The pointer to TC device instance
+ */
+void _tc_start_pwm(struct _pwm_device *const device);
+
+/**
+ * \brief Stop PWM
+ *
+ * \param[in] device The pointer to TC device instance
+ */
+void _tc_stop_pwm(struct _pwm_device *const device);
+
+/**
+ * \brief Check if PWM is running
+ *
+ * \param[in] device The pointer to TC device instance
+ *
+ * \return Check status.
+ * \retval true The given timer is running
+ * \retval false The given timer is not running
+ */
+bool _tc_is_pwm_enabled(const struct _pwm_device *const device);
+
+/**
+ * \brief Set PWM parameter
+ * \param[in] device The pointer to TC device instance
+ * \param[in] period Total period of one PWM cycle.
+ * \param[in] duty_cycle Period of PWM first half during one cycle.
+ */
+void _tc_set_pwm_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
+
+/**
+ * \brief Get pwm waveform period value
+ * \param[in] device The pointer to TC device instance
+ * \return Period value.
+ */
+pwm_period_t _tc_pwm_get_period(const struct _pwm_device *const device);
+
+/**
+ * \brief Get pwm waveform duty cycle value
+ * \param[in] device The pointer to TC device instance
+ * \return Duty cycle value
+ */
+uint32_t _tc_pwm_get_duty(const struct _pwm_device *const device);
+
+/**
+ * \brief Enable/disable PWM interrupt
+ *
+ * param[in] device The pointer to PWM device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] disable Enable or disable
+ */
+void _tc_pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
+
+/**
+ * \brief Retrieve pwm helper functions
+ *
+ * \return A pointer to set of pwm helper functions
+ */
+struct _pwm_hpl_interface *_tc_get_pwm(void);
+
+//@}
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_TC_BASE_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.c b/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.c
new file mode 100644
index 0000000..52fc6f3
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.c	
@@ -0,0 +1,364 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hpl_pwm.h>
+#include <hpl_tcc.h>
+#include <hpl_tcc_config.h>
+#include <hpl_timer.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+/**
+ * \brief TCC configuration type
+ */
+struct tcc_cfg {
+	void *                 hw; /*!< instance of TCC */
+	IRQn_Type              irq;
+	hri_tcc_ctrla_reg_t    ctrl_a;
+	hri_tcc_ctrlbset_reg_t ctrl_b;
+	hri_tcc_dbgctrl_reg_t  dbg_ctrl;
+	hri_tcc_evctrl_reg_t   event_ctrl;
+	hri_tcc_cc_reg_t       cc0;
+	hri_tcc_cc_reg_t       cc1;
+	hri_tcc_cc_reg_t       cc2;
+	hri_tcc_cc_reg_t       cc3;
+	hri_tcc_per_reg_t      per;
+};
+/**
+ * \brief pwm configuration type
+ */
+struct tcc_pwm_cfg {
+	void *    hw; /*!< instance of TCC */
+	IRQn_Type irq;
+	uint8_t   sel_ch;
+	uint32_t  period;
+	uint32_t  duty_cycle;
+	uint32_t  wave;
+};
+
+/**
+ * \internal Retrieve configuration
+ *
+ * \param[in] hw The pointer of TCC base address
+ *
+ * \return The configuration
+ */
+static struct tcc_cfg *_get_tcc_cfg(void *hw);
+
+/**
+ * \brief Array of TCC configurations
+ */
+static struct tcc_cfg _cfgs[1] = {
+    {(void *)TCC0,
+     TCC0_IRQn,
+     CONF_TCC0_CTRLA,
+     CONF_TCC0_CTRLB,
+     CONF_TCC0_DBGCTRL,
+     CONF_TCC0_EVCTRL,
+     CONF_TCC0_CC0,
+     CONF_TCC0_CC1,
+     CONF_TCC0_CC2,
+     CONF_TCC0_CC3,
+     CONF_TCC0_PER},
+};
+
+/**
+ * \internal Retrieve configuration
+ *
+ * \param[in] hw The pointer of TCC base address
+ *
+ * \return The configuration
+ */
+static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw);
+
+/**
+ * \brief Array of PWM configurations
+ */
+static struct tcc_pwm_cfg _cfgs_pwm[1] = {
+    {(void *)TCC0,
+     TCC0_IRQn,
+     CONF_TCC0_SEL_CH,
+     CONF_TCC0_PER_REG,
+     CONF_TCC0_CCX_REG,
+     (CONF_TCC0_WAVEGEN << TCC_WAVE_WAVEGEN_Pos)},
+};
+/* Renamed access REG name PERB -> PERBUF */
+#define hri_tcc_write_PERB_reg hri_tcc_write_PERBUF_reg
+#define hri_tcc_read_PERB_reg hri_tcc_read_PERBUF_reg
+
+/** Renamed access REG name CCB -> CCBUF */
+#define hri_tcc_write_CCB_reg hri_tcc_write_CCBUF_reg
+#define hri_tcc_read_CCB_reg hri_tcc_read_CCBUF_reg
+
+static struct _pwm_device *_tcc0_dev = NULL;
+
+/**
+ * \brief Set of pointer to hal_pwm helper functions
+ */
+static struct _pwm_hpl_interface _tcc_pwm_functions = {
+    _tcc_pwm_init,
+    _tcc_pwm_deinit,
+    _tcc_start_pwm,
+    _tcc_stop_pwm,
+    _tcc_set_pwm_param,
+    _tcc_is_pwm_enabled,
+    _tcc_pwm_get_period,
+    _tcc_pwm_get_duty,
+    _tcc_pwm_set_irq_state,
+};
+
+/**
+ * \brief Init irq param with the given tcc hardware instance
+ */
+static void _tcc_init_irq_param(const void *const hw, void *dev)
+{
+	if (hw == TCC0) {
+		_tcc0_dev = (struct _pwm_device *)dev;
+	}
+}
+/**
+ * \brief Initialize TCC for PWM mode
+ */
+int32_t _tcc_pwm_init(struct _pwm_device *const device, void *const hw)
+{
+	struct tcc_cfg *cfg = _get_tcc_cfg(hw);
+	if (cfg == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm == NULL) {
+		return ERR_NOT_FOUND;
+	}
+
+	device->hw = hw;
+
+	if (!hri_tcc_is_syncing(hw, TCC_SYNCBUSY_SWRST)) {
+		if (hri_tcc_get_CTRLA_reg(hw, TCC_CTRLA_ENABLE)) {
+			hri_tcc_clear_CTRLA_ENABLE_bit(hw);
+			hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_ENABLE);
+		}
+		hri_tcc_write_CTRLA_reg(hw, TCC_CTRLA_SWRST);
+	}
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+
+	hri_tcc_write_CTRLA_reg(hw, cfg->ctrl_a);
+	hri_tcc_set_CTRLB_reg(hw, cfg->ctrl_b);
+	hri_tcc_write_DBGCTRL_reg(hw, cfg->dbg_ctrl);
+	hri_tcc_write_EVCTRL_reg(hw, cfg->event_ctrl);
+
+	hri_tcc_write_WAVE_reg(hw, cfg_pwm->wave);
+	hri_tcc_write_PER_reg(hw, cfg_pwm->period);
+	cfg->per = cfg_pwm->period;
+	switch (cfg_pwm->sel_ch) {
+	case 0:
+		cfg->cc0 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 0, cfg->cc0);
+		break;
+	case 1:
+		cfg->cc1 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 1, cfg->cc1);
+		break;
+	case 2:
+		cfg->cc2 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 2, cfg->cc2);
+		break;
+	case 3:
+		cfg->cc3 = cfg_pwm->duty_cycle;
+		hri_tcc_write_CC_reg(hw, 3, cfg->cc3);
+		break;
+	default:
+		return ERR_NO_RESOURCE;
+		break;
+	}
+	hri_tcc_clear_CTRLB_LUPD_bit(hw);
+
+	_tcc_init_irq_param(hw, (void *)device);
+	NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
+	NVIC_ClearPendingIRQ((IRQn_Type)cfg_pwm->irq);
+	NVIC_EnableIRQ((IRQn_Type)cfg_pwm->irq);
+
+	return ERR_NONE;
+}
+/**
+ * \brief De-initialize TCC for PWM mode
+ */
+void _tcc_pwm_deinit(struct _pwm_device *const device)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm != NULL) {
+		NVIC_DisableIRQ((IRQn_Type)cfg_pwm->irq);
+		hri_tcc_clear_CTRLA_ENABLE_bit(hw);
+		hri_tcc_set_CTRLA_SWRST_bit(hw);
+	}
+}
+/**
+ * \brief Start PWM
+ */
+void _tcc_start_pwm(struct _pwm_device *const device)
+{
+	hri_tcc_set_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Stop PWM
+ */
+void _tcc_stop_pwm(struct _pwm_device *const device)
+{
+	hri_tcc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Set PWM parameter
+ */
+void _tcc_set_pwm_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm != NULL) {
+		hri_tcc_write_PERB_reg(hw, period);
+		hri_tcc_write_CCB_reg(hw, cfg_pwm->sel_ch, duty_cycle);
+		;
+	}
+}
+/**
+ * \brief Get pwm waveform period value
+ */
+pwm_period_t _tcc_pwm_get_period(const struct _pwm_device *const device)
+{
+	return (pwm_period_t)(hri_tcc_read_PERB_reg(device->hw));
+}
+/**
+ * \brief Get pwm waveform duty cycle
+ */
+uint32_t _tcc_pwm_get_duty(const struct _pwm_device *const device)
+{
+	void *const         hw      = device->hw;
+	struct tcc_pwm_cfg *cfg_pwm = _get_tcc_pwm_cfg(hw);
+	if (cfg_pwm == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	uint32_t per        = hri_tcc_read_PERB_reg(hw);
+	uint32_t duty_cycle = hri_tcc_read_CCB_reg(hw, cfg_pwm->sel_ch);
+
+	return ((duty_cycle * 1000) / per);
+}
+/**
+ * \brief Check if PWM is running
+ */
+bool _tcc_is_pwm_enabled(const struct _pwm_device *const device)
+{
+	return hri_tcc_get_CTRLA_ENABLE_bit(device->hw);
+}
+/**
+ * \brief Enable/disable PWM interrupt
+ */
+void _tcc_pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable)
+{
+	ASSERT(device);
+
+	if (PWM_DEVICE_PERIOD_CB == type) {
+		hri_tcc_write_INTEN_OVF_bit(device->hw, disable);
+	} else if (PWM_DEVICE_ERROR_CB == type) {
+		hri_tcc_write_INTEN_ERR_bit(device->hw, disable);
+	}
+}
+
+/**
+ * \brief Retrieve timer helper functions
+ */
+struct _timer_hpl_interface *_tcc_get_timer(void)
+{
+	return NULL;
+}
+
+/**
+ * \brief Retrieve pwm helper functions
+ */
+struct _pwm_hpl_interface *_tcc_get_pwm(void)
+{
+	return &_tcc_pwm_functions;
+}
+/**
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+	void *const hw = device->hw;
+
+	if (hri_tcc_get_interrupt_OVF_bit(hw)) {
+		hri_tcc_clear_interrupt_OVF_bit(hw);
+		if (NULL != device->callback.pwm_period_cb) {
+			device->callback.pwm_period_cb(device);
+		}
+	}
+	if (hri_tcc_get_INTEN_ERR_bit(hw)) {
+		hri_tcc_clear_interrupt_ERR_bit(hw);
+		if (NULL != device->callback.pwm_error_cb) {
+			device->callback.pwm_error_cb(device);
+		}
+	}
+}
+
+/**
+ * \brief TCC interrupt handler
+ */
+void TCC0_Handler(void)
+{
+	tcc_pwm_interrupt_handler(_tcc0_dev);
+}
+
+static struct tcc_cfg *_get_tcc_cfg(void *hw)
+{
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_cfgs); i++) {
+		if (_cfgs[i].hw == hw) {
+			return &(_cfgs[i]);
+		}
+	}
+	return NULL;
+}
+
+static struct tcc_pwm_cfg *_get_tcc_pwm_cfg(void *hw)
+{
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(_cfgs_pwm); i++) {
+		if (_cfgs_pwm[i].hw == hw) {
+			return &(_cfgs_pwm[i]);
+		}
+	}
+	return NULL;
+}
diff --git a/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.h b/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.h
new file mode 100644
index 0000000..6ccf04f
--- /dev/null
+++ b/Smol Watch Project/My Project/hpl/tcc/hpl_tcc.h	
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer/Counter for Control Applications
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HPL_TCC_V101_BASE_H_INCLUDED
+#define _HPL_TCC_V101_BASE_H_INCLUDED
+
+#include <hpl_timer.h>
+#include <hpl_pwm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup tcc_group TCC Low Level Driver Helpers
+ *
+ * \section tcc_helpers_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+
+/**
+ * \brief Retrieve timer helper functions
+ *
+ * \return A pointer to set of timer helper functions
+ */
+struct _timer_hpl_interface *_tcc_get_timer(void);
+/**
+ * \brief Initialize TCC for PWM
+ *
+ * This function does low level TCC configuration.
+ *
+ * \param[in] device The pointer to PWM device instance
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ */
+int32_t _tcc_pwm_init(struct _pwm_device *const device, void *const hw);
+
+/**
+ * \brief De-initialize TCC for PWM
+ *
+ * \param[in] device The pointer to TCC device instance
+ */
+void _tcc_pwm_deinit(struct _pwm_device *const device);
+
+/**
+ * \brief Retrieve offset of the given tcc hardware instance
+ *
+ * \param[in] device The pointer to TCC device instance
+ *
+ * \return The offset of the given tcc hardware instance
+ */
+uint8_t _tcc_pwm_get_hardware_offset(const struct _pwm_device *const device);
+
+/**
+ * \brief Start PWM
+ *
+ * \param[in] device The pointer to TCC device instance
+ */
+void _tcc_start_pwm(struct _pwm_device *const device);
+
+/**
+ * \brief Stop PWM
+ *
+ * \param[in] device The pointer to TCC device instance
+ */
+void _tcc_stop_pwm(struct _pwm_device *const device);
+
+/**
+ * \brief Check if PWM is running
+ *
+ * \param[in] device The pointer to TCC device instance
+ *
+ * \return Check status.
+ * \retval true The given pwm is running
+ * \retval false The given pwm is not running
+ */
+bool _tcc_is_pwm_enabled(const struct _pwm_device *const device);
+
+/**
+ * \brief Set PWM parameter
+ * \param[in] device The pointer to TCC device instance
+ * \param[in] period Total period of one PWM cycle.
+ * \param[in] duty_cycle Period of PWM first half during one cycle.
+ */
+void _tcc_set_pwm_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
+
+/**
+ * \brief Get pwm waveform period value
+ * \param[in] device The pointer to TCC device instance
+ * \return Period value.
+ */
+pwm_period_t _tcc_pwm_get_period(const struct _pwm_device *const device);
+
+/**
+ * \brief Get pwm waveform duty cycle value
+ * \param[in] device The pointer to TCC device instance
+ * \return Duty cycle value
+ */
+uint32_t _tcc_pwm_get_duty(const struct _pwm_device *const device);
+
+/**
+ * \brief Enable/disable PWM interrupt
+ *
+ * param[in] device The pointer to PWM device instance
+ * param[in] type The type of interrupt to disable/enable if applicable
+ * param[in] disable Enable or disable
+ */
+void _tcc_pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
+
+/**
+ * \brief Retrieve pwm helper functions
+ *
+ * \return A pointer to set of pwm helper functions
+ */
+struct _pwm_hpl_interface *_tcc_get_pwm(void);
+
+//@}
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HPL_TCC_V101_BASE_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/hri/hri_ac_l22.h b/Smol Watch Project/My Project/hri/hri_ac_l22.h
new file mode 100644
index 0000000..f1e17ce
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_ac_l22.h	
@@ -0,0 +1,1746 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_AC_COMPONENT_
+#ifndef _HRI_AC_L22_H_INCLUDED_
+#define _HRI_AC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint32_t hri_ac_syncbusy_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_dbgctrl_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	while (((Ac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI0;
+	tmp |= value << AC_EVCTRL_INVEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI1;
+	tmp |= value << AC_EVCTRL_INVEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= ~AC_DBGCTRL_DBGRUN;
+	tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
+	((Ac *)hw)->DBGCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_RUNSTDBY;
+	tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYSTEN;
+	tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST_Msk;
+	tmp |= AC_COMPCTRL_HYST(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_L22_H_INCLUDED */
+#endif /* _SAML22_AC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_adc_l22.h b/Smol Watch Project/My Project/hri/hri_adc_l22.h
new file mode 100644
index 0000000..53ba6af
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_adc_l22.h	
@@ -0,0 +1,2803 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_ADC_COMPONENT_
+#ifndef _HRI_ADC_L22_H_INCLUDED_
+#define _HRI_ADC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrlc_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_inputctrl_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_syncbusy_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_seqctrl_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_ctrla_reg_t;
+typedef uint8_t  hri_adc_ctrlb_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_seqstatus_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const       hw,
+                                                                        hri_adc_seqstatus_reg_t mask)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SEQSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SEQSTATUS.reg;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ONDEMAND;
+	tmp |= value << ADC_CTRLA_ONDEMAND_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_PRESCALER_Msk;
+	tmp |= ADC_CTRLB_PRESCALER(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHEI;
+	tmp |= value << ADC_EVCTRL_FLUSHEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHINV;
+	tmp |= value << ADC_EVCTRL_FLUSHINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTINV;
+	tmp |= value << ADC_EVCTRL_STARTINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_DIFFMODE;
+	tmp |= value << ADC_CTRLC_DIFFMODE_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_LEFTADJ;
+	tmp |= value << ADC_CTRLC_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_FREERUN;
+	tmp |= value << ADC_CTRLC_FREERUN_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_CORREN;
+	tmp |= value << ADC_CTRLC_CORREN_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_R2R;
+	tmp |= value << ADC_CTRLC_R2R_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_RESSEL_Msk;
+	tmp |= ADC_CTRLC_RESSEL(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_WINMODE_Msk;
+	tmp |= ADC_CTRLC_WINMODE(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_DUALSEL_Msk;
+	tmp |= ADC_CTRLC_DUALSEL(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->CTRLC.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_OFFCOMP;
+	tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos;
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp &= ~ADC_SEQCTRL_SEQEN_Msk;
+	tmp |= ADC_SEQCTRL_SEQEN(data);
+	((Adc *)hw)->SEQCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SEQCTRL.reg;
+}
+
+static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASCOMP_Msk;
+	tmp |= ADC_CALIB_BIASCOMP(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASREFBUF_Msk;
+	tmp |= ADC_CALIB_BIASREFBUF(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_L22_H_INCLUDED */
+#endif /* _SAML22_ADC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_aes_l22.h b/Smol Watch Project/My Project/hri/hri_aes_l22.h
new file mode 100644
index 0000000..f88f081
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_aes_l22.h	
@@ -0,0 +1,1213 @@
+/**
+ * \file
+ *
+ * \brief SAM AES
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_AES_COMPONENT_
+#ifndef _HRI_AES_L22_H_INCLUDED_
+#define _HRI_AES_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AES_CRITICAL_SECTIONS)
+#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AES_CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_aes_ciplen_reg_t;
+typedef uint32_t hri_aes_ctrla_reg_t;
+typedef uint32_t hri_aes_ghash_reg_t;
+typedef uint32_t hri_aes_hashkey_reg_t;
+typedef uint32_t hri_aes_indata_reg_t;
+typedef uint32_t hri_aes_intvectv_reg_t;
+typedef uint32_t hri_aes_keyword_reg_t;
+typedef uint32_t hri_aes_randseed_reg_t;
+typedef uint8_t  hri_aes_ctrlb_reg_t;
+typedef uint8_t  hri_aes_databufptr_reg_t;
+typedef uint8_t  hri_aes_dbgctrl_reg_t;
+typedef uint8_t  hri_aes_intenset_reg_t;
+typedef uint8_t  hri_aes_intflag_reg_t;
+
+static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	((Aes *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTENSET.reg;
+}
+
+static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data)
+{
+	((Aes *)hw)->INTENSET.reg = data;
+	((Aes *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_ENABLE;
+	tmp |= value << AES_CTRLA_ENABLE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CIPHER;
+	tmp |= value << AES_CTRLA_CIPHER_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_STARTMODE;
+	tmp |= value << AES_CTRLA_STARTMODE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_LOD;
+	tmp |= value << AES_CTRLA_LOD_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYGEN;
+	tmp |= value << AES_CTRLA_KEYGEN_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_XORKEY;
+	tmp |= value << AES_CTRLA_XORKEY_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_AESMODE_Msk;
+	tmp |= AES_CTRLA_AESMODE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CFBS_Msk;
+	tmp |= AES_CTRLA_CFBS(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYSIZE_Msk;
+	tmp |= AES_CTRLA_KEYSIZE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CTYPE_Msk;
+	tmp |= AES_CTRLA_CTYPE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLA.reg;
+}
+
+static inline void hri_aes_set_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_START;
+	tmp |= value << AES_CTRLB_START_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_NEWMSG;
+	tmp |= value << AES_CTRLB_NEWMSG_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_EOM;
+	tmp |= value << AES_CTRLB_EOM_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_GFMUL;
+	tmp |= value << AES_CTRLB_GFMUL_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLB.reg;
+}
+
+static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const        hw,
+                                                                           hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk;
+	tmp |= AES_DATABUFPTR_INDATAPTR(data);
+	((Aes *)hw)->DATABUFPTR.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DATABUFPTR.reg;
+}
+
+static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->INDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INDATA.reg;
+}
+
+static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index,
+                                                            hri_aes_hashkey_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->HASHKEY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->HASHKEY[index].reg;
+}
+
+static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->GHASH[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->GHASH[index].reg;
+}
+
+static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CIPLEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CIPLEN.reg;
+}
+
+static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->RANDSEED.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw)
+{
+	return ((Aes *)hw)->RANDSEED.reg;
+}
+
+static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->KEYWORD[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INTVECTV[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AES_L22_H_INCLUDED */
+#endif /* _SAML22_AES_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_ccl_l22.h b/Smol Watch Project/My Project/hri/hri_ccl_l22.h
new file mode 100644
index 0000000..b510c86
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_ccl_l22.h	
@@ -0,0 +1,776 @@
+/**
+ * \file
+ *
+ * \brief SAM CCL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_CCL_COMPONENT_
+#ifndef _HRI_CCL_L22_H_INCLUDED_
+#define _HRI_CCL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
+#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CCL_CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ccl_lutctrl_reg_t;
+typedef uint8_t  hri_ccl_ctrl_reg_t;
+typedef uint8_t  hri_ccl_seqctrl_reg_t;
+
+static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_ENABLE;
+	tmp |= value << CCL_CTRL_ENABLE_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_RUNSTDBY;
+	tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
+{
+	return ((Ccl *)hw)->CTRL.reg;
+}
+
+static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
+	tmp |= CCL_SEQCTRL_SEQSEL(data);
+	((Ccl *)hw)->SEQCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->SEQCTRL[index].reg;
+}
+
+static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_ENABLE;
+	tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_EDGESEL;
+	tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INVEI;
+	tmp |= value << CCL_LUTCTRL_INVEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEI;
+	tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEO;
+	tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
+                                                                   hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
+	tmp |= CCL_LUTCTRL_FILTSEL(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
+	tmp |= CCL_LUTCTRL_INSEL0(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
+	tmp |= CCL_LUTCTRL_INSEL1(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
+	tmp |= CCL_LUTCTRL_INSEL2(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
+                                                                 hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
+	tmp |= CCL_LUTCTRL_TRUTH(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->LUTCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CCL_L22_H_INCLUDED */
+#endif /* _SAML22_CCL_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_dmac_l22.h b/Smol Watch Project/My Project/hri/hri_dmac_l22.h
new file mode 100644
index 0000000..a20e28e
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_dmac_l22.h	
@@ -0,0 +1,4559 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_L22_H_INCLUDED_
+#define _HRI_DMAC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrlb_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrla_reg_t;
+typedef uint8_t  hri_dmac_chid_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmac_qosctrl_reg_t;
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->CHINTENSET.reg = data;
+	((Dmac *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_CRCENABLE;
+	tmp |= value << DMAC_CTRL_CRCENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk;
+	tmp |= DMAC_QOSCTRL_WRBQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_FQOS_Msk;
+	tmp |= DMAC_QOSCTRL_FQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_DQOS_Msk;
+	tmp |= DMAC_QOSCTRL_DQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->QOSCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= ~DMAC_CHID_ID_Msk;
+	tmp |= DMAC_CHID_ID(data);
+	((Dmac *)hw)->CHID.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHID.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((Dmac *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVIE;
+	tmp |= value << DMAC_CHCTRLB_EVIE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVOE;
+	tmp |= value << DMAC_CHCTRLB_EVOE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVACT_Msk;
+	tmp |= DMAC_CHCTRLB_EVACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_LVL_Msk;
+	tmp |= DMAC_CHCTRLB_LVL(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGSRC(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLB.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_L22_H_INCLUDED */
+#endif /* _SAML22_DMAC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_dsu_l22.h b/Smol Watch Project/My Project/hri/hri_dsu_l22.h
new file mode 100644
index 0000000..2e8bbe8
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_dsu_l22.h	
@@ -0,0 +1,1163 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_DSU_COMPONENT_
+#ifndef _HRI_DSU_L22_H_INCLUDED_
+#define _HRI_DSU_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_dcfg_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry0_reg_t;
+typedef uint32_t hri_dsu_entry1_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint32_t hri_dsu_pid5_reg_t;
+typedef uint32_t hri_dsu_pid6_reg_t;
+typedef uint32_t hri_dsu_pid7_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY0.reg;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY1.reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID5.reg;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID6.reg;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID7.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_AMOD_Msk;
+	tmp |= DSU_ADDR_AMOD(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= ~DSU_DCFG_DCFG_Msk;
+	tmp |= DSU_DCFG_DCFG(data);
+	((Dsu *)hw)->DCFG[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCFG[index].reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_L22_H_INCLUDED */
+#endif /* _SAML22_DSU_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_eic_l22.h b/Smol Watch Project/My Project/hri/hri_eic_l22.h
new file mode 100644
index 0000000..058012b
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_eic_l22.h	
@@ -0,0 +1,1463 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_EIC_COMPONENT_
+#ifndef _HRI_EIC_L22_H_INCLUDED_
+#define _HRI_EIC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_eic_nmiflag_reg_t;
+typedef uint32_t hri_eic_asynch_reg_t;
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_syncbusy_reg_t;
+typedef uint8_t  hri_eic_ctrla_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
+	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_ENABLE;
+	tmp |= value << EIC_CTRLA_ENABLE_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_CKSEL;
+	tmp |= value << EIC_CTRLA_CKSEL_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg = data;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
+{
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	return ((Eic *)hw)->CTRLA.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIASYNCH;
+	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
+	tmp |= EIC_EVCTRL_EXTINTEO(data);
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
+	tmp |= EIC_ASYNCH_ASYNCH(data);
+	((Eic *)hw)->ASYNCH.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
+{
+	return ((Eic *)hw)->ASYNCH.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_L22_H_INCLUDED */
+#endif /* _SAML22_EIC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_evsys_l22.h b/Smol Watch Project/My Project/hri/hri_evsys_l22.h
new file mode 100644
index 0000000..a2964f9
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_evsys_l22.h	
@@ -0,0 +1,1333 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_L22_H_INCLUDED_
+#define _HRI_EVSYS_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_chstatus_reg_t;
+typedef uint32_t hri_evsys_intenset_reg_t;
+typedef uint32_t hri_evsys_intflag_reg_t;
+typedef uint32_t hri_evsys_swevt_reg_t;
+typedef uint32_t hri_evsys_user_reg_t;
+typedef uint8_t  hri_evsys_ctrla_reg_t;
+
+static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	((Evsys *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTENSET.reg;
+}
+
+static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data)
+{
+	((Evsys *)hw)->INTENSET.reg = data;
+	((Evsys *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CTRLA.reg;
+}
+
+static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index,
+                                                                     hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index,
+                                                                    hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index,
+                                                                hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->CHANNEL[index].reg;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index,
+                                                                 hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index,
+                                                          hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->USER[index].reg;
+}
+
+static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->SWEVT.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_L22_H_INCLUDED */
+#endif /* _SAML22_EVSYS_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_freqm_l22.h b/Smol Watch Project/My Project/hri/hri_freqm_l22.h
new file mode 100644
index 0000000..e221bbf
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_freqm_l22.h	
@@ -0,0 +1,464 @@
+/**
+ * \file
+ *
+ * \brief SAM FREQM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_FREQM_COMPONENT_
+#ifndef _HRI_FREQM_L22_H_INCLUDED_
+#define _HRI_FREQM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
+#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define FREQM_CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_freqm_cfga_reg_t;
+typedef uint32_t hri_freqm_syncbusy_reg_t;
+typedef uint32_t hri_freqm_value_reg_t;
+typedef uint8_t  hri_freqm_ctrla_reg_t;
+typedef uint8_t  hri_freqm_ctrlb_reg_t;
+typedef uint8_t  hri_freqm_intenset_reg_t;
+typedef uint8_t  hri_freqm_intflag_reg_t;
+typedef uint8_t  hri_freqm_status_reg_t;
+
+static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	((Freqm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+}
+
+static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
+}
+
+static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+	} else {
+		((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+	}
+}
+
+static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+}
+
+static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
+{
+	((Freqm *)hw)->INTENSET.reg = data;
+	((Freqm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->VALUE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->VALUE.reg;
+}
+
+static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= ~FREQM_CTRLA_ENABLE;
+	tmp |= value << FREQM_CTRLA_ENABLE_Pos;
+	((Freqm *)hw)->CTRLA.reg = tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg = data;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
+{
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	return ((Freqm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	uint16_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= ~FREQM_CFGA_REFNUM_Msk;
+	tmp |= FREQM_CFGA_REFNUM(data);
+	((Freqm *)hw)->CFGA.reg = tmp;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->CFGA.reg;
+}
+
+static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->STATUS.reg;
+}
+
+static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLB.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_FREQM_L22_H_INCLUDED */
+#endif /* _SAML22_FREQM_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_gclk_l22.h b/Smol Watch Project/My Project/hri/hri_gclk_l22.h
new file mode 100644
index 0000000..2ae6d49
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_gclk_l22.h	
@@ -0,0 +1,770 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_L22_H_INCLUDED_
+#define _HRI_GCLK_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_pchctrl_reg_t;
+typedef uint32_t hri_gclk_syncbusy_reg_t;
+typedef uint8_t  hri_gclk_ctrla_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	return ((Gclk *)hw)->CTRLA.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIV_Msk;
+	tmp |= GCLK_GENCTRL_DIV(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	return ((Gclk *)hw)->GENCTRL[index].reg;
+}
+
+static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_CHEN;
+	tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_WRTLOCK;
+	tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_GEN_Msk;
+	tmp |= GCLK_PCHCTRL_GEN(data);
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Gclk *)hw)->PCHCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_L22_H_INCLUDED */
+#endif /* _SAML22_GCLK_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_l22.h b/Smol Watch Project/My Project/hri/hri_l22.h
new file mode 100644
index 0000000..d99268c
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_l22.h	
@@ -0,0 +1,70 @@
+/**
+ * \file
+ *
+ * \brief SAM L22 HRI top-level header file
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HRI_L22_H_INCLUDED_
+#define _HRI_L22_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_l22.h>
+#include <hri_adc_l22.h>
+#include <hri_aes_l22.h>
+#include <hri_ccl_l22.h>
+#include <hri_dmac_l22.h>
+#include <hri_dsu_l22.h>
+#include <hri_eic_l22.h>
+#include <hri_evsys_l22.h>
+#include <hri_freqm_l22.h>
+#include <hri_gclk_l22.h>
+#include <hri_mclk_l22.h>
+#include <hri_mtb_l22.h>
+#include <hri_nvic_l22.h>
+#include <hri_nvmctrl_l22.h>
+#include <hri_osc32kctrl_l22.h>
+#include <hri_oscctrl_l22.h>
+#include <hri_pac_l22.h>
+#include <hri_pm_l22.h>
+#include <hri_port_l22.h>
+#include <hri_rstc_l22.h>
+#include <hri_rtc_l22.h>
+#include <hri_sercom_l22.h>
+#include <hri_slcd_l22.h>
+#include <hri_supc_l22.h>
+#include <hri_systemcontrol_l22.h>
+#include <hri_systick_l22.h>
+#include <hri_tc_l22.h>
+#include <hri_tcc_l22.h>
+#include <hri_trng_l22.h>
+#include <hri_usb_l22.h>
+#include <hri_wdt_l22.h>
+
+#endif /* _HRI_L22_H_INCLUDED_ */
diff --git a/Smol Watch Project/My Project/hri/hri_mclk_l22.h b/Smol Watch Project/My Project/hri/hri_mclk_l22.h
new file mode 100644
index 0000000..b03c006
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_mclk_l22.h	
@@ -0,0 +1,2300 @@
+/**
+ * \file
+ *
+ * \brief SAM MCLK
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_MCLK_COMPONENT_
+#ifndef _HRI_MCLK_L22_H_INCLUDED_
+#define _HRI_MCLK_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
+#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MCLK_CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mclk_ahbmask_reg_t;
+typedef uint32_t hri_mclk_apbamask_reg_t;
+typedef uint32_t hri_mclk_apbbmask_reg_t;
+typedef uint32_t hri_mclk_apbcmask_reg_t;
+typedef uint8_t  hri_mclk_bupdiv_reg_t;
+typedef uint8_t  hri_mclk_cpudiv_reg_t;
+typedef uint8_t  hri_mclk_intenset_reg_t;
+typedef uint8_t  hri_mclk_intflag_reg_t;
+
+static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	((Mclk *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+	} else {
+		((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTENSET.reg;
+}
+
+static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
+{
+	((Mclk *)hw)->INTENSET.reg = data;
+	((Mclk *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= ~MCLK_CPUDIV_CPUDIV_Msk;
+	tmp |= MCLK_CPUDIV_CPUDIV(data);
+	((Mclk *)hw)->CPUDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->CPUDIV.reg;
+}
+
+static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp &= ~MCLK_BUPDIV_BUPDIV_Msk;
+	tmp |= MCLK_BUPDIV_BUPDIV(data);
+	((Mclk *)hw)->BUPDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->BUPDIV.reg;
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB0;
+	tmp |= value << MCLK_AHBMASK_HPB0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB1;
+	tmp |= value << MCLK_AHBMASK_HPB1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB2;
+	tmp |= value << MCLK_AHBMASK_HPB2_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DMAC;
+	tmp |= value << MCLK_AHBMASK_DMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_USB;
+	tmp |= value << MCLK_AHBMASK_USB_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DSU;
+	tmp |= value << MCLK_AHBMASK_DSU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PAC;
+	tmp |= value << MCLK_AHBMASK_PAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HSRAM;
+	tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PAC;
+	tmp |= value << MCLK_APBAMASK_PAC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PM;
+	tmp |= value << MCLK_APBAMASK_PM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_MCLK;
+	tmp |= value << MCLK_APBAMASK_MCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RSTC;
+	tmp |= value << MCLK_APBAMASK_RSTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSCCTRL;
+	tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
+	tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SUPC;
+	tmp |= value << MCLK_APBAMASK_SUPC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_GCLK;
+	tmp |= value << MCLK_APBAMASK_GCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_WDT;
+	tmp |= value << MCLK_APBAMASK_WDT_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RTC;
+	tmp |= value << MCLK_APBAMASK_RTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_EIC;
+	tmp |= value << MCLK_APBAMASK_EIC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_FREQM;
+	tmp |= value << MCLK_APBAMASK_FREQM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_USB;
+	tmp |= value << MCLK_APBBMASK_USB_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_DSU;
+	tmp |= value << MCLK_APBBMASK_DSU_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_NVMCTRL;
+	tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_PORT;
+	tmp |= value << MCLK_APBBMASK_PORT_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_EVSYS;
+	tmp |= value << MCLK_APBCMASK_EVSYS_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM0;
+	tmp |= value << MCLK_APBCMASK_SERCOM0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM1;
+	tmp |= value << MCLK_APBCMASK_SERCOM1_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM2;
+	tmp |= value << MCLK_APBCMASK_SERCOM2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM3;
+	tmp |= value << MCLK_APBCMASK_SERCOM3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM4;
+	tmp |= value << MCLK_APBCMASK_SERCOM4_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM5;
+	tmp |= value << MCLK_APBCMASK_SERCOM5_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC0;
+	tmp |= value << MCLK_APBCMASK_TCC0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC0;
+	tmp |= value << MCLK_APBCMASK_TC0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC1;
+	tmp |= value << MCLK_APBCMASK_TC1_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC2;
+	tmp |= value << MCLK_APBCMASK_TC2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC3;
+	tmp |= value << MCLK_APBCMASK_TC3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_ADC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_ADC) >> MCLK_APBCMASK_ADC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_ADC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_ADC;
+	tmp |= value << MCLK_APBCMASK_ADC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AC;
+	tmp |= value << MCLK_APBCMASK_AC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_PTC;
+	tmp |= value << MCLK_APBCMASK_PTC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SLCD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SLCD) >> MCLK_APBCMASK_SLCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SLCD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SLCD;
+	tmp |= value << MCLK_APBCMASK_SLCD_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AES;
+	tmp |= value << MCLK_APBCMASK_AES_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TRNG;
+	tmp |= value << MCLK_APBCMASK_TRNG_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_CCL;
+	tmp |= value << MCLK_APBCMASK_CCL_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBCMASK.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MCLK_L22_H_INCLUDED */
+#endif /* _SAML22_MCLK_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_mtb_l22.h b/Smol Watch Project/My Project/hri/hri_mtb_l22.h
new file mode 100644
index 0000000..f8cb66d
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_mtb_l22.h	
@@ -0,0 +1,551 @@
+/**
+ * \file
+ *
+ * \brief SAM MTB
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_MTB_COMPONENT_
+#ifndef _HRI_MTB_L22_H_INCLUDED_
+#define _HRI_MTB_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MTB_CRITICAL_SECTIONS)
+#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MTB_CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mtb_authstatus_reg_t;
+typedef uint32_t hri_mtb_base_reg_t;
+typedef uint32_t hri_mtb_cid0_reg_t;
+typedef uint32_t hri_mtb_cid1_reg_t;
+typedef uint32_t hri_mtb_cid2_reg_t;
+typedef uint32_t hri_mtb_cid3_reg_t;
+typedef uint32_t hri_mtb_claimset_reg_t;
+typedef uint32_t hri_mtb_devarch_reg_t;
+typedef uint32_t hri_mtb_devid_reg_t;
+typedef uint32_t hri_mtb_devtype_reg_t;
+typedef uint32_t hri_mtb_flow_reg_t;
+typedef uint32_t hri_mtb_itctrl_reg_t;
+typedef uint32_t hri_mtb_lockaccess_reg_t;
+typedef uint32_t hri_mtb_lockstatus_reg_t;
+typedef uint32_t hri_mtb_master_reg_t;
+typedef uint32_t hri_mtb_pid0_reg_t;
+typedef uint32_t hri_mtb_pid1_reg_t;
+typedef uint32_t hri_mtb_pid2_reg_t;
+typedef uint32_t hri_mtb_pid3_reg_t;
+typedef uint32_t hri_mtb_pid4_reg_t;
+typedef uint32_t hri_mtb_pid5_reg_t;
+typedef uint32_t hri_mtb_pid6_reg_t;
+typedef uint32_t hri_mtb_pid7_reg_t;
+typedef uint32_t hri_mtb_position_reg_t;
+
+static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMSET.reg = mask;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CLAIMSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CLAIMSET.reg;
+}
+
+static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data)
+{
+	((Mtb *)hw)->CLAIMSET.reg = data;
+	((Mtb *)hw)->CLAIMCLR.reg = ~data;
+}
+
+static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMCLR.reg = mask;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->BASE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->BASE.reg;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKSTATUS.reg;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->AUTHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->AUTHSTATUS.reg;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVARCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVARCH.reg;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVID.reg;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVTYPE.reg;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID4.reg;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID5.reg;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID6.reg;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID7.reg;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID0.reg;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID1.reg;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID2.reg;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID3.reg;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID0.reg;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID1.reg;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID2.reg;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID3.reg;
+}
+
+static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->POSITION.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->POSITION.reg;
+}
+
+static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->MASTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->MASTER.reg;
+}
+
+static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->FLOW.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->FLOW.reg;
+}
+
+static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->ITCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->ITCTRL.reg;
+}
+
+static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKACCESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKACCESS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MTB_L22_H_INCLUDED */
+#endif /* _SAML22_MTB_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_nvic_l22.h b/Smol Watch Project/My Project/hri/hri_nvic_l22.h
new file mode 100644
index 0000000..5596c99
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_nvic_l22.h	
@@ -0,0 +1,269 @@
+/**
+ * \file
+ *
+ * \brief SAM NVIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_NVIC_COMPONENT_
+#ifndef _HRI_NVIC_L22_H_INCLUDED_
+#define _HRI_NVIC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
+#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVIC_CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_nvic_icer_reg_t;
+typedef uint32_t hri_nvic_icpr_reg_t;
+typedef uint32_t hri_nvic_ipr_reg_t;
+typedef uint32_t hri_nvic_iser_reg_t;
+typedef uint32_t hri_nvic_ispr_reg_t;
+
+static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ISER.reg;
+}
+
+static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ICER.reg;
+}
+
+static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ISPR.reg;
+}
+
+static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ICPR.reg;
+}
+
+static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->IPR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->IPR[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVIC_L22_H_INCLUDED */
+#endif /* _SAML22_NVIC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_nvmctrl_l22.h b/Smol Watch Project/My Project/hri/hri_nvmctrl_l22.h
new file mode 100644
index 0000000..07629fb
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_nvmctrl_l22.h	
@@ -0,0 +1,1104 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_L22_H_INCLUDED_
+#define _HRI_NVMCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_lock_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint8_t  hri_nvmctrl_intenset_reg_t;
+typedef uint8_t  hri_nvmctrl_intflag_reg_t;
+
+static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMD_Msk;
+	tmp |= NVMCTRL_CTRLA_CMD(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk;
+	tmp |= NVMCTRL_CTRLA_CMDEX(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_MANW;
+	tmp |= value << NVMCTRL_CTRLB_MANW_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_FWUP;
+	tmp |= value << NVMCTRL_CTRLB_FWUP_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_CACHEDIS;
+	tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_RWS_Msk;
+	tmp |= NVMCTRL_CTRLB_RWS(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk;
+	tmp |= NVMCTRL_CTRLB_SLEEPPRM(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_READMODE_Msk;
+	tmp |= NVMCTRL_CTRLB_READMODE(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLB.reg;
+}
+
+static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_NVMP_Msk;
+	tmp |= NVMCTRL_PARAM_NVMP(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_PSZ_Msk;
+	tmp |= NVMCTRL_PARAM_PSZ(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const       hw,
+                                                                      hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk;
+	tmp |= NVMCTRL_PARAM_RWWEEP(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= ~NVMCTRL_LOCK_LOCK_Msk;
+	tmp |= NVMCTRL_LOCK_LOCK(data);
+	((Nvmctrl *)hw)->LOCK.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->LOCK.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_NVMCTRL_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_osc32kctrl_l22.h b/Smol Watch Project/My Project/hri/hri_osc32kctrl_l22.h
new file mode 100644
index 0000000..44bb32b
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_osc32kctrl_l22.h	
@@ -0,0 +1,1233 @@
+/**
+ * \file
+ *
+ * \brief SAM OSC32KCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_OSC32KCTRL_COMPONENT_
+#ifndef _HRI_OSC32KCTRL_L22_H_INCLUDED_
+#define _HRI_OSC32KCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
+typedef uint32_t hri_osc32kctrl_intenset_reg_t;
+typedef uint32_t hri_osc32kctrl_intflag_reg_t;
+typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
+typedef uint32_t hri_osc32kctrl_status_reg_t;
+typedef uint8_t  hri_osc32kctrl_cfdctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_evctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_rtcctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_slcdctrl_reg_t;
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const             hw,
+                                                                         hri_osc32kctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = data;
+	((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const            hw,
+                                                                                hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
+	tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
+	((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->RTCCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg |= OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_SLCDCTRL_SLCDSEL) >> OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	tmp |= value << OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
+	((Osc32kctrl *)hw)->SLCDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg ^= OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_get_SLCDCTRL_reg(const void *const             hw,
+                                                                            hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_read_SLCDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const            hw,
+                                                                                 hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->CFDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const              hw,
+                                                                                   hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const              hw,
+                                                                              hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->OSCULP32K.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSC32KCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_OSC32KCTRL_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_oscctrl_l22.h b/Smol Watch Project/My Project/hri/hri_oscctrl_l22.h
new file mode 100644
index 0000000..d1bc4b6
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_oscctrl_l22.h	
@@ -0,0 +1,3451 @@
+/**
+ * \file
+ *
+ * \brief SAM OSCCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_OSCCTRL_COMPONENT_
+#ifndef _HRI_OSCCTRL_L22_H_INCLUDED_
+#define _HRI_OSCCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS)
+#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSCCTRL_CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_oscctrl_dfllctrl_reg_t;
+typedef uint16_t hri_oscctrl_xoscctrl_reg_t;
+typedef uint32_t hri_oscctrl_dfllmul_reg_t;
+typedef uint32_t hri_oscctrl_dfllval_reg_t;
+typedef uint32_t hri_oscctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrl_dpllratio_reg_t;
+typedef uint32_t hri_oscctrl_intenset_reg_t;
+typedef uint32_t hri_oscctrl_intflag_reg_t;
+typedef uint32_t hri_oscctrl_status_reg_t;
+typedef uint8_t  hri_oscctrl_cfdpresc_reg_t;
+typedef uint8_t  hri_oscctrl_dfllsync_reg_t;
+typedef uint8_t  hri_oscctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_dpllpresc_reg_t;
+typedef uint8_t  hri_oscctrl_dpllstatus_reg_t;
+typedef uint8_t  hri_oscctrl_dpllsyncbusy_reg_t;
+typedef uint8_t  hri_oscctrl_evctrl_reg_t;
+typedef uint8_t  hri_oscctrl_osc16mctrl_reg_t;
+
+static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_oscctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL;
+}
+
+static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_oscctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data)
+{
+	((Oscctrl *)hw)->INTENSET.reg = data;
+	((Oscctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->STATUS.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const              hw,
+                                                                              hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                          hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_AMPGC;
+	tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const          hw,
+                                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_GAIN(data);
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const          hw,
+                                                                             hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_STARTUP(data);
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const          hw,
+                                                                      hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->XOSCCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const          hw,
+                                                                              hri_oscctrl_cfdpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk;
+	tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data);
+	((Oscctrl *)hw)->CFDPRESC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const          hw,
+                                                                      hri_oscctrl_cfdpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->CFDPRESC.reg;
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE;
+	tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const            hw,
+                                                                              hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk;
+	tmp |= OSCCTRL_OSC16MCTRL_FSEL(data);
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const            hw,
+                                                                          hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->OSC16MCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_ENABLE;
+	tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_MODE;
+	tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_STABLE;
+	tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_LLAW;
+	tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_USBCRM;
+	tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_CCDIS;
+	tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_QLDIS;
+	tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC;
+	tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK;
+	tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->DFLLCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_FINE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_COARSE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= OSCCTRL_DFLLVAL_DIFF(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk;
+	tmp |= OSCCTRL_DFLLMUL_MUL(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_FSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_CSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_READREQ;
+	tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLSYNC.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                           hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((Oscctrl *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((Oscctrl *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LPEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                              hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                              hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                             hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                           hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLCTRLB.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const           hw,
+                                                                             hri_oscctrl_dpllpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk;
+	tmp |= OSCCTRL_DPLLPRESC_PRESC(data);
+	((Oscctrl *)hw)->DPLLPRESC.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllpresc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->DPLLPRESC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSCCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_OSCCTRL_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_pac_l22.h b/Smol Watch Project/My Project/hri/hri_pac_l22.h
new file mode 100644
index 0000000..488c707
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_pac_l22.h	
@@ -0,0 +1,1076 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PAC_COMPONENT_
+#ifndef _HRI_PAC_L22_H_INCLUDED_
+#define _HRI_PAC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_intflaga_reg_t;
+typedef uint32_t hri_pac_intflagahb_reg_t;
+typedef uint32_t hri_pac_intflagb_reg_t;
+typedef uint32_t hri_pac_intflagc_reg_t;
+typedef uint32_t hri_pac_statusa_reg_t;
+typedef uint32_t hri_pac_statusb_reg_t;
+typedef uint32_t hri_pac_statusc_reg_t;
+typedef uint32_t hri_pac_wrctrl_reg_t;
+typedef uint8_t  hri_pac_evctrl_reg_t;
+typedef uint8_t  hri_pac_intenset_reg_t;
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDMAC) >> PAC_INTFLAGAHB_HSRAMDMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDMAC;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGAHB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGAHB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGA.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGA.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU;
+}
+
+static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_ADC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC) >> PAC_INTFLAGC_ADC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_ADC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SLCD_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SLCD) >> PAC_INTFLAGC_SLCD_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SLCD_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SLCD;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGC.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGC.reg = mask;
+}
+
+static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+	} else {
+		((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+}
+
+static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data)
+{
+	((Pac *)hw)->INTENSET.reg = data;
+	((Pac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_ADC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC) >> PAC_STATUSC_ADC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SLCD_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SLCD) >> PAC_STATUSC_SLCD_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSC.reg;
+}
+
+static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_PERID_Msk;
+	tmp |= PAC_WRCTRL_PERID(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_KEY_Msk;
+	tmp |= PAC_WRCTRL_KEY(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WRCTRL.reg;
+}
+
+static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= ~PAC_EVCTRL_ERREO;
+	tmp |= value << PAC_EVCTRL_ERREO_Pos;
+	((Pac *)hw)->EVCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_L22_H_INCLUDED */
+#endif /* _SAML22_PAC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_pm_l22.h b/Smol Watch Project/My Project/hri/hri_pm_l22.h
new file mode 100644
index 0000000..d56d3cf
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_pm_l22.h	
@@ -0,0 +1,592 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PM_COMPONENT_
+#ifndef _HRI_PM_L22_H_INCLUDED_
+#define _HRI_PM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_pm_stdbycfg_reg_t;
+typedef uint8_t  hri_pm_ctrla_reg_t;
+typedef uint8_t  hri_pm_intenset_reg_t;
+typedef uint8_t  hri_pm_intflag_reg_t;
+typedef uint8_t  hri_pm_plcfg_reg_t;
+typedef uint8_t  hri_pm_sleepcfg_reg_t;
+
+static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
+}
+
+static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= ~PM_CTRLA_IORET;
+	tmp |= value << PM_CTRLA_IORET_Pos;
+	((Pm *)hw)->CTRLA.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
+	tmp |= PM_SLEEPCFG_SLEEPMODE(data);
+	((Pm *)hw)->SLEEPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEPCFG.reg;
+}
+
+static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= ~PM_PLCFG_PLDIS;
+	tmp |= value << PM_PLCFG_PLDIS_Pos;
+	((Pm *)hw)->PLCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= ~PM_PLCFG_PLSEL_Msk;
+	tmp |= PM_PLCFG_PLSEL(data);
+	((Pm *)hw)->PLCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->PLCFG.reg;
+}
+
+static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint16_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_VREGSMOD_Msk;
+	tmp |= PM_STDBYCFG_VREGSMOD(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint16_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_BBIASHS_Msk;
+	tmp |= PM_STDBYCFG_BBIASHS(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->STDBYCFG.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_L22_H_INCLUDED */
+#endif /* _SAML22_PM_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_port_l22.h b/Smol Watch Project/My Project/hri/hri_port_l22.h
new file mode 100644
index 0000000..ee99c2e
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_port_l22.h	
@@ -0,0 +1,2357 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PORT_COMPONENT_
+#ifndef _HRI_PORT_L22_H_INCLUDED_
+#define _HRI_PORT_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_evctrl_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_evctrl_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_L22_H_INCLUDED */
+#endif /* _SAML22_PORT_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_rstc_l22.h b/Smol Watch Project/My Project/hri/hri_rstc_l22.h
new file mode 100644
index 0000000..853744e
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_rstc_l22.h	
@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief SAM RSTC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_RSTC_COMPONENT_
+#ifndef _HRI_RSTC_L22_H_INCLUDED_
+#define _HRI_RSTC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
+#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RSTC_CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_rstc_bkupexit_reg_t;
+typedef uint8_t hri_rstc_rcause_reg_t;
+
+static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->RCAUSE.reg;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->BKUPEXIT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->BKUPEXIT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RSTC_L22_H_INCLUDED */
+#endif /* _SAML22_RSTC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_rtc_l22.h b/Smol Watch Project/My Project/hri/hri_rtc_l22.h
new file mode 100644
index 0000000..0b46f01
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_rtc_l22.h	
@@ -0,0 +1,9084 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_RTC_COMPONENT_
+#ifndef _HRI_RTC_L22_H_INCLUDED_
+#define _HRI_RTC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrla_reg_t;
+typedef uint16_t hri_rtcmode0_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode0_intenset_reg_t;
+typedef uint16_t hri_rtcmode0_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrla_reg_t;
+typedef uint16_t hri_rtcmode1_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode1_intenset_reg_t;
+typedef uint16_t hri_rtcmode1_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode2_ctrla_reg_t;
+typedef uint16_t hri_rtcmode2_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode2_intenset_reg_t;
+typedef uint16_t hri_rtcmode2_intflag_reg_t;
+typedef uint32_t hri_rtc_bkup_reg_t;
+typedef uint32_t hri_rtc_gp_reg_t;
+typedef uint32_t hri_rtc_tampctrl_reg_t;
+typedef uint32_t hri_rtc_tampid_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode0_evctrl_reg_t;
+typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode0_timestamp_reg_t;
+typedef uint32_t hri_rtcmode1_evctrl_reg_t;
+typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode1_timestamp_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint32_t hri_rtcmode2_evctrl_reg_t;
+typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode2_timestamp_reg_t;
+typedef uint8_t  hri_rtc_dbgctrl_reg_t;
+typedef uint8_t  hri_rtc_freqcorr_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode0_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode1_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode2_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode0_timestamp_reg_t mask)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode0_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode1_timestamp_reg_t mask)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode1_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const            hw,
+                                                                             hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const            hw,
+                                                                               hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode2_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE0_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE0.CTRLA.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE1_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE1.CTRLA.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLKREP;
+	tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE2_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	return ((Rtc *)hw)->MODE2.CTRLA.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE0_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE0_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRLB.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE1_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE1_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRLB.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE2_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE2_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRLB.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= ~RTC_GP_GP_Msk;
+	tmp |= RTC_GP_GP(data);
+	((Rtc *)hw)->MODE0.GP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	return ((Rtc *)hw)->MODE0.GP[index].reg;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL0;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL1;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL2;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL3;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL4;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC0;
+	tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC1;
+	tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC2;
+	tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC3;
+	tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC4;
+	tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN0ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN1ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN2ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN3ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN4ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID0;
+	tmp |= value << RTC_TAMPID_TAMPID0_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID1;
+	tmp |= value << RTC_TAMPID_TAMPID1_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID2;
+	tmp |= value << RTC_TAMPID_TAMPID2_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID3;
+	tmp |= value << RTC_TAMPID_TAMPID3_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID4;
+	tmp |= value << RTC_TAMPID_TAMPID4_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPEVT;
+	tmp |= value << RTC_TAMPID_TAMPEVT_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPID.reg;
+}
+
+static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= ~RTC_BKUP_BKUP_Msk;
+	tmp |= RTC_BKUP_BKUP(data);
+	((Rtc *)hw)->MODE0.BKUP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.BKUP[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_L22_H_INCLUDED */
+#endif /* _SAML22_RTC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_sercom_l22.h b/Smol Watch Project/My Project/hri/hri_sercom_l22.h
new file mode 100644
index 0000000..6d97ca8
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_sercom_l22.h	
@@ -0,0 +1,7827 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_L22_H_INCLUDED_
+#define _HRI_SERCOM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_data_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_ctrlc_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_data_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_data_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxerrcnt_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const              hw,
+                                                                              hri_sercomusart_rxerrcnt_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXERRCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXERRCNT.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXINV;
+	tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXINV;
+	tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_INACK;
+	tmp |= value << SERCOM_USART_CTRLC_INACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DSNACK;
+	tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk;
+	tmp |= SERCOM_USART_CTRLC_GTIME(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk;
+	tmp |= SERCOM_USART_CTRLC_MAXITER(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= ~SERCOM_I2CM_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CM_DATA_DATA(data);
+	((Sercom *)hw)->I2CM.DATA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_data_reg_t mask)
+{
+	uint8_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= ~SERCOM_I2CS_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CS_DATA_DATA(data);
+	((Sercom *)hw)->I2CS.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const        hw,
+                                                                      hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= ~SERCOM_SPI_DATA_DATA_Msk;
+	tmp |= SERCOM_SPI_DATA_DATA(data);
+	((Sercom *)hw)->SPI.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const          hw,
+                                                                          hri_sercomusart_data_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= ~SERCOM_USART_DATA_DATA_Msk;
+	tmp |= SERCOM_USART_DATA_DATA(data);
+	((Sercom *)hw)->USART.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const          hw,
+                                                                      hri_sercomusart_data_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_L22_H_INCLUDED */
+#endif /* _SAML22_SERCOM_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_slcd_l22.h b/Smol Watch Project/My Project/hri/hri_slcd_l22.h
new file mode 100644
index 0000000..89fde26
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_slcd_l22.h	
@@ -0,0 +1,5440 @@
+/**
+ * \file
+ *
+ * \brief SAM SLCD
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SLCD_COMPONENT_
+#ifndef _HRI_SLCD_L22_H_INCLUDED_
+#define _HRI_SLCD_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SLCD_CRITICAL_SECTIONS)
+#define SLCD_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SLCD_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SLCD_CRITICAL_SECTION_ENTER()
+#define SLCD_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_slcd_cmindex_reg_t;
+typedef uint16_t hri_slcd_ctrlb_reg_t;
+typedef uint16_t hri_slcd_ctrlc_reg_t;
+typedef uint32_t hri_slcd_acmcfg_reg_t;
+typedef uint32_t hri_slcd_bcfg_reg_t;
+typedef uint32_t hri_slcd_cmdata_reg_t;
+typedef uint32_t hri_slcd_cmdmask_reg_t;
+typedef uint32_t hri_slcd_csrcfg_reg_t;
+typedef uint32_t hri_slcd_ctrla_reg_t;
+typedef uint32_t hri_slcd_isdata_reg_t;
+typedef uint32_t hri_slcd_lpenh_reg_t;
+typedef uint32_t hri_slcd_lpenl_reg_t;
+typedef uint32_t hri_slcd_sdatah0_reg_t;
+typedef uint32_t hri_slcd_sdatah1_reg_t;
+typedef uint32_t hri_slcd_sdatah2_reg_t;
+typedef uint32_t hri_slcd_sdatah3_reg_t;
+typedef uint32_t hri_slcd_sdatah4_reg_t;
+typedef uint32_t hri_slcd_sdatah5_reg_t;
+typedef uint32_t hri_slcd_sdatah6_reg_t;
+typedef uint32_t hri_slcd_sdatah7_reg_t;
+typedef uint32_t hri_slcd_sdatal0_reg_t;
+typedef uint32_t hri_slcd_sdatal1_reg_t;
+typedef uint32_t hri_slcd_sdatal2_reg_t;
+typedef uint32_t hri_slcd_sdatal3_reg_t;
+typedef uint32_t hri_slcd_sdatal4_reg_t;
+typedef uint32_t hri_slcd_sdatal5_reg_t;
+typedef uint32_t hri_slcd_sdatal6_reg_t;
+typedef uint32_t hri_slcd_sdatal7_reg_t;
+typedef uint32_t hri_slcd_syncbusy_reg_t;
+typedef uint8_t  hri_slcd_abmcfg_reg_t;
+typedef uint8_t  hri_slcd_cmcfg_reg_t;
+typedef uint8_t  hri_slcd_ctrld_reg_t;
+typedef uint8_t  hri_slcd_evctrl_reg_t;
+typedef uint8_t  hri_slcd_fc0_reg_t;
+typedef uint8_t  hri_slcd_fc1_reg_t;
+typedef uint8_t  hri_slcd_fc2_reg_t;
+typedef uint8_t  hri_slcd_intenset_reg_t;
+typedef uint8_t  hri_slcd_intflag_reg_t;
+typedef uint8_t  hri_slcd_status_reg_t;
+
+static inline void hri_slcd_wait_for_sync(const void *const hw, hri_slcd_syncbusy_reg_t reg)
+{
+	while (((Slcd *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_slcd_is_syncing(const void *const hw, hri_slcd_syncbusy_reg_t reg)
+{
+	return ((Slcd *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT;
+}
+
+static inline bool hri_slcd_get_INTFLAG_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST;
+}
+
+static inline bool hri_slcd_get_INTFLAG_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST;
+}
+
+static inline bool hri_slcd_get_interrupt_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O;
+}
+
+static inline bool hri_slcd_get_interrupt_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O;
+}
+
+static inline bool hri_slcd_get_interrupt_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O;
+}
+
+static inline bool hri_slcd_get_interrupt_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT;
+}
+
+static inline bool hri_slcd_get_interrupt_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST;
+}
+
+static inline bool hri_slcd_get_interrupt_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST;
+}
+
+static inline hri_slcd_intflag_reg_t hri_slcd_get_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_intflag_reg_t hri_slcd_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_slcd_clear_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask)
+{
+	((Slcd *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_slcd_set_INTEN_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC0O) >> SLCD_INTENSET_FC0O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC0O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O;
+}
+
+static inline void hri_slcd_set_INTEN_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC1O) >> SLCD_INTENSET_FC1O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC1O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O;
+}
+
+static inline void hri_slcd_set_INTEN_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC2O) >> SLCD_INTENSET_FC2O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC2O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O;
+}
+
+static inline void hri_slcd_set_INTEN_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT;
+}
+
+static inline bool hri_slcd_get_INTEN_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDRT) >> SLCD_INTENSET_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_VLCDRT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT;
+}
+
+static inline void hri_slcd_set_INTEN_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST;
+}
+
+static inline bool hri_slcd_get_INTEN_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDST) >> SLCD_INTENSET_VLCDST_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_VLCDST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST;
+}
+
+static inline void hri_slcd_set_INTEN_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST;
+}
+
+static inline bool hri_slcd_get_INTEN_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_PRST) >> SLCD_INTENSET_PRST_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_PRST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST;
+}
+
+static inline void hri_slcd_set_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	((Slcd *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_slcd_intenset_reg_t hri_slcd_get_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_intenset_reg_t hri_slcd_read_INTEN_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->INTENSET.reg;
+}
+
+static inline void hri_slcd_write_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t data)
+{
+	((Slcd *)hw)->INTENSET.reg = data;
+	((Slcd *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_slcd_clear_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	((Slcd *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_slcd_get_STATUS_VLCDR_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDR) >> SLCD_STATUS_VLCDR_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_PRUN_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_PRUN) >> SLCD_STATUS_PRUN_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_VLCDS_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDS) >> SLCD_STATUS_VLCDS_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_CMWRBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_CMWRBUSY) >> SLCD_STATUS_CMWRBUSY_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_ACMBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ACMBUSY) >> SLCD_STATUS_ACMBUSY_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_ABMBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ABMBUSY) >> SLCD_STATUS_ABMBUSY_Pos;
+}
+
+static inline hri_slcd_status_reg_t hri_slcd_get_STATUS_reg(const void *const hw, hri_slcd_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_status_reg_t hri_slcd_read_STATUS_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->STATUS.reg;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_SWRST) >> SLCD_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_ENABLE) >> SLCD_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_CTRLD_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_CTRLD) >> SLCD_SYNCBUSY_CTRLD_Pos;
+}
+
+static inline hri_slcd_syncbusy_reg_t hri_slcd_get_SYNCBUSY_reg(const void *const hw, hri_slcd_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_syncbusy_reg_t hri_slcd_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_slcd_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_SWRST;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_SWRST) >> SLCD_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_ENABLE) >> SLCD_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_ENABLE;
+	tmp |= value << SLCD_CTRLA_ENABLE_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_WMOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_WMOD) >> SLCD_CTRLA_WMOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_WMOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_WMOD;
+	tmp |= value << SLCD_CTRLA_WMOD_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RUNSTDBY) >> SLCD_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_RUNSTDBY;
+	tmp |= value << SLCD_CTRLA_RUNSTDBY_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_XVLCD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_XVLCD) >> SLCD_CTRLA_XVLCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_XVLCD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_XVLCD;
+	tmp |= value << SLCD_CTRLA_XVLCD_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DUTY(mask)) >> SLCD_CTRLA_DUTY_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_DUTY_Msk;
+	tmp |= SLCD_CTRLA_DUTY(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DUTY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DUTY_Msk) >> SLCD_CTRLA_DUTY_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRESC(mask)) >> SLCD_CTRLA_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_PRESC_Msk;
+	tmp |= SLCD_CTRLA_PRESC(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRESC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRESC_Msk) >> SLCD_CTRLA_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_CKDIV(mask)) >> SLCD_CTRLA_CKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_CKDIV_Msk;
+	tmp |= SLCD_CTRLA_CKDIV(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_CKDIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_CKDIV_Msk) >> SLCD_CTRLA_CKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_BIAS(mask)) >> SLCD_CTRLA_BIAS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_BIAS_Msk;
+	tmp |= SLCD_CTRLA_BIAS(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_BIAS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_BIAS_Msk) >> SLCD_CTRLA_BIAS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRF(mask)) >> SLCD_CTRLA_PRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_PRF_Msk;
+	tmp |= SLCD_CTRLA_PRF(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRF_Msk) >> SLCD_CTRLA_PRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DMFCS(mask)) >> SLCD_CTRLA_DMFCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_DMFCS_Msk;
+	tmp |= SLCD_CTRLA_DMFCS(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DMFCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DMFCS_Msk) >> SLCD_CTRLA_DMFCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RRF(mask)) >> SLCD_CTRLA_RRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_RRF_Msk;
+	tmp |= SLCD_CTRLA_RRF(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_RRF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RRF_Msk) >> SLCD_CTRLA_RRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg = data;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_reg(const void *const hw)
+{
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	return ((Slcd *)hw)->CTRLA.reg;
+}
+
+static inline void hri_slcd_set_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLB_BBEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBEN) >> SLCD_CTRLB_BBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_BBEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_BBEN;
+	tmp |= value << SLCD_CTRLB_BBEN_Pos;
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLB_LREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LREN) >> SLCD_CTRLB_LREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_LREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_LREN;
+	tmp |= value << SLCD_CTRLB_LREN_Pos;
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBD(mask)) >> SLCD_CTRLB_BBD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_BBD_Msk;
+	tmp |= SLCD_CTRLB_BBD(data);
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_BBD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBD_Msk) >> SLCD_CTRLB_BBD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LRD(mask)) >> SLCD_CTRLB_LRD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_LRD_Msk;
+	tmp |= SLCD_CTRLB_LRD(data);
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_LRD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LRD_Msk) >> SLCD_CTRLB_LRD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CTRLB.reg;
+}
+
+static inline void hri_slcd_set_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_CLEAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CLEAR) >> SLCD_CTRLC_CLEAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_CLEAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_CLEAR;
+	tmp |= value << SLCD_CTRLC_CLEAR_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_LOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LOCK) >> SLCD_CTRLC_LOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_LOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_LOCK;
+	tmp |= value << SLCD_CTRLC_LOCK_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_ABMEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_ABMEN) >> SLCD_CTRLC_ABMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_ABMEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_ABMEN;
+	tmp |= value << SLCD_CTRLC_ABMEN_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_ACMEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_ACMEN) >> SLCD_CTRLC_ACMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_ACMEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_ACMEN;
+	tmp |= value << SLCD_CTRLC_ACMEN_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CTST(mask)) >> SLCD_CTRLC_CTST_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_CTST_Msk;
+	tmp |= SLCD_CTRLC_CTST(data);
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_CTST_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CTST_Msk) >> SLCD_CTRLC_CTST_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LPPM(mask)) >> SLCD_CTRLC_LPPM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_LPPM_Msk;
+	tmp |= SLCD_CTRLC_LPPM(data);
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_LPPM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LPPM_Msk) >> SLCD_CTRLC_LPPM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CTRLC.reg;
+}
+
+static inline void hri_slcd_set_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_BLANK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_BLANK) >> SLCD_CTRLD_BLANK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_BLANK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_BLANK;
+	tmp |= value << SLCD_CTRLD_BLANK_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_BLINK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_BLINK) >> SLCD_CTRLD_BLINK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_BLINK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_BLINK;
+	tmp |= value << SLCD_CTRLD_BLINK_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_CSREN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_CSREN) >> SLCD_CTRLD_CSREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_CSREN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_CSREN;
+	tmp |= value << SLCD_CTRLD_CSREN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC0EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC0EN) >> SLCD_CTRLD_FC0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC0EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC0EN;
+	tmp |= value << SLCD_CTRLD_FC0EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC1EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC1EN) >> SLCD_CTRLD_FC1EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC1EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC1EN;
+	tmp |= value << SLCD_CTRLD_FC1EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC2EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC2EN) >> SLCD_CTRLD_FC2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC2EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC2EN;
+	tmp |= value << SLCD_CTRLD_FC2EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_DISPEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_DISPEN) >> SLCD_CTRLD_DISPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_DISPEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_DISPEN;
+	tmp |= value << SLCD_CTRLD_DISPEN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrld_reg_t hri_slcd_get_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	uint8_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg = data;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrld_reg_t hri_slcd_read_CTRLD_reg(const void *const hw)
+{
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	return ((Slcd *)hw)->CTRLD.reg;
+}
+
+static inline void hri_slcd_set_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC0OEO) >> SLCD_EVCTRL_FC0OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC0OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC0OEO;
+	tmp |= value << SLCD_EVCTRL_FC0OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC1OEO) >> SLCD_EVCTRL_FC1OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC1OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC1OEO;
+	tmp |= value << SLCD_EVCTRL_FC1OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC2OEO) >> SLCD_EVCTRL_FC2OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC2OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC2OEO;
+	tmp |= value << SLCD_EVCTRL_FC2OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_evctrl_reg_t hri_slcd_get_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_evctrl_reg_t hri_slcd_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_slcd_set_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC0_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_PB) >> SLCD_FC0_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC0_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= ~SLCD_FC0_PB;
+	tmp |= value << SLCD_FC0_PB_Pos;
+	((Slcd *)hw)->FC0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_OVF(mask)) >> SLCD_FC0_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= ~SLCD_FC0_OVF_Msk;
+	tmp |= SLCD_FC0_OVF(data);
+	((Slcd *)hw)->FC0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_OVF_Msk) >> SLCD_FC0_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC0.reg;
+}
+
+static inline void hri_slcd_set_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC1_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_PB) >> SLCD_FC1_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC1_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= ~SLCD_FC1_PB;
+	tmp |= value << SLCD_FC1_PB_Pos;
+	((Slcd *)hw)->FC1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_OVF(mask)) >> SLCD_FC1_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= ~SLCD_FC1_OVF_Msk;
+	tmp |= SLCD_FC1_OVF(data);
+	((Slcd *)hw)->FC1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_OVF_Msk) >> SLCD_FC1_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC1.reg;
+}
+
+static inline void hri_slcd_set_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC2_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_PB) >> SLCD_FC2_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC2_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= ~SLCD_FC2_PB;
+	tmp |= value << SLCD_FC2_PB_Pos;
+	((Slcd *)hw)->FC2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_OVF(mask)) >> SLCD_FC2_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= ~SLCD_FC2_OVF_Msk;
+	tmp |= SLCD_FC2_OVF(data);
+	((Slcd *)hw)->FC2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_OVF_Msk) >> SLCD_FC2_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC2.reg;
+}
+
+static inline void hri_slcd_set_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg |= SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp = (tmp & SLCD_LPENL_LPEN(mask)) >> SLCD_LPENL_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp &= ~SLCD_LPENL_LPEN_Msk;
+	tmp |= SLCD_LPENL_LPEN(data);
+	((Slcd *)hw)->LPENL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg &= ~SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg ^= SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_LPEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp = (tmp & SLCD_LPENL_LPEN_Msk) >> SLCD_LPENL_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->LPENL.reg;
+}
+
+static inline void hri_slcd_set_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg |= SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp = (tmp & SLCD_LPENH_LPEN(mask)) >> SLCD_LPENH_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp &= ~SLCD_LPENH_LPEN_Msk;
+	tmp |= SLCD_LPENH_LPEN(data);
+	((Slcd *)hw)->LPENH.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg &= ~SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg ^= SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_LPEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp = (tmp & SLCD_LPENH_LPEN_Msk) >> SLCD_LPENH_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->LPENH.reg;
+}
+
+static inline void hri_slcd_set_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg |= SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp = (tmp & SLCD_SDATAL0_SDATA(mask)) >> SLCD_SDATAL0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp &= ~SLCD_SDATAL0_SDATA_Msk;
+	tmp |= SLCD_SDATAL0_SDATA(data);
+	((Slcd *)hw)->SDATAL0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg &= ~SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg ^= SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp = (tmp & SLCD_SDATAL0_SDATA_Msk) >> SLCD_SDATAL0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL0.reg;
+}
+
+static inline void hri_slcd_set_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg |= SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp = (tmp & SLCD_SDATAH0_SDATA(mask)) >> SLCD_SDATAH0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp &= ~SLCD_SDATAH0_SDATA_Msk;
+	tmp |= SLCD_SDATAH0_SDATA(data);
+	((Slcd *)hw)->SDATAH0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg &= ~SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg ^= SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp = (tmp & SLCD_SDATAH0_SDATA_Msk) >> SLCD_SDATAH0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH0.reg;
+}
+
+static inline void hri_slcd_set_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg |= SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp = (tmp & SLCD_SDATAL1_SDATA(mask)) >> SLCD_SDATAL1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp &= ~SLCD_SDATAL1_SDATA_Msk;
+	tmp |= SLCD_SDATAL1_SDATA(data);
+	((Slcd *)hw)->SDATAL1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg &= ~SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg ^= SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp = (tmp & SLCD_SDATAL1_SDATA_Msk) >> SLCD_SDATAL1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL1.reg;
+}
+
+static inline void hri_slcd_set_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg |= SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp = (tmp & SLCD_SDATAH1_SDATA(mask)) >> SLCD_SDATAH1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp &= ~SLCD_SDATAH1_SDATA_Msk;
+	tmp |= SLCD_SDATAH1_SDATA(data);
+	((Slcd *)hw)->SDATAH1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg &= ~SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg ^= SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp = (tmp & SLCD_SDATAH1_SDATA_Msk) >> SLCD_SDATAH1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH1.reg;
+}
+
+static inline void hri_slcd_set_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg |= SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp = (tmp & SLCD_SDATAL2_SDATA(mask)) >> SLCD_SDATAL2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp &= ~SLCD_SDATAL2_SDATA_Msk;
+	tmp |= SLCD_SDATAL2_SDATA(data);
+	((Slcd *)hw)->SDATAL2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg &= ~SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg ^= SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp = (tmp & SLCD_SDATAL2_SDATA_Msk) >> SLCD_SDATAL2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL2.reg;
+}
+
+static inline void hri_slcd_set_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg |= SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp = (tmp & SLCD_SDATAH2_SDATA(mask)) >> SLCD_SDATAH2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp &= ~SLCD_SDATAH2_SDATA_Msk;
+	tmp |= SLCD_SDATAH2_SDATA(data);
+	((Slcd *)hw)->SDATAH2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg &= ~SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg ^= SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp = (tmp & SLCD_SDATAH2_SDATA_Msk) >> SLCD_SDATAH2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH2.reg;
+}
+
+static inline void hri_slcd_set_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg |= SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp = (tmp & SLCD_SDATAL3_SDATA(mask)) >> SLCD_SDATAL3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp &= ~SLCD_SDATAL3_SDATA_Msk;
+	tmp |= SLCD_SDATAL3_SDATA(data);
+	((Slcd *)hw)->SDATAL3.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg &= ~SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg ^= SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp = (tmp & SLCD_SDATAL3_SDATA_Msk) >> SLCD_SDATAL3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL3.reg;
+}
+
+static inline void hri_slcd_set_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg |= SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp = (tmp & SLCD_SDATAH3_SDATA(mask)) >> SLCD_SDATAH3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp &= ~SLCD_SDATAH3_SDATA_Msk;
+	tmp |= SLCD_SDATAH3_SDATA(data);
+	((Slcd *)hw)->SDATAH3.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg &= ~SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg ^= SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp = (tmp & SLCD_SDATAH3_SDATA_Msk) >> SLCD_SDATAH3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH3.reg;
+}
+
+static inline void hri_slcd_set_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg |= SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp = (tmp & SLCD_SDATAL4_SDATA(mask)) >> SLCD_SDATAL4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp &= ~SLCD_SDATAL4_SDATA_Msk;
+	tmp |= SLCD_SDATAL4_SDATA(data);
+	((Slcd *)hw)->SDATAL4.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg &= ~SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg ^= SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp = (tmp & SLCD_SDATAL4_SDATA_Msk) >> SLCD_SDATAL4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL4.reg;
+}
+
+static inline void hri_slcd_set_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg |= SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp = (tmp & SLCD_SDATAH4_SDATA(mask)) >> SLCD_SDATAH4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp &= ~SLCD_SDATAH4_SDATA_Msk;
+	tmp |= SLCD_SDATAH4_SDATA(data);
+	((Slcd *)hw)->SDATAH4.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg &= ~SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg ^= SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp = (tmp & SLCD_SDATAH4_SDATA_Msk) >> SLCD_SDATAH4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH4.reg;
+}
+
+static inline void hri_slcd_set_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg |= SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp = (tmp & SLCD_SDATAL5_SDATA(mask)) >> SLCD_SDATAL5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp &= ~SLCD_SDATAL5_SDATA_Msk;
+	tmp |= SLCD_SDATAL5_SDATA(data);
+	((Slcd *)hw)->SDATAL5.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg &= ~SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg ^= SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp = (tmp & SLCD_SDATAL5_SDATA_Msk) >> SLCD_SDATAL5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL5.reg;
+}
+
+static inline void hri_slcd_set_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg |= SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp = (tmp & SLCD_SDATAH5_SDATA(mask)) >> SLCD_SDATAH5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp &= ~SLCD_SDATAH5_SDATA_Msk;
+	tmp |= SLCD_SDATAH5_SDATA(data);
+	((Slcd *)hw)->SDATAH5.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg &= ~SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg ^= SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp = (tmp & SLCD_SDATAH5_SDATA_Msk) >> SLCD_SDATAH5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH5.reg;
+}
+
+static inline void hri_slcd_set_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg |= SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp = (tmp & SLCD_SDATAL6_SDATA(mask)) >> SLCD_SDATAL6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp &= ~SLCD_SDATAL6_SDATA_Msk;
+	tmp |= SLCD_SDATAL6_SDATA(data);
+	((Slcd *)hw)->SDATAL6.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg &= ~SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg ^= SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp = (tmp & SLCD_SDATAL6_SDATA_Msk) >> SLCD_SDATAL6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL6.reg;
+}
+
+static inline void hri_slcd_set_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg |= SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp = (tmp & SLCD_SDATAH6_SDATA(mask)) >> SLCD_SDATAH6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp &= ~SLCD_SDATAH6_SDATA_Msk;
+	tmp |= SLCD_SDATAH6_SDATA(data);
+	((Slcd *)hw)->SDATAH6.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg &= ~SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg ^= SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp = (tmp & SLCD_SDATAH6_SDATA_Msk) >> SLCD_SDATAH6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH6.reg;
+}
+
+static inline void hri_slcd_set_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg |= SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp = (tmp & SLCD_SDATAL7_SDATA(mask)) >> SLCD_SDATAL7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp &= ~SLCD_SDATAL7_SDATA_Msk;
+	tmp |= SLCD_SDATAL7_SDATA(data);
+	((Slcd *)hw)->SDATAL7.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg &= ~SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg ^= SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp = (tmp & SLCD_SDATAL7_SDATA_Msk) >> SLCD_SDATAL7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL7.reg;
+}
+
+static inline void hri_slcd_set_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg |= SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp = (tmp & SLCD_SDATAH7_SDATA(mask)) >> SLCD_SDATAH7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp &= ~SLCD_SDATAH7_SDATA_Msk;
+	tmp |= SLCD_SDATAH7_SDATA(data);
+	((Slcd *)hw)->SDATAH7.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg &= ~SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg ^= SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp = (tmp & SLCD_SDATAH7_SDATA_Msk) >> SLCD_SDATAH7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH7.reg;
+}
+
+static inline void hri_slcd_set_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_BCFG_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_MODE) >> SLCD_BCFG_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_BCFG_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_MODE;
+	tmp |= value << SLCD_BCFG_MODE_Pos;
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_FCS(mask)) >> SLCD_BCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_FCS_Msk;
+	tmp |= SLCD_BCFG_FCS(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_FCS_Msk) >> SLCD_BCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS0(mask)) >> SLCD_BCFG_BSS0_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_BSS0_Msk;
+	tmp |= SLCD_BCFG_BSS0(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS0_Msk) >> SLCD_BCFG_BSS0_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS1(mask)) >> SLCD_BCFG_BSS1_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_BSS1_Msk;
+	tmp |= SLCD_BCFG_BSS1(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS1_Msk) >> SLCD_BCFG_BSS1_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->BCFG.reg;
+}
+
+static inline void hri_slcd_set_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CSRCFG_DIR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DIR) >> SLCD_CSRCFG_DIR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_DIR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_DIR;
+	tmp |= value << SLCD_CSRCFG_DIR_Pos;
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_FCS(mask)) >> SLCD_CSRCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_FCS_Msk;
+	tmp |= SLCD_CSRCFG_FCS(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_FCS_Msk) >> SLCD_CSRCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_SIZE(mask)) >> SLCD_CSRCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_SIZE_Msk;
+	tmp |= SLCD_CSRCFG_SIZE(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_SIZE_Msk) >> SLCD_CSRCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DATA(mask)) >> SLCD_CSRCFG_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_DATA_Msk;
+	tmp |= SLCD_CSRCFG_DATA(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DATA_Msk) >> SLCD_CSRCFG_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CSRCFG.reg;
+}
+
+static inline void hri_slcd_set_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CMCFG_DEC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_DEC) >> SLCD_CMCFG_DEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_DEC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= ~SLCD_CMCFG_DEC;
+	tmp |= value << SLCD_CMCFG_DEC_Pos;
+	((Slcd *)hw)->CMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_NSEG(mask)) >> SLCD_CMCFG_NSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= ~SLCD_CMCFG_NSEG_Msk;
+	tmp |= SLCD_CMCFG_NSEG(data);
+	((Slcd *)hw)->CMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_NSEG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_NSEG_Msk) >> SLCD_CMCFG_NSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMCFG.reg;
+}
+
+static inline void hri_slcd_set_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_ACMCFG_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_MODE) >> SLCD_ACMCFG_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_MODE;
+	tmp |= value << SLCD_ACMCFG_MODE_Pos;
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NCOM(mask)) >> SLCD_ACMCFG_NCOM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NCOM_Msk;
+	tmp |= SLCD_ACMCFG_NCOM(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NCOM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NCOM_Msk) >> SLCD_ACMCFG_NCOM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDIG(mask)) >> SLCD_ACMCFG_NDIG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NDIG_Msk;
+	tmp |= SLCD_ACMCFG_NDIG(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDIG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDIG_Msk) >> SLCD_ACMCFG_NDIG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STEPS(mask)) >> SLCD_ACMCFG_STEPS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_STEPS_Msk;
+	tmp |= SLCD_ACMCFG_STEPS(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STEPS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STEPS_Msk) >> SLCD_ACMCFG_STEPS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDROW(mask)) >> SLCD_ACMCFG_NDROW_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NDROW_Msk;
+	tmp |= SLCD_ACMCFG_NDROW(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDROW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDROW_Msk) >> SLCD_ACMCFG_NDROW_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STSEG(mask)) >> SLCD_ACMCFG_STSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_STSEG_Msk;
+	tmp |= SLCD_ACMCFG_STSEG(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STSEG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STSEG_Msk) >> SLCD_ACMCFG_STSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_FCS(mask)) >> SLCD_ACMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_FCS_Msk;
+	tmp |= SLCD_ACMCFG_FCS(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_FCS_Msk) >> SLCD_ACMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->ACMCFG.reg;
+}
+
+static inline void hri_slcd_set_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_FCS(mask)) >> SLCD_ABMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= ~SLCD_ABMCFG_FCS_Msk;
+	tmp |= SLCD_ABMCFG_FCS(data);
+	((Slcd *)hw)->ABMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_FCS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_FCS_Msk) >> SLCD_ABMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_SIZE(mask)) >> SLCD_ABMCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= ~SLCD_ABMCFG_SIZE_Msk;
+	tmp |= SLCD_ABMCFG_SIZE(data);
+	((Slcd *)hw)->ABMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_SIZE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_SIZE_Msk) >> SLCD_ABMCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->ABMCFG.reg;
+}
+
+static inline void hri_slcd_set_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg |= SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp = (tmp & SLCD_CMDMASK_SDMASK(mask)) >> SLCD_CMDMASK_SDMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp &= ~SLCD_CMDMASK_SDMASK_Msk;
+	tmp |= SLCD_CMDMASK_SDMASK(data);
+	((Slcd *)hw)->CMDMASK.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg &= ~SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg ^= SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_SDMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp = (tmp & SLCD_CMDMASK_SDMASK_Msk) >> SLCD_CMDMASK_SDMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMDMASK.reg;
+}
+
+static inline void hri_slcd_set_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_SINDEX(mask)) >> SLCD_CMINDEX_SINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= ~SLCD_CMINDEX_SINDEX_Msk;
+	tmp |= SLCD_CMINDEX_SINDEX(data);
+	((Slcd *)hw)->CMINDEX.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_SINDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_SINDEX_Msk) >> SLCD_CMINDEX_SINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_CINDEX(mask)) >> SLCD_CMINDEX_CINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= ~SLCD_CMINDEX_CINDEX_Msk;
+	tmp |= SLCD_CMINDEX_CINDEX(data);
+	((Slcd *)hw)->CMINDEX.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_CINDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_CINDEX_Msk) >> SLCD_CMINDEX_CINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMINDEX.reg;
+}
+
+static inline void hri_slcd_write_ISDATA_reg(const void *const hw, hri_slcd_isdata_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ISDATA.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_write_CMDATA_reg(const void *const hw, hri_slcd_cmdata_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDATA.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SLCD_L22_H_INCLUDED */
+#endif /* _SAML22_SLCD_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_supc_l22.h b/Smol Watch Project/My Project/hri/hri_supc_l22.h
new file mode 100644
index 0000000..9488ef0
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_supc_l22.h	
@@ -0,0 +1,2532 @@
+/**
+ * \file
+ *
+ * \brief SAM SUPC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SUPC_COMPONENT_
+#ifndef _HRI_SUPC_L22_H_INCLUDED_
+#define _HRI_SUPC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
+#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SUPC_CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_supc_bbps_reg_t;
+typedef uint32_t hri_supc_bkin_reg_t;
+typedef uint32_t hri_supc_bkout_reg_t;
+typedef uint32_t hri_supc_bod12_reg_t;
+typedef uint32_t hri_supc_bod33_reg_t;
+typedef uint32_t hri_supc_intenset_reg_t;
+typedef uint32_t hri_supc_intflag_reg_t;
+typedef uint32_t hri_supc_status_reg_t;
+typedef uint32_t hri_supc_vref_reg_t;
+typedef uint32_t hri_supc_vreg_reg_t;
+
+static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	((Supc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY;
+}
+
+static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY;
+}
+
+static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
+{
+	((Supc *)hw)->INTENSET.reg = data;
+	((Supc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos;
+}
+
+static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->STATUS.reg;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKIN.reg;
+}
+
+static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ENABLE;
+	tmp |= value << SUPC_BOD33_ENABLE_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_HYST;
+	tmp |= value << SUPC_BOD33_HYST_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_STDBYCFG;
+	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNSTDBY;
+	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNBKUP;
+	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTCFG;
+	tmp |= value << SUPC_BOD33_ACTCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_VMON;
+	tmp |= value << SUPC_BOD33_VMON_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTION_Msk;
+	tmp |= SUPC_BOD33_ACTION(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_PSEL_Msk;
+	tmp |= SUPC_BOD33_PSEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_LEVEL_Msk;
+	tmp |= SUPC_BOD33_LEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk;
+	tmp |= SUPC_BOD33_BKUPLEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD33.reg;
+}
+
+static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ENABLE;
+	tmp |= value << SUPC_BOD12_ENABLE_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_HYST;
+	tmp |= value << SUPC_BOD12_HYST_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_STDBYCFG;
+	tmp |= value << SUPC_BOD12_STDBYCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_RUNSTDBY;
+	tmp |= value << SUPC_BOD12_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTCFG;
+	tmp |= value << SUPC_BOD12_ACTCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTION_Msk;
+	tmp |= SUPC_BOD12_ACTION(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_PSEL_Msk;
+	tmp |= SUPC_BOD12_PSEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_LEVEL_Msk;
+	tmp |= SUPC_BOD12_LEVEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD12.reg;
+}
+
+static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_ENABLE;
+	tmp |= value << SUPC_VREG_ENABLE_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_STDBYPL0;
+	tmp |= value << SUPC_VREG_STDBYPL0_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_RUNSTDBY;
+	tmp |= value << SUPC_VREG_RUNSTDBY_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_LPEFF;
+	tmp |= value << SUPC_VREG_LPEFF_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_SEL_Msk;
+	tmp |= SUPC_VREG_SEL(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSVSTEP_Msk;
+	tmp |= SUPC_VREG_VSVSTEP(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSPER_Msk;
+	tmp |= SUPC_VREG_VSPER(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREG.reg;
+}
+
+static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSEN;
+	tmp |= value << SUPC_VREF_TSEN_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_VREFOE;
+	tmp |= value << SUPC_VREF_VREFOE_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSSEL;
+	tmp |= value << SUPC_VREF_TSSEL_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_RUNSTDBY;
+	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_ONDEMAND;
+	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_SEL_Msk;
+	tmp |= SUPC_VREF_SEL(data);
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREF.reg;
+}
+
+static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_WAKEEN;
+	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_PSOKEN;
+	tmp |= value << SUPC_BBPS_PSOKEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_CONF_Msk;
+	tmp |= SUPC_BBPS_CONF(data);
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BBPS.reg;
+}
+
+static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_EN_Msk;
+	tmp |= SUPC_BKOUT_EN(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_CLR_Msk;
+	tmp |= SUPC_BKOUT_CLR(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_SET_Msk;
+	tmp |= SUPC_BKOUT_SET(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
+	tmp |= SUPC_BKOUT_RTCTGL(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKOUT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SUPC_L22_H_INCLUDED */
+#endif /* _SAML22_SUPC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_systemcontrol_l22.h b/Smol Watch Project/My Project/hri/hri_systemcontrol_l22.h
new file mode 100644
index 0000000..9553d51
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_systemcontrol_l22.h	
@@ -0,0 +1,498 @@
+/**
+ * \file
+ *
+ * \brief SAM SystemControl
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SystemControl_COMPONENT_
+#ifndef _HRI_SystemControl_L22_H_INCLUDED_
+#define _HRI_SystemControl_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
+#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SystemControl_CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systemcontrol_aircr_reg_t;
+typedef uint32_t hri_systemcontrol_ccr_reg_t;
+typedef uint32_t hri_systemcontrol_cpuid_reg_t;
+typedef uint32_t hri_systemcontrol_dfsr_reg_t;
+typedef uint32_t hri_systemcontrol_icsr_reg_t;
+typedef uint32_t hri_systemcontrol_scr_reg_t;
+typedef uint32_t hri_systemcontrol_shcsr_reg_t;
+typedef uint32_t hri_systemcontrol_shpr2_reg_t;
+typedef uint32_t hri_systemcontrol_shpr3_reg_t;
+typedef uint32_t hri_systemcontrol_vtor_reg_t;
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const             hw,
+                                                                                    hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const             hw,
+                                                                                   hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const             hw,
+                                                                            hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CPUID.reg;
+}
+
+static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3;
+}
+
+static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9;
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_ccr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CCR.reg;
+}
+
+static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_icsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ICSR.reg;
+}
+
+static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_vtor_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->VTOR.reg;
+}
+
+static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_aircr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->AIRCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_scr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR2.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR3.reg;
+}
+
+static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shcsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHCSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHCSR.reg;
+}
+
+static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_dfsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->DFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->DFSR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SystemControl_L22_H_INCLUDED */
+#endif /* _SAML22_SystemControl_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_systick_l22.h b/Smol Watch Project/My Project/hri/hri_systick_l22.h
new file mode 100644
index 0000000..aa09233
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_systick_l22.h	
@@ -0,0 +1,219 @@
+/**
+ * \file
+ *
+ * \brief SAM SysTick
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SysTick_COMPONENT_
+#ifndef _HRI_SysTick_L22_H_INCLUDED_
+#define _HRI_SysTick_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SysTick_CRITICAL_SECTIONS)
+#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SysTick_CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systick_calib_reg_t;
+typedef uint32_t hri_systick_csr_reg_t;
+typedef uint32_t hri_systick_cvr_reg_t;
+typedef uint32_t hri_systick_rvr_reg_t;
+
+static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30;
+}
+
+static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CALIB.reg;
+}
+
+static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CSR.reg;
+}
+
+static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->RVR.reg;
+}
+
+static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CVR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SysTick_L22_H_INCLUDED */
+#endif /* _SAML22_SysTick_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_tc_l22.h b/Smol Watch Project/My Project/hri/hri_tc_l22.h
new file mode 100644
index 0000000..8fab128
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_tc_l22.h	
@@ -0,0 +1,2899 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TC_COMPONENT_
+#ifndef _HRI_TC_L22_H_INCLUDED_
+#define _HRI_TC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tccount16_cc_reg_t;
+typedef uint16_t hri_tccount16_ccbuf_reg_t;
+typedef uint16_t hri_tccount16_count_reg_t;
+typedef uint32_t hri_tc_ctrla_reg_t;
+typedef uint32_t hri_tc_syncbusy_reg_t;
+typedef uint32_t hri_tccount32_cc_reg_t;
+typedef uint32_t hri_tccount32_ccbuf_reg_t;
+typedef uint32_t hri_tccount32_count_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_drvctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+typedef uint8_t  hri_tc_wave_reg_t;
+typedef uint8_t  hri_tccount8_cc_reg_t;
+typedef uint8_t  hri_tccount8_ccbuf_reg_t;
+typedef uint8_t  hri_tccount8_count_reg_t;
+typedef uint8_t  hri_tccount8_per_reg_t;
+typedef uint8_t  hri_tccount8_perbuf_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = data;
+	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ONDEMAND;
+	tmp |= value << TC_CTRLA_ONDEMAND_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ALOCK;
+	tmp |= value << TC_CTRLA_ALOCK_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN0;
+	tmp |= value << TC_CTRLA_CAPTEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN1;
+	tmp |= value << TC_CTRLA_CAPTEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN0;
+	tmp |= value << TC_CTRLA_COPEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN1;
+	tmp |= value << TC_CTRLA_COPEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	return ((Tc *)hw)->COUNT16.CTRLA.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.EVCTRL.reg;
+}
+
+static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= ~TC_WAVE_WAVEGEN_Msk;
+	tmp |= TC_WAVE_WAVEGEN(data);
+	((Tc *)hw)->COUNT16.WAVE.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.WAVE.reg;
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN0;
+	tmp |= value << TC_DRVCTRL_INVEN0_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN1;
+	tmp |= value << TC_DRVCTRL_INVEN1_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                              hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index,
+                                                            hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const         hw,
+                                                                          hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
+	tmp |= TC_COUNT8_PERBUF_PERBUF(data);
+	((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const         hw,
+                                                                    hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.PERBUF.reg;
+}
+
+static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT8_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                  hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+}
+
+static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT16_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+}
+
+static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT32_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b)
+#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b)
+#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b)
+#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b)
+#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b)
+#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a)
+#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b)
+#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b)
+#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b)
+#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b)
+#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b)
+#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a)
+#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a)
+#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b)
+#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b)
+#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b)
+#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b)
+#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b)
+#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_L22_H_INCLUDED */
+#endif /* _SAML22_TC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_tcc_l22.h b/Smol Watch Project/My Project/hri/hri_tcc_l22.h
new file mode 100644
index 0000000..c10442a
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_tcc_l22.h	
@@ -0,0 +1,9462 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TCC_COMPONENT_
+#ifndef _HRI_TCC_L22_H_INCLUDED_
+#define _HRI_TCC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattbuf_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccbuf_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perbuf_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+}
+
+static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_MSYNC;
+	tmp |= value << TCC_CTRLA_MSYNC_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_DMAOS;
+	tmp |= value << TCC_CTRLA_DMAOS_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKPRESC;
+	tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKPRESC;
+	tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHER_Msk;
+	tmp |= TCC_PER_DITH4_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHER_Msk;
+	tmp |= TCC_PER_DITH5_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHER_Msk;
+	tmp |= TCC_PER_DITH6_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHER_Msk;
+	tmp |= TCC_CC_DITH4_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHER_Msk;
+	tmp |= TCC_CC_DITH5_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHER_Msk;
+	tmp |= TCC_CC_DITH6_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB0;
+	tmp |= value << TCC_PATTBUF_PGEB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB1;
+	tmp |= value << TCC_PATTBUF_PGEB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB2;
+	tmp |= value << TCC_PATTBUF_PGEB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB3;
+	tmp |= value << TCC_PATTBUF_PGEB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB4;
+	tmp |= value << TCC_PATTBUF_PGEB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB5;
+	tmp |= value << TCC_PATTBUF_PGEB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB6;
+	tmp |= value << TCC_PATTBUF_PGEB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB7;
+	tmp |= value << TCC_PATTBUF_PGEB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB0;
+	tmp |= value << TCC_PATTBUF_PGVB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB1;
+	tmp |= value << TCC_PATTBUF_PGVB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB2;
+	tmp |= value << TCC_PATTBUF_PGVB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB3;
+	tmp |= value << TCC_PATTBUF_PGVB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB4;
+	tmp |= value << TCC_PATTBUF_PGVB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB5;
+	tmp |= value << TCC_PATTBUF_PGVB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB6;
+	tmp |= value << TCC_PATTBUF_PGVB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB7;
+	tmp |= value << TCC_PATTBUF_PGVB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTBUF.reg;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERBUF.reg;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_L22_H_INCLUDED */
+#endif /* _SAML22_TCC_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_trng_l22.h b/Smol Watch Project/My Project/hri/hri_trng_l22.h
new file mode 100644
index 0000000..8aad3ac
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_trng_l22.h	
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM TRNG
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TRNG_COMPONENT_
+#ifndef _HRI_TRNG_L22_H_INCLUDED_
+#define _HRI_TRNG_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
+#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TRNG_CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_trng_data_reg_t;
+typedef uint8_t  hri_trng_ctrla_reg_t;
+typedef uint8_t  hri_trng_evctrl_reg_t;
+typedef uint8_t  hri_trng_intenset_reg_t;
+typedef uint8_t  hri_trng_intflag_reg_t;
+
+static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	((Trng *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
+}
+
+static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+	} else {
+		((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+	}
+}
+
+static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTENSET.reg;
+}
+
+static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
+{
+	((Trng *)hw)->INTENSET.reg = data;
+	((Trng *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Trng *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->DATA.reg;
+}
+
+static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_ENABLE;
+	tmp |= value << TRNG_CTRLA_ENABLE_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_RUNSTDBY;
+	tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->CTRLA.reg;
+}
+
+static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= ~TRNG_EVCTRL_DATARDYEO;
+	tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
+	((Trng *)hw)->EVCTRL.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Trng *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TRNG_L22_H_INCLUDED */
+#endif /* _SAML22_TRNG_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_usb_l22.h b/Smol Watch Project/My Project/hri/hri_usb_l22.h
new file mode 100644
index 0000000..57a9419
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_usb_l22.h	
@@ -0,0 +1,4713 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_USB_COMPONENT_
+#ifndef _HRI_USB_L22_H_INCLUDED_
+#define _HRI_USB_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usb_padcal_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdescriptordevice_extreg_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint32_t hri_usb_descadd_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptordevice_addr_reg_t;
+typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t;
+typedef uint8_t  hri_usb_ctrla_reg_t;
+typedef uint8_t  hri_usb_fsmstatus_reg_t;
+typedef uint8_t  hri_usb_qosctrl_reg_t;
+typedef uint8_t  hri_usb_syncbusy_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptordevice_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+
+static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const       hw,
+                                                                        hri_usb_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg = data;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw)
+{
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	return ((Usb *)hw)->DEVICE.CTRLA.reg;
+}
+
+static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->DEVICE.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DESCADD.reg;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.PADCAL.reg;
+}
+
+static inline void hri_usbdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_reg(const void *const           hw,
+                                                                       hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                       hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                           hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_get_STATUS_BK_reg(const void *const                hw,
+                                                                                 hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_L22_H_INCLUDED */
+#endif /* _SAML22_USB_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/hri/hri_wdt_l22.h b/Smol Watch Project/My Project/hri/hri_wdt_l22.h
new file mode 100644
index 0000000..4794b25
--- /dev/null
+++ b/Smol Watch Project/My Project/hri/hri_wdt_l22.h	
@@ -0,0 +1,617 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_WDT_COMPONENT_
+#ifndef _HRI_WDT_L22_H_INCLUDED_
+#define _HRI_WDT_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_wdt_syncbusy_reg_t;
+typedef uint8_t  hri_wdt_clear_reg_t;
+typedef uint8_t  hri_wdt_config_reg_t;
+typedef uint8_t  hri_wdt_ctrla_reg_t;
+typedef uint8_t  hri_wdt_ewctrl_reg_t;
+typedef uint8_t  hri_wdt_intenset_reg_t;
+typedef uint8_t  hri_wdt_intflag_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Wdt *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ENABLE;
+	tmp |= value << WDT_CTRLA_ENABLE_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_WEN;
+	tmp |= value << WDT_CTRLA_WEN_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ALWAYSON;
+	tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
+{
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	return ((Wdt *)hw)->CTRLA.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_L22_H_INCLUDED */
+#endif /* _SAML22_WDT_COMPONENT_ */
diff --git a/Smol Watch Project/My Project/main.c b/Smol Watch Project/My Project/main.c
new file mode 100644
index 0000000..27f7731
--- /dev/null
+++ b/Smol Watch Project/My Project/main.c	
@@ -0,0 +1,48 @@
+#include <atmel_start.h>
+#include "watch-library/watch.h"
+
+int main(void)
+{
+	atmel_start_init();
+	
+	Watch watch;
+	struct calendar_date_time date_time;
+	date_time.date.year = 2021;
+	date_time.date.month = 4;
+	date_time.date.day = 25;
+	date_time.time.hour = 4;
+	date_time.time.min = 0;
+	date_time.time.sec = 0;
+
+	watch_init(&watch);
+	watch_enable_led();
+	watch_enable_date_time();
+	watch_set_date_time(date_time);
+	watch_enable_digital_output(A0);
+	gpio_set_pin_level(A0, true);
+	watch_enable_i2c();
+	
+	uint8_t chipID = 0;
+	uint8_t ChipIdRegister = 0xD0;
+	watch_i2c_send(0x77, &ChipIdRegister, 1);
+	watch_i2c_receive(0x77, &chipID, 1);
+	if (chipID == 0x60) {
+		watch_set_led_green();
+	}
+
+	uint8_t last = date_time.time.sec;
+	
+	while (1) {
+		watch_get_date_time(&date_time);
+		if (date_time.time.sec != last) {
+			last = date_time.time.sec;
+			if (last % 2 == 0) {
+				watch_set_led_red();
+			} else {
+				watch_set_led_green();
+			}
+		}
+	}
+	
+	return 0;
+}
diff --git a/Smol Watch Project/My Project/sleep_manager/sleep_manager.c b/Smol Watch Project/My Project/sleep_manager/sleep_manager.c
new file mode 100644
index 0000000..d23bfc2
--- /dev/null
+++ b/Smol Watch Project/My Project/sleep_manager/sleep_manager.c	
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <sleep_manager.h>
+#include <hal_sleep.h>
+#include <utils_assert.h>
+
+/** Event structure used to subscribe to sleep events */
+static struct event sleepmgr_event;
+/** The list of ready-to-sleep callbacks */
+static struct list_descriptor ready_to_sleep_cbs;
+/** The list of prepare-to-sleep callbacks */
+static struct list_descriptor prepare_to_sleep_cbs;
+/** The list of wake up callbacks */
+static struct list_descriptor wake_up_cbs;
+
+static void sleepmgr_event_callback(event_id_t id, event_data_t data);
+
+/**
+ * \brief Initialize sleep manager
+ */
+void sleepmgr_init(void)
+{
+	event_subscribe(&sleepmgr_event, EVENT_PREPARE_TO_SLEEP_ID, sleepmgr_event_callback);
+	event_subscribe(&sleepmgr_event, EVENT_IS_READY_TO_SLEEP_ID, sleepmgr_event_callback);
+	event_subscribe(&sleepmgr_event, EVENT_WOKEN_UP_ID, sleepmgr_event_callback);
+}
+
+/**
+ * \brief Register sleep callback
+ */
+void sleepmgr_register_ready_to_sleep_callback(struct sleepmgr_ready_to_sleep_cb *const cb)
+{
+	ASSERT(cb);
+
+	list_insert_as_head(&ready_to_sleep_cbs, cb);
+}
+
+/**
+ * \brief Register wake up callback
+ */
+void sleepmgr_register_prepare_to_sleep_callback(struct sleepmgr_prepare_to_sleep_cb *const cb)
+{
+	ASSERT(cb);
+
+	list_insert_as_head(&prepare_to_sleep_cbs, cb);
+}
+
+/**
+ * \brief Register wake up callback
+ */
+void sleepmgr_register_wake_up_callback(struct sleepmgr_wake_up_cb *const cb)
+{
+	ASSERT(cb);
+
+	list_insert_as_head(&wake_up_cbs, cb);
+}
+
+/**
+ * \brief Go to sleep
+ */
+void sleepmgr_sleep(const uint8_t mode)
+{
+	event_post(EVENT_PREPARE_TO_SLEEP_ID, mode);
+	sleep(mode);
+}
+
+/**
+ * \brief Send wake-up notification
+ */
+void sleepmgr_wakeup(const enum sleepmgr_wakeup_source source)
+{
+	event_post(EVENT_WOKEN_UP_ID, source);
+}
+
+/**
+ * \brief Check if device is ready to sleep
+ */
+bool sleepmgr_is_ready_to_sleep(const uint8_t mode)
+{
+	struct sleepmgr_ready_to_sleep ready;
+
+	ready.ready = true;
+	ready.mode  = mode;
+
+	event_post(EVENT_IS_READY_TO_SLEEP_ID, (event_data_t)&ready);
+
+	return ready.ready;
+}
+
+/**
+ * \brief "Going to sleep" event callback
+ *
+ * \param[in] id The event ID to process
+ * \param[in] data Not used
+ */
+static void sleepmgr_event_callback(event_id_t id, event_data_t data)
+{
+	if (EVENT_IS_READY_TO_SLEEP_ID == id) {
+		struct sleepmgr_ready_to_sleep_cb *cur;
+		struct sleepmgr_ready_to_sleep *   ret_val = (struct sleepmgr_ready_to_sleep *)data;
+		struct sleepmgr_ready_to_sleep     ready;
+
+		for (cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_head(&ready_to_sleep_cbs); cur;
+		     cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_next_element(cur)) {
+			ready.mode  = ret_val->mode;
+			ready.ready = true;
+			cur->cb(&ready);
+			ret_val->ready &= ready.ready;
+		}
+	} else if (EVENT_WOKEN_UP_ID == id) {
+		struct sleepmgr_wake_up_cb *cur;
+
+		for (cur = (struct sleepmgr_wake_up_cb *)list_get_head(&wake_up_cbs); cur;
+		     cur = (struct sleepmgr_wake_up_cb *)list_get_next_element(cur)) {
+			cur->cb((const enum sleepmgr_wakeup_source)data);
+		}
+	} else if (EVENT_PREPARE_TO_SLEEP_ID == id) {
+		struct sleepmgr_prepare_to_sleep_cb *cur;
+
+		for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+		     cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_next_element(cur)) {
+			cur->cb(data);
+		}
+	}
+}
diff --git a/Smol Watch Project/My Project/sleep_manager/sleep_manager.h b/Smol Watch Project/My Project/sleep_manager/sleep_manager.h
new file mode 100644
index 0000000..bf7fd51
--- /dev/null
+++ b/Smol Watch Project/My Project/sleep_manager/sleep_manager.h	
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SLEEP_MANAGER_H_INCLUDED
+#define _SLEEP_MANAGER_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils_event.h>
+
+/**
+ * \brief Wake up sources.
+ */
+enum sleepmgr_wakeup_source { SM_WAKEUP_SOURCE_EXT_IRQ, SM_WAKEUP_SOURCE_IRQ };
+
+struct sleepmgr_ready_to_sleep;
+
+/**
+ * \brief The type of a callback called before going to sleep
+ */
+typedef void (*sleepmgr_ready_to_sleep_callback_t)(struct sleepmgr_ready_to_sleep *const ready);
+
+/**
+ * \brief The type of a callback called right before going to sleep
+ */
+typedef void (*sleepmgr_prepare_to_sleep_callback_t)(const uint8_t mode);
+
+/**
+ * \brief The type of a callback called after waking up
+ */
+typedef void (*sleepmgr_wake_up_callback_t)(const enum sleepmgr_wakeup_source source);
+
+/**
+ * \brief The is ready to sleep callback structure
+ */
+struct sleepmgr_ready_to_sleep_cb {
+	struct is_ready_to_sleep_service {
+		struct list_element elem; /*! The pointer to next callback */
+	} service;                    /*! For internal use only */
+	/*! The callback to be called to ask modules about thier active status */
+	sleepmgr_ready_to_sleep_callback_t cb;
+};
+
+/**
+ * \brief The prepare to sleep callback structure
+ */
+struct sleepmgr_prepare_to_sleep_cb {
+	struct prepare_to_sleep_service {
+		struct list_element elem; /*! The pointer to next callback */
+	} service;                    /*! For internal use only */
+	/*! The callback to be called right before going to sleep */
+	sleepmgr_prepare_to_sleep_callback_t cb;
+};
+
+/**
+ * \brief The wake up callback structure
+ */
+struct sleepmgr_wake_up_cb {
+	struct wake_up_service {
+		struct list_element elem; /*! The pointer to next callback */
+	} service;                    /*! For internal use only */
+	/*! The callback to be called after waking up */
+	sleepmgr_wake_up_callback_t cb;
+};
+
+/**
+ * \brief The structure used in ready to sleep callback
+ */
+struct sleepmgr_ready_to_sleep {
+	bool    ready; /*! Ready to sleep flag */
+	uint8_t mode;  /*! The sleep mode to be used */
+};
+
+/**
+ * \brief Initialize sleep manager
+ */
+void sleepmgr_init(void);
+
+/**
+ * \brief Register is ready to sleep callback
+ *
+ * \param[in] cb Callback to register
+ */
+void sleepmgr_register_ready_to_sleep_callback(struct sleepmgr_ready_to_sleep_cb *const cb);
+
+/**
+ * \brief Register wake up callback
+ *
+ * \param[in] cb Callback to register
+ */
+void sleepmgr_register_prepare_to_sleep_callback(struct sleepmgr_prepare_to_sleep_cb *const cb);
+
+/**
+ * \brief Register wake up callback
+ *
+ * \param[in] cb Callback to register
+ */
+void sleepmgr_register_wake_up_callback(struct sleepmgr_wake_up_cb *const cb);
+
+/**
+ * \brief Go to sleep
+ *
+ * \param[in] mode Sleep mode to use
+ */
+void sleepmgr_sleep(const uint8_t mode);
+
+/**
+ * \brief Send wake-up notification
+ */
+void sleepmgr_wakeup(const enum sleepmgr_wakeup_source source);
+
+/**
+ * \brief Check if device is ready to sleep
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return True if device is ready to sleep, false otherwise
+ */
+bool sleepmgr_is_ready_to_sleep(const uint8_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SLEEP_MANAGER_H_INCLUDED */
diff --git a/Smol Watch Project/My Project/sleep_manager_main.c b/Smol Watch Project/My Project/sleep_manager_main.c
new file mode 100644
index 0000000..2ffade9
--- /dev/null
+++ b/Smol Watch Project/My Project/sleep_manager_main.c	
@@ -0,0 +1,24 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#include "atmel_start.h"
+#include "sleep_manager_main.h"
+
+static struct sleepmgr_ready_to_sleep_cb sleepmgr_cb;
+
+static void sleep_cb(struct sleepmgr_ready_to_sleep *const ready)
+{
+	ready->ready = false;
+}
+
+void sleep_manager_init(void)
+{
+	sleepmgr_init();
+
+	sleepmgr_cb.cb = sleep_cb;
+	sleepmgr_register_ready_to_sleep_callback(&sleepmgr_cb);
+}
diff --git a/Smol Watch Project/My Project/sleep_manager_main.h b/Smol Watch Project/My Project/sleep_manager_main.h
new file mode 100644
index 0000000..41857a7
--- /dev/null
+++ b/Smol Watch Project/My Project/sleep_manager_main.h	
@@ -0,0 +1,23 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#ifndef SLEEP_MANAGER_MAIN_H
+#define SLEEP_MANAGER_MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include <sleep_manager.h>
+
+void sleep_manager_init(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SLEEP_MANAGER_MAIN_H
diff --git a/Smol Watch Project/My Project/watch-library/watch.c b/Smol Watch Project/My Project/watch-library/watch.c
new file mode 100644
index 0000000..154653b
--- /dev/null
+++ b/Smol Watch Project/My Project/watch-library/watch.c	
@@ -0,0 +1,98 @@
+/*
+ * watch.c
+ *
+ * Created: 4/25/2021 10:22:10 AM
+ *  Author: joeycastillo
+ */ 
+
+#include "watch.h"
+#include "driver_init.h"
+
+void watch_init(Watch *watch) {
+}
+
+void watch_enable_led() {
+	PWM_0_init();
+	pwm_set_parameters(&PWM_0, 10000, 0);
+	pwm_enable(&PWM_0);
+}
+
+void watch_disable_led() {
+	gpio_set_pin_function(RED, GPIO_PIN_FUNCTION_OFF);
+	gpio_set_pin_function(GREEN, GPIO_PIN_FUNCTION_OFF);
+
+	pwm_disable(&PWM_0);
+}
+
+void watch_set_led_color(uint16_t red, uint16_t green) {
+	TC3->COUNT16.CC[0].reg = red;
+	TC3->COUNT16.CC[1].reg = green;
+}
+
+void watch_set_led_red() {
+	watch_set_led_color(65535, 0);
+}
+
+void watch_set_led_green() {
+	watch_set_led_color(0, 65535);
+}
+
+void watch_enable_date_time() {
+	CALENDAR_0_init();
+	calendar_enable(&CALENDAR_0);
+}
+
+void watch_set_date_time(struct calendar_date_time date_time) {
+	calendar_set_date(&CALENDAR_0, &date_time.date);
+	calendar_set_time(&CALENDAR_0, &date_time.time);
+}
+
+void watch_get_date_time(struct calendar_date_time *date_time) {
+	calendar_get_date_time(&CALENDAR_0, date_time);
+}
+
+void watch_enable_analog(const uint8_t pin) {
+	ADC_0_init(); // todo: only call this once
+	switch (pin) {
+		case A0:
+		gpio_set_pin_function(A0, PINMUX_PB04B_ADC_AIN12);
+		break;
+		case A1:
+		gpio_set_pin_function(A1, PINMUX_PB01B_ADC_AIN9);
+		break;
+		case A2:
+		gpio_set_pin_function(A2, PINMUX_PB02B_ADC_AIN10);
+		break;
+		default:
+		return;
+	}
+	gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF);
+}
+
+void watch_enable_digital_input(const uint8_t pin) {
+	gpio_set_pin_direction(pin, GPIO_DIRECTION_IN);
+	gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+
+void watch_enable_digital_output(const uint8_t pin) {
+	gpio_set_pin_direction(pin, GPIO_DIRECTION_OUT);
+	gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+
+struct io_descriptor *I2C_0_io;
+
+void watch_enable_i2c() {
+	I2C_0_init();
+	i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_sync_enable(&I2C_0);
+}
+
+void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) {
+	i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+	io_write(I2C_0_io, buf, length);
+}
+
+void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) {
+	i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+	io_read(I2C_0_io, buf, length);
+}
diff --git a/Smol Watch Project/My Project/watch-library/watch.h b/Smol Watch Project/My Project/watch-library/watch.h
new file mode 100644
index 0000000..1894e6c
--- /dev/null
+++ b/Smol Watch Project/My Project/watch-library/watch.h	
@@ -0,0 +1,48 @@
+/*
+ * Watch.h
+ *
+ * Created: 4/25/2021 8:29:16 AM
+ *  Author: joeycastillo
+ */ 
+
+
+#ifndef WATCH_H_
+#define WATCH_H_
+#include <stdint.h>
+#include "hpl_calendar.h"
+
+#define WATCH_NUM_DISPLAYS (3)
+
+struct WatchDisplay {
+	uint8_t num_chars;
+	uint8_t* chars;
+};
+
+typedef struct Watch {
+	struct WatchDisplay displays[WATCH_NUM_DISPLAYS];
+} Watch;
+
+void watch_init(Watch *watch);
+
+void watch_enable_led();
+void watch_disable_led();
+void watch_set_led_color(uint16_t red, uint16_t green);
+void watch_set_led_red();
+void watch_set_led_green();
+
+void watch_enable_date_time();
+void watch_set_date_time(struct calendar_date_time date_time);
+void watch_get_date_time(struct calendar_date_time *date_time);
+
+void watch_enable_analog(const uint8_t pin);
+
+void watch_enable_digital_input(const uint8_t pin);
+void watch_enable_digital_output(const uint8_t pin);
+
+struct io_descriptor *I2C_0_io;
+
+void watch_enable_i2c();
+void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length);
+void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length);
+
+#endif /* WATCH_H_ */
\ No newline at end of file
diff --git a/Smol Watch Project/Smol Watch Baseline.atsln b/Smol Watch Project/Smol Watch Baseline.atsln
new file mode 100644
index 0000000..a424594
--- /dev/null
+++ b/Smol Watch Project/Smol Watch Baseline.atsln	
@@ -0,0 +1,22 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "My Project", "My Project\My Project.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal